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REVIEW 4 major objections 5 minor 15 references

Improved Prefetching Techniques for Linked Data Structures

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Linkey uses layout hints to prefetch linked data structures accurately.

desk verdict Solid hybrid prefetcher idea with a genuine design bug in the multi-child table-building algorithm and a curated IPC headline; deserves a review round with major revisions. read the letter →

arxiv 2505.21669 v1 pith:WYMJHX4B submitted 2025-05-27 cs.AR

Nikola Vuk Maruszewski This is my paper
classification cs.AR
keywords prefetchinglinkeddatastructurespointerchasinghardware-softwareco-designcontent-directedresourcelocalitymemoryhierarchy
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Memory latency is rising, and ordinary prefetchers struggle with pointer-chasing code because nodes are scattered in memory and access patterns are hard to predict. The paper introduces Linkey, a hardware-software cooperative prefetcher that learns the shape of a linked data structure from a few pieces of software-supplied metadata (node size, child-pointer offsets, and root addresses) plus memory responses. It then issues parallel prefetches for the children of the current node, covering multiple levels of the structure at once. The evaluation reports a geomean 13% reduction in L1-D misses, a 65.4% accuracy gain, and a 1.40% geomean IPC improvement on applicable benchmarks, which suggests a small hardware cost can make pointer-chasing workloads significantly faster.

What carries the argument

The mechanism is a set of three hardware tables: the Address Table (AT) stores virtual addresses of known LDS nodes, the Child Association Table (CAT) stores parent-child links together with the child-pointer offset index, and the Backup Fetch Queue (BFQ) holds child addresses not yet in the AT. Software supplies NodeSize, ChildOs (linking-pointer offsets), and root addresses; a key offset KeyO is learned at runtime. A CAM lookup on the AT identifies the current node, and a recursive traversal of CAT entries issues up to eight parallel prefetch requests, also draining the BFQ when the tables do not fill the buffer. On memory responses, child pointers are extracted at the specified offsets and inserted into the AT/CAT, letting the tables build asynchronously.

What would settle it

Run Linkey on a workload that relinks nodes frequently (e.g., a splay tree with Zipfian keys) or starts traversals from many different nodes, and compare L1-D miss rate and IPC against a striding baseline; a miss-rate increase would show the assumptions do not hold.

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Extended reading notes

Core claim

The central claim is that reference locality, combined with explicit layout metadata, is enough to prefetch linked data structures without speculating which values are pointers. Linkey maintains an Address Table (AT) of known node addresses, a Child Association Table (CAT) linking parents to children via specific child offsets, and a Backup Fetch Queue (BFQ) that stores child addresses found from memory responses. When a demand access hits an AT entry, Linkey fetches the key field and all child pointers of that node, then follows CAT entries to fetch grandchildren in parallel. Memory responses rebuild the tables asynchronously, so the prefetcher stays ahead of the core. In the evaluation, this design reduces miss rate by a geomean of 13% (up to 58.8%), increases accuracy by 65.4% geomean, and raises IPC by 1.40% geomean (up to 12.1%) on benchmarks where the structure is stable and root-centric.

Load-bearing premise

The scheme assumes child pointers change rarely and most traversals start from a small fixed set of roots; if either fails, the prefetches can pollute the cache and hurt performance.

Editorial extensions

If this is right

  • Programmers can accelerate pointer-chasing loops by adding one-time configuration instructions that specify node layout and roots, with no per-access changes.
  • On workloads with stable child pointers and root-centric traversals, Linkey reduces L1-D misses by a geomean of 13% and improves IPC by up to 12.1%.
  • Because Linkey never guesses pointer values, it avoids the cache pollution and security issues attributed to content-directed prefetchers while still fetching the right child nodes.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The AT/CAT design could plausibly extend to dynamic graphs by adding mutation-detection or software invalidation, a route the paper leaves for future work.
  • Linkey's accuracy over a striding baseline suggests that combining layout hints with temporal-stream prefetching could yield further gains on mixed pointer and array workloads.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The manuscript introduces Linkey, a hybrid hardware/software prefetcher for linked data structures (LDSs). Software provides node size, child-pointer offsets, and root addresses; hardware maintains an Address Table (AT), a Child Association Table (CAT), and a Backup Fetch Queue (BFQ) to learn and cache parent/child associations and issue prefetches for pointer-chasing traversals. The design is evaluated in the Sniper simulator against a striding prefetcher on 15 custom C++ benchmarks spanning linked lists, binary trees, red-black trees, splay trees, tries, octrees, and graphs. The reported headline results are a geomean 13% reduction in L1-D load misses, a 65.4% geomean increase in prefetch accuracy, and a 1.40% geomean IPC improvement on benchmarks where the authors deem Linkey applicable, with an all-benchmark geomean IPC change of 0.05%.

Significance. If the design and evaluation are correct, Linkey would be a useful addition to the LDS-prefetching literature: it uses a small amount of software metadata to avoid pointer-speculation, supports multiple child pointers, and is explicitly designed to exploit modern memory bandwidth by issuing several prefetches per invocation. The paper is also commendably candid about when the technique fails (splay trees, graph BFS), and it states its reference-locality assumptions clearly. However, the manuscript's central evaluation claim is weaker than the abstract suggests: the all-benchmark IPC geomean is essentially flat, and the 1.40% figure is obtained only after removing the two benchmark families that lose performance. In addition, there is no quantitative comparison against prior LDS prefetchers such as CDP, ECDP, DBP, jump-pointer, or correlation-based schemes, which the related-work chapter discusses at length. The design's stated multi-child support also contains an internal inconsistency in the table-building algorithm that, as written, prevents the CAT from being populated correctly for nodes with more than one child pointer.

major comments (4)
  1. [§3.2.2, Algorithm 3.2 and Tables 3.1–3.2] A simple fix is to enumerate ChildOs with an index `i` from 0 to |ChildOs|-1, compute the byte offset as ChildOs[i], and use `i` for `Parent.Children[i]` and for the CAT offset index, but as written the algorithm is internally inconsistent. This needs to be corrected and the affected pseudocode, table descriptions, and Figure 3.1 example reconciled.
  2. [§4.4.2, Figures 4.7–4.8 and abstract] The current framing overstates the headline performance benefit, even though the underlying miss-rate reduction of 13% is meaningful.
  3. [§4.4 and Chapter 5] The evaluation compares Linkey only against a striding prefetcher (`pre_simple`). The related-work chapter discusses CDP [15], ECDP [18], DBP [50], and jump-pointer prefetching [29,39,51] as the most relevant prior art, and the introduction argues that Linkey avoids the cache pollution of CDP-like schemes. Without quantitative comparison to at least one or two of these LDS-specific prefetchers on the same benchmarks and simulator, the claim that Linkey is an improvement in this problem space is not directly supported. Adding such comparisons, or at least a discussion of expected relative behavior on the same benchmark set, is needed to substantiate the novelty and advantages claimed in §1.1 and Chapter 5.
  4. [§3.1, assumptions (2) and (4)] The design relies on the assumption that most traversals start from a small set of roots and that non-pointer fields are accessed in the same order (KeyO). The splay-tree and graph-BFS results show that violating these assumptions causes cache pollution and IPC loss. The paper acknowledges this and suggests disabling Linkey on such workloads, but it does not quantify how often the assumptions hold in the claimed 'applicable benchmarks' beyond the custom suite. Since the 1.40% IPC claim is based on the applicable subset, the criteria for applicability should be specified more precisely than 'benchmarks where Linkey is applicable' (abstract, §1.1, conclusion) so that the claim is testable and reproducible.
minor comments (5)
  1. [Abstract and §1] The abstract contains a typo ('access patters are arbitrarily complex') and uses 'Linkey' without spacing; these were noted but do not affect the technical content.
  2. [§4.4.2] The text says 'decease' where 'decrease' is intended; similar small typographical errors appear elsewhere.
  3. [§4.4, Figure 4.4] The figure labels the geomean values as 0.74 (lookup), 1.03 (traversal), and 0.87 (aggregate); the text reports a 'geomean 13% reduction.' The 0.87 aggregate geomean corresponds to a 13% decrease, but the mismatch between 'decrease' language and normalized values may confuse readers; consider reporting both as percentages consistently.
  4. [§4.4.2 and Figure 4.8] The caption for Figure 4.8 says 'with graph bfs and Splay Tree benchmarks removed,' but the textual discussion in §4.4.2.1 explains the removal; the figure itself should also state the rationale in the caption to prevent the appearance of cherry-picking.
  5. [§2.3.2] The description of correlation prefetchers could be clearer about how spatio-temporal memory streaming [55,62] specifically handles pointer-chasing patterns; as written, the paragraph conflates temporal correlation with the LDS-specific approach.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: Linkey's design, tables, and results stand independently of the measured outcomes; the noted algorithmic and evaluation concerns are not circularity.

full rationale

The paper's derivation chain is self-contained. Linkey's core mechanism (AT/CAT/BFQ) is defined from software-supplied metadata (NodeSize, ChildOs, roots) and runtime pointer values; no output metric (miss count, IPC, accuracy) appears in the definition of these structures or in the algorithms that build them. The evaluation compares against an external striding prefetcher baseline in Sniper, and the reported gains are measurements, not quantities forced by construction. The configuration choice among three table sizes is standard design-space exploration, not a fitted parameter renamed as a prediction. The IPC claim restricted to 'benchmarks where Linkey is applicable' is justified by the paper's stated reference-locality assumptions (splay trees and BFS graphs violate them) rather than by definition of the metric. The paper contains no load-bearing self-citation or author-imported uniqueness theorem; related-work citations such as [56] supply benchmark code, not the central claim. Algorithm 3.2's apparent byte-offset/index confusion is an internal correctness bug, and the splay/graph slowdowns are acknowledged limitations, but neither constitutes circular reasoning.

Assumptions & free parameters 8 free parameters · 6 assumptions · 4 invented entities

The central claim depends on several domain assumptions (reference locality, small root sets, representative benchmarks) and on the simulator's ability to model memory responses. The only hand-fitted elements are the hardware table sizes and request limits, selected after inspecting results. The AT/CAT/BFQ are the proposed design, not unexplained entities; none has independent evidence outside this simulation.

free parameters (8)
  • AT size (entries) = 256
    Selected after sweeping 64, 256, and 1024 entries; the 256-entry table represents a 7.2KiB total hardware budget, about 10% of the L1 caches (Section 4.4.1.1). This is a post hoc design choice, not a prediction.
  • CAT size (entries) = 1024
    Selected with the 256-entry AT to balance performance and area; larger sizes improved results but were deemed too costly (Section 4.4.1).
  • BFQ size (entries) = 8
    Hard-coded in Sections 3.3 and 4.1; no sweep is reported.
  • Maximum child pointers = 8
    Width of ChildOs register; limits the trie benchmark to the 8 most common letters and may not fit all LDS node types (Section 4.1.1, 4.2.2.4).
  • Maximum node size = 4 KiB
    12-bit NodeSize/ChildOs offsets; limits applicability to nodes whose trailing child pointers lie within 4KiB of the node start (Section 4.1.1).
  • Number of roots = 4
    Four root registers with valid bits; hand-chosen, not swept (Section 4.1.1).
  • Prefetch output buffer cap = 8
    Issue loop stops when request buffer has 8 entries (Section 3.4); chosen to bound bandwidth use.
  • Prefetch requests per cycle = 2
    Cache controller issues two prefetch requests at a time to model increased memory bandwidth (Section 4.1); no sensitivity analysis.
assumptions (6)
  • ad hoc to paper Linked data structures have high reference locality: child pointers of nodes do not change often.
    Section 3.1, assumption 1. This is an optimization target, not a universal property; splay-tree and dynamic BST results show it can fail.
  • ad hoc to paper Most traversals start from a small set of roots, and roots are much hotter than other nodes.
    Section 3.1, assumption 2. The AT/CAT design and the exclusion of graph BFS from the headline IPC result depend on this assumption.
  • ad hoc to paper Traversal access patterns follow the same order of non-pointer fields, enabling KeyO to identify the key offset.
    Section 3.1, assumption 4 and Algorithm 3.1. When field order varies across traversals, the single KeyO register will mispredict the node start.
  • domain assumption Simulator magic instructions can expose memory response data to the prefetcher without changing performance conclusions.
    Section 4.1.1: 'simulator magic instructions are used to view memory response data... this is purely for simulation within Sniper.' No RTL or timing model verifies this.
  • domain assumption The Sniper simulator with parameters from [11] is representative of a modern x86-64 system.
    Section 4.1, Table 4.1. Results are not validated against real hardware or other simulators.
  • ad hoc to paper The seven custom benchmark families are representative of real-world linked-data-structure workloads.
    Section 4.2 defines the suite; the established Olden suite [7] is deferred to future work, so external representativeness is unestablished.
invented entities (4)
  • Address Table (AT)
    purpose: Stores the addresses and child-association indexes of known LDS nodes, enabling table-based parallel prefetching.
    Evaluated only in a modified Sniper simulation; no RTL, FPGA, or silicon implementation is provided.
  • Child Association Table (CAT)
    purpose: Records parent-child relationships between AT entries, keyed by child pointer offset.
    Simulated only; no independent hardware measurement.
  • Backup Fetch Queue (BFQ)
    purpose: Buffers child pointers discovered from memory responses to continue prefetching after AT/CAT entries are exhausted.
    Simulated only; its timing and interaction with the memory system are not validated in real hardware.
  • Linkey software interface (lds.reset, lds.set root, lds.add offset, lds.set size, lds.new traversal)
    purpose: Provides NodeSize, ChildOs, roots, and traversal markers from software to the prefetcher.
    Instruction semantics are defined in Table 4.2, but no compiler, binary, or ISA extension is implemented.

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Cite this review

Pith. "Pith review of Improved Prefetching Techniques for Linked Data Structures." pith.science (2026). https://pith.science/paper/WYMJHX4B

@misc{pith2026250521669,
  author       = {Pith},
  title        = {Pith review of: Improved Prefetching Techniques for Linked Data Structures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WYMJHX4B}},
  note         = {Machine review of arXiv:2505.21669}
}
abstract

With ever-increasing main memory stall times, we need novel techniques to reduce effective memory access latencies. Prefetching has been shown to be an effective solution, especially with contiguous data structures that follow the traditional principles of spatial and temporal locality. However, on linked data structures$-$made up of many nodes linked together with pointers$-$typical prefetchers struggle, failing to predict accesses as elements are arbitrarily scattered throughout memory and access patters are arbitrarily complex and hence difficult to predict. To remedy these issues, we introduce $\textit{Linkey}$, a novel prefetcher that utilizes hints from the programmer/compiler to cache layout information and accurately prefetch linked data structures. $\textit{Linkey}$ obtains substantial performance improvements over a striding baseline. We achieve a geomean 13% reduction in miss rate with a maximum improvement of 58.8%, and a 65.4% geomean increase in accuracy, with many benchmarks improving from 0%. On benchmarks where $\textit{Linkey}$ is applicable, we observe a geomean IPC improvement of 1.40%, up to 12.1%.

Figures

Figures reproduced from arXiv: 2505.21669 by the authors.

Figure 2.1
Figure 2.1. Common types of linked data structures. Circles and rectangles [PITH_FULL_IMAGE:figures/full_fig_p019_2_1.png] view at source ↗
Figure 2
Figure 2. a) to track free segments of memory. Self-balancing binary search trees (Fig [PITH_FULL_IMAGE:figures/full_fig_p019_2.png] view at source ↗
Figure 3.1
Figure 3.1. Populated example of the Address and Child Association Tables [PITH_FULL_IMAGE:figures/full_fig_p031_3_1.png] view at source ↗
Figures from the paper (9 more)
Figure 3.2
Figure 3.2. Figure 3.2: The Linkey fetch pipeline. This sits on the critical path and runs in parallel to the core’s L1-D$ access. The full fetch pipeline is displayed in [PITH_FULL_IMAGE:figures/full_fig_p036_3_2.png]
Figure 4.1
Figure 4.1. Figure 4.1: A histogram of a Zipfian distribution with parameter [PITH_FULL_IMAGE:figures/full_fig_p045_4_1.png]
Figure 4.2
Figure 4.2. Figure 4.2: Normalized numbers of load misses with different prefetcher [PITH_FULL_IMAGE:figures/full_fig_p049_4_2.png]
Figure 4.3
Figure 4.3. Figure 4.3: Normalized IPC with different prefetcher configurations. Rows [PITH_FULL_IMAGE:figures/full_fig_p050_4_3.png]
Figure 4.4
Figure 4.4. Figure 4.4: Normalized numbers of load misses when using the [PITH_FULL_IMAGE:figures/full_fig_p051_4_4.png]
Figure 4.5
Figure 4.5. Figure 4.5: Prefetch accuracy of the [PITH_FULL_IMAGE:figures/full_fig_p052_4_5.png]
Figure 4.6
Figure 4.6. Figure 4.6: Prefetch hit counts of the Linkey prefetcher and striding base￾line. Note the use of a log scale on the Y-axis. was small. Overall, we observe a 65.4% improvement in mean prefetch accuracy, from 26.6% to 43.9%. This shows that Linkey can accurately identify and fetch…
Figure 4.7
Figure 4.7. Figure 4.7: Normalized IPC when using the [PITH_FULL_IMAGE:figures/full_fig_p053_4_7.png]
Figure 4.8
Figure 4.8. Figure 4.8: Normalized IPC when using the [PITH_FULL_IMAGE:figures/full_fig_p054_4_8.png]

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Works this paper leans on

15 extracted references · 14 canonical work pages

  1. [1]

    V., and Corasick, M

    [1]Aho, A. V., and Corasick, M. J.Efficient string matching: An aid to biblio- graphic search.Commun. ACM 18, 6 (June 1975), 333–340. [2]Ainsworth, S., and Jones, T. M.Graph Prefetching Using Data Structure Knowledge. InProceedings of the 2016 International Conference on Supercomputing (New York, NY, USA, June 2016), ICS ’16, Association for Computing Mac...

    work page 1975

  2. [12]

    S., Yun, T.-S., Byeon, S., Koo, Y

    [46]Park, M.-J., Cho, H. S., Yun, T.-S., Byeon, S., Koo, Y. J., Yoon, S., Lee, D. U., Choi, S., Park, J., Lee, J., Cho, K., Moon, J., Yoon, B.-K., Park, Y.-J., Oh, S.-m., Lee, C. K., Kim, T.-K., Lee, S.-H., Kim, H.-W., Ju, Y., Lim, S.-K., Baek, S. G., Lee, K. Y., Lee, S. H., We, W. S., Kim, S., Choi, Y., Lee, S.-H., Yang, S. M., Lee, G., Kim, I.-K., Jeon,...

    work page 2022

  3. [14]

    69 [60]Vicarte, J. R. S., Flanders, M., Paccagnella, R., Garrett-Grossman, G., Morrison, A., Fletcher, C. W., and Kohlbrenner, D.Augury: Using Data Memory-Dependent Prefetchers to Leak Data at Rest. In2022 IEEE Sympo- sium on Security and Privacy (SP)(May 2022), pp. 1491–1505. [61]W ang, Z., Burger, D., McKinley, K., Reinhardt, S., and Weems, C. Guided re...

    work page 2022

  4. [126]

    S.Effective jump-pointer prefetching for linked data structures

    [51]Roth, A., and Sohi, G. S.Effective jump-pointer prefetching for linked data structures. InProceedings of the 26th Annual International Symposium on Computer Architecture(USA, May 1999), ISCA ’99, IEEE Computer Society, pp. 111–121. [52]Sankaranarayanan, K., Lin, C.-K., and Chinya, G. N.Helper Without Threads: Customized Prefetching for Delinquent Irre...

    work page 1999

  5. [137]

    [15]Cooksey, R., Jourdan, S., and Grunwald, D.A stateless, content-directed data prefetching mechanism.SIGOPS Oper. Syst. Rev. 36, 5 (Oct. 2002), 279–290. [16]Cooper, B. F., Silberstein, A., Tam, E., Ramakrishnan, R., and Sears, R.Benchmarking cloud serving systems with YCSB. InProceedings of the 1st ACM Symposium on Cloud Computing(New York, NY, USA, Jun...

    work page 2002

  6. [543]

    B., and Kim, H.Spare register aware prefetching for graph algorithms on GPUs

    [32]Lakshminarayana, N. B., and Kim, H.Spare register aware prefetching for graph algorithms on GPUs. In2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)(Feb. 2014), pp. 614–625. [33]Lattner, C.Llvm/llvm-project. LL VM, May

    work page 2014

  7. [1996]

    E., Heirman, W., and Eeckhout, L.Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation

    [8]Carlson, T. E., Heirman, W., and Eeckhout, L.Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. InProceed- ings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis(Seattle Washington, Nov. 2011), ACM, pp. 1–12. 64 [9]Carlson, T. E., Heirman, W., Eyerman, S.,...

    work page 2024

  8. [2000]

    In2011 IEEE 3rd International Conference on Communication Software and Networks(May 2011), pp

    [25]HuiDong, Z., Jing, C., Wei, D., and Yan, H.Performance evaluation of thread prefetching for recursive data structures. In2011 IEEE 3rd International Conference on Communication Software and Networks(May 2011), pp. 610–613. [26]JEDEC. Graphics Double Data Rate (GDDR5X) SGRAM Standard, Mar

    work page 2011

Show all 15 references
  1. [2002]

    Proceedings.(Nov

    (MICRO-35). Proceedings.(Nov. 2002), pp. 62–73. [14]Comer, D.Ubiquitous B-Tree.ACM Computing Surveys 11, 2 (June 1979), 121–

    2002

  2. [2003]

    Proceedings.(June 2003), pp. 388–398. [62]Wenisch, T., Somogyi, S., Hardavellas, N., Kim, J., Ailamaki, A., and F alsafi, B.Temporal streaming of shared memory. In32nd International Sympo- sium on Computer Architecture (ISCA’05)(June 2005), pp. 222–233. [63]Xue, F., Han, C., L...

    2003 arXiv

  3. [2004]

    2004), pp

    CGO 2004.(Mar. 2004), pp. 75–86. [35]Lee, J., Cho, K., Lee, C. K., Lee, Y., Park, J.-H., Oh, S.-H., Ju, Y., Jeong, C., Cho, H. S., Lee, J., Yun, T.-S., Cho, J. H., Oh, S., Moon, J., Park, Y.-J., Choi, H.-S., Kim, I.-K., Yang, S. M., Kim, S.-Y., Jang, J., Kim, J., Lee, S.-H., J...

    2004

  4. [2019]

    In2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)(Sept

    [6]Burcea, I., Soares, L., and Moshovos, A.Pointy: A hybrid pointer prefetcher for managed runtime systems. In2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT)(Sept. 2012), pp. 97–106. [7]Carlisle, M. C.Olden: Parallelizing Programs...

    2012

  5. [2023]

    InPro- ceedings of the 24th Annual International Symposium on Computer Architecture (New York, NY, USA, May 1997), ISCA ’97, Association for Computing Machin- ery, pp

    [27]Joseph, D., and Grunwald, D.Prefetching using Markov predictors. InPro- ceedings of the 24th Annual International Symposium on Computer Architecture (New York, NY, USA, May 1997), ISCA ’97, Association for Computing Machin- ery, pp. 252–263. [28]Kalter, H., Stapper, C., Ba...

    1997

  6. [2024]

    In2010 IEEE 16th International Conference on Parallel and Distributed Systems(Dec

    [37]Liu, G., Huang, Z., Peir, J.-k., and Shi, X.Semantics-Aware, Timely Prefetch- ing of Linked Data Structure. In2010 IEEE 16th International Conference on Parallel and Distributed Systems(Dec. 2010), pp. 213–220. [38]Luk, C.-K., and Mowry, T.Automatic compiler-inserted prefe...

    2010

  7. [2025]

    [43]Mittal, S.A Survey of Recent Prefetching Techniques for Processor Caches.ACM Computing Surveys 49, 2 (June 2017), 1–35

    [42]Meagher, D.Geometric modeling using octree encoding.Computer Graphics and Image Processing 19, 2 (June 1982), 129–147. [43]Mittal, S.A Survey of Recent Prefetching Techniques for Processor Caches.ACM Computing Surveys 49, 2 (June 2017), 1–35. [44]Mori, K., Kosugi, S., Yosh...

    1982

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