Energy-Oriented Computing Architecture Simulator for SNN Training

2); (2) Southern University of Science; 3; 3); (3) Shenzhen Institutes of Advanced Technology; 4); (4) University of Chinese Academy of Sciences); Chinese Academy of Sciences; Fengwei An (2) ((1) Pengcheng Laboratory; Huihui Zhou (1

REVIEW 4 major objections 5 minor 9 references

Energy-Oriented Computing Architecture Simulator for SNN Training

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read EOCAS is an energy-oriented simulator that ranks dataflows and memory hierarchies for SNN training and picks an advanced weight-stationary scheme that cuts convolution energy by 33.8–61.4%.

desk verdict Plausible SNN training energy simulator with real synthesis backing, but headline energy numbers rest on an unvalidated model and an unjustified sparsity assumption. read the letter →

arxiv 2505.24137 v2 pith:PFJHUK7C submitted 2025-05-30 cs.AR

Yunhao Ma (1 , 2) , Wanyi Jia (1 , 3 , 4) , Yanyu Lin (1) , Wenjie Lin (1) , Xueke Zhu (1)

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Huihui Zhou (1 3) Fengwei An (2) ((1) Pengcheng Laboratory (2) Southern University of Science Technology (3) Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences (4) University of Chinese Academy of Sciences)

This is my paper

classification cs.AR

keywords SNNtrainingEnergy-OrientedComputingArchitectureSimulatordataflowoptimizationspikingneuralnetworkhardwareacceleratorenergyefficiencybackpropagationneuromorphic

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that systematic energy evaluation for SNN training is missing, and proposes EOCAS, a simulator that represents the hardware design space and estimates the energy of forward propagation, backward propagation, and weight-gradient convolution for each candidate array shape, memory layout, and dataflow. The central claim is that EOCAS can identify the optimal architecture, and that the architecture it picks — a 16x16 array running an 'advanced weight-stationary' (advanced WS) dataflow — uses 33.8% to 61.4% less energy than conventional dataflows for the evaluated layer. The paper also claims that a Verilog implementation of this design, synthesized on TSMC 28nm at 500 MHz, consumes 0.452 W and outperforms several state-of-the-art DNN and SNN accelerators in energy efficiency and memory usage. A sympathetic reader would care because energy-efficient SNN training hardware is the missing piece for neuromorphic systems to move beyond inference.

What carries the argument

The load-bearing object is the energy model built from reuse factors and unit energies for each variable at each storage level (Table I, II), together with the nested-loop representation of dataflow and the cost equations (16)–(22) that convert operand counts into energy. The advanced WS dataflow is the proposed mechanism: it decomposes input feature maps across output and input channels for fine-grained parallelism, partially loads weights for tiled reuse, and accumulates partial sums over the full output spatial grid. This dataflow carries the argument because it is what EOCAS ranks above conventional schemes, and it is what the hardware implementation instantiates.

What would settle it

Take the post-synthesis power report of the implemented design during a full training run and measure the power of the soma and grad units separately; if their combined energy is a substantial fraction of the 0.452 W total or differs across dataflows, the simulator's ranking of architectures would need revisiting.

Watch

Extended reading notes

Core claim

EOCAS treats the SNN training task as three convolutions — spike convolution in forward propagation, potential-gradient convolution in backpropagation, and weight-gradient convolution — and evaluates each under configurable array geometries (e.g. 2x128, 4x64, 8x32, 16x16) and dataflows (WS1, WS2, OS, RS, advanced WS). Its energy model sums compute energy and memory-access energy using reuse factors and per-access unit energies, and it ignores element-wise soma and grad operations as computationally negligible and dataflow-independent. The simulator selects 16x16 as the optimal array and advanced WS as the optimal dataflow, reporting 758.616 μJ total energy for the evaluated layer, with reductions of 33.8% (vs WS1), 55.8% (vs WS2), and 61.3–61.4% (vs OS and RS). The paper then builds the full FWD/BWD hardware at RTL, synthesizes it with Synopsys Design Compiler on TSMC 28nm under typical parameters, and reports 0.452 W total power, 2.76x higher energy efficiency than TrueNorth, 49.25% lower memory usage than SATA, and roughly one-tenth the energy of a Transformer training accelerator.

Load-bearing premise

The energy ranking assumes that the soma unit, the grad unit, and element-wise operations consume so little energy, and vary so little with dataflow, that optimizing only the convolution array and memory hierarchy finds the true energy-optimal architecture.

Editorial extensions

If this is right

For any deep SNN training workload, EOCAS can be re-run with the workload's layer shapes and sparsity to produce an architecture/dataflow recommendation; the paper demonstrates this for a representative CIFAR-100 layer.
The advanced WS dataflow yields the lowest energy among the five evaluated dataflows for the 16x16 array, with savings of 33.8–61.4% total energy in the simulated convolution.
The RTL implementation at 500 MHz on TSMC 28nm realizes the simulated optimum, with 0.452 W power and post-synthesis energy estimates that beat the compared inference-only and training accelerators on energy efficiency and memory.
Because soma and grad operations are treated as dataflow-independent, the optimization can focus on the convolution array and memory hierarchy without per-dataflow re-evaluation of those units.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

One could test the weak assumption directly by instrumenting the post-synthesis netlist for soma/grad power; if their share of total training energy is non-negligible, EOCAS's ranking might change.
The same reuse-factor energy accounting could be applied to inference, since inference is just the FP path; advanced WS might also improve inference-only SNN accelerators.
EOCAS's design-space representation could be extended to other neuron models and surrogate-gradient functions by replacing the operation counts and unit energies, giving a general energy simulator for neuromorphic training.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: this is a real attempt at filling a gap, not a throwaway. The paper adapts Timeloop/ZigZag-style design-space energy simulation to SNN training with spike sparsity, adds an advanced weight-stationary dataflow, and backs it with a synthesized 28nm Verilog implementation. That combination is genuinely new for the neuromorphic training subfield; SATA and H2Learn are training accelerators but not design-space simulators, and the paper's implementation goes beyond them. Credit where due. The soft spots are real and load-bearing. First, the paper claims "no systematic energy evaluation methods exist" while citing SATA and H2Learn, both of which include energy evaluation. That overstatement needs fixing but is not fatal. Second, Section III-C's energy model is not fully specified: the per-SRAM energy constants, unit operation energies, and sparsity values are not reported, and the equations are garbled in the extracted text; no code or data are provided. More importantly, the simulator is never validated against the synthesized hardware's PrimeTime power breakdown; the only external anchor is the total 0.452W post-synthesis power. Third, and this is the main problem: Sections II and III-D explicitly declare soma, grad, and element-wise operations negligible. At high spike sparsity, which is the whole point of using SNNs, convolution energy scales down with Spar_l but soma/grad energy does not; the "several orders of magnitude" gap can collapse. Even if the omitted energy is constant across dataflows, the absolute 758.616 uJ and the 33.8-61.4% reductions in Table IV change when a constant is added, and the SOTA comparisons are computed from the same partial model. The stress-test note lands. The reader's conclusion is fair: reject in current form, low confidence because a complete PDF might fix equation display, but the lack of validation would remain. That said, the paper deserves referee time. The topic is underserved, the framing is coherent, and the implementation is concrete. A serious referee could push for the missing constants, a validation section against the synthesized netlist, inclusion of soma/grad in the model, and fairer comparisons that separate training from inference. I'd accept it for peer review with the expectation of heavy revision. I wouldn't cite it yet, but it is worth a reading-group discussion on simulator methodology.

Referee Report

4 major / 5 minor

Summary. The paper proposes EOCAS, an energy-oriented architecture simulator for spiking neural network (SNN) training, intended to select the most energy-efficient compute array configuration, dataflow, and memory hierarchy. The simulator models convolution energy from Mux/Add/Mul operations plus memory read/write energy, using per-layer spike sparsity to reduce operation counts. The authors apply EOCAS to a CIFAR-100-style layer, claim that a 16x16 array and an 'advanced WS' dataflow are optimal, and report a total energy of 758.616 μJ, which they say is 33.8–61.4% lower than alternative dataflows. They also implement the selected architecture in Verilog, synthesize it with Synopsys Design Compiler on a TSMC-28nm library, report 0.452 W post-synthesis power, and compare the design against several prior SNN/DNN accelerators.

Significance. If the energy model were complete, validated, and reproducible, EOCAS could be a useful contribution to the under-served area of SNN training accelerator design, where most prior work focuses on inference. The authors are to be credited for building a full hardware implementation, reporting post-synthesis power, and attempting a systematic design-space exploration. However, the central quantitative claims—the energy-optimality of advanced WS and the 33.8–61.4% energy reductions—rest on a simulator whose energy model omits non-negligible components, whose energy constants are not reported, and whose predictions are never validated against measured hardware. As written, the evidence for the main claims is endogenous to the simulator itself.

major comments (4)

[Sections II and III-D; Eqs. (15)–(22); Table IV] The energy model excludes soma and grad unit energy. Section II states that element-wise operations are "several orders of magnitude less computational than the spike convolution operation, which can be ignored," and Section III-D asserts that dataflow variations have limited impact on soma/grad operations. Yet Section III-D lists per-soma cost as 3 comparators, 3 multiplexers, 1 adder, and 1 multiplier, and per-grad cost as 2 multipliers, 2 adders, and 2 multiplexers. These costs are independent of spike sparsity, while convolution operation counts in Eqs. (4)–(5) scale with Spar_l. At realistic sparsity (e.g., Spar_l = 0.1) and for layers with small input channel counts (e.g., C_in = 3), the ratio of convolution operations to soma operations is on the order of C_in x K^2 x Spar_l, which is not "several orders of magnitude"; the omitted soma/grad energy can therefore be comparable to the included convolution energy, so the overall energy values in Table IV and the claimed energy reductions are unsupported.
[Section III-C; Eqs. (20)–(22); Tables I–III] The energy constants and reuse factors needed to evaluate the model are not reported. Eq. (20) references e0…e6, Eq. (21) references e0…e12, and Eq. (22) references e0…e18, but no numeric values, technology assumptions, or extraction procedure are given for these coefficients, nor for the unit operation energies o0, o1, o2 used in Eqs. (17)–(19). Table I is said to define reuse factors but its contents are not visible; Tables II and III have identical captions and do not provide the required constants. Without these inputs, the 758.616 μJ figure and all comparative energy numbers cannot be reproduced or audited.
[Section IV; Tables IV–VII] EOCAS is never validated against measured hardware. The introduction cites LLMCompass as having a 10.9% error rate relative to real hardware, but no analogous error analysis is presented for EOCAS. The only hardware data point is the post-synthesis power of 0.452 W, which is not compared with the simulator's energy prediction for the same workload. Since the simulator selects the dataflow and array configuration and the same simulator produces the energy numbers used to declare advanced WS superior, the main evidence for the central claim is circular. The paper needs an external check, for example comparing EOCAS's predicted energy with post-synthesis or post-layout power/energy measurements (or with published measurements for a comparable accelerator) on the same CNN/SNN workload.
[Section II; Eqs. (4) and (5) and Eq. (12)] There is an inconsistency in the sparsity treatment of Mux versus Add operations. Eq. (4) for the Mux operand count lacks the Spar_l factor that appears in Eq. (5) for the Add operand count, even though Section III-A states that when the Mux output is 0 the accumulation is skipped, implying that Mux operations should also be gated by sparsity. If this is intentional, the formula needs justification; if it is a typo, the formulas must be corrected before the energy model can be evaluated. In addition, Eq. (12) contains an unexplained "+1" term that should be clarified.

minor comments (5)

[Section I] The abstract and introduction claim that "no systematic energy evaluation methods exist for SNN training tasks," which is contradicted by the paper's own citation of SATA [15] and H2Learn [10], both of which address SNN training energy evaluation; the claim should be softened to "few" or "no open-source simulator with these features."
[Equations (1)–(12); throughout] The mathematical notation is heavily garbled, with placeholder symbols such as "??", "∇??", and "????????" appearing in place of defined variables. This makes it difficult to verify the derivation of the operation-count formulas and should be corrected with consistently defined notation.
[Section IV.A; Fig. 6] The description of "advanced WS" is too informal to be reproducible. A formal loop nest or mapping specification, as is standard for dataflow papers (e.g., in Timeloop/ZigZag), is needed to distinguish the proposed dataflow from the two conventional WS variants and from OS and RS.
[Section IV.B; Table VII] The claim that the proposed design achieves 2.76x higher energy efficiency than TrueNorth is not supported with a derivation or a clear definition of the energy-efficiency metric used; the comparison should state both the workload and the efficiency measure explicitly.
[Section IV.A; Fig. 5 and Table III] Figure 5 is described as showing "different energy intervals with different schemes," but the x-axis and y-axis quantities are not defined, and the relationship between these schemes and the 16x16 array choice is not explained. Table III appears to be mislabeled; its caption is identical to Table II and its contents are not described in the text.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: EOCAS's dataflow ranking is a computed simulation result, and the hardware claims have independent grounding from post-synthesis power and published SOTA comparisons.

full rationale

EOCAS is a design-space exploration tool: it takes SNN models, a memory pool, and a general accelerator template as inputs, computes convolution and memory energy from Eqs. (15)-(22), and selects the lowest-energy dataflow and array configuration. The claim that advanced WS achieves 758.616 uJ and beats WS1, WS2, OS, and RS is a simulation output, not a fitted parameter renamed as a prediction; the ranking follows from the stated energy equations and the dataflow reuse factors. The subsequent 28nm synthesis reports an independent post-synthesis power of 0.452 W, and the SOTA comparisons use published numbers for TrueNorth, SATA, and the transformer accelerator, so the central hardware claims do not reduce to the simulator's own outputs. The paper's decision to ignore soma, grad, and element-wise unit energy (Sec. II, III-D) is an explicit assumption that could undercut the numerical energy totals, but it is a correctness/completeness risk rather than a circular reduction: Eq. (15) does not define 'optimal' in terms of the result, and no load-bearing self-citation or uniqueness argument appears in the derivation chain.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claim rests on assumed unit energies, reuse factors, sparsity values, and modeling choices that are not reported or independently validated. The paper contributes the simulator framework and the advanced WS dataflow, but all energy advantages are computed by that same framework, so the ledger of unverified inputs is large.

free parameters (4)

Unit operation energies o0, o1, o2 for Mux, Add, Mul = not reported
Equations (17)-(19) use o0, o1, o2 to convert operation counts into compute energy. Their values are never given, and all totals scale linearly with them.
Per-SRAM read/write energy coefficients (referenced as e0..e18 in Eqs. 20-22) = not reported
Memory energy equations multiply operation counts by these per-access energies. They are not listed in the visible text and directly determine which dataflow ranks best.
Per-layer spike sparsity Spar_l = not reported
Operation-count formulas (4)-(5) and (11)-(12) depend on Spar_l to skip spike multiplexing and addition. How Spar_l is obtained (measured or assumed) is not stated.
Data reuse factors for each variable and memory level = not reported
Table I defines reuse factors 'inspired by [9]' that scale memory access counts. These factors heavily influence the comparison between WS, OS, RS, and advanced WS.

assumptions (4)

domain assumption SNN training energy is a linear sum of compute energy and memory-access energy with fixed per-operation and per-access constants.
Section III-C builds the total energy from Eq. (15) through (22) with constants o0-o2 and memory unit energies. This additive model is assumed accurate for the 28nm library and the target arrays.
domain assumption Element-wise operations, soma-unit energy, and grad-unit energy are negligible or dataflow-independent and can be excluded from the optimization.
Section II states element-wise ops 'can be ignored'; Section III-D treats soma/grad as static. If their energy is significant, the selected dataflow may not minimize true training energy.
domain assumption The operation-count formulas (4), (5), (9), (11), (12) correctly count Mux, Add, and Mul operations, including sparsity effects.
All energy totals derive from these counts, but the printed equations use undefined symbols and the sparsity term is not visible, so the counts cannot be independently verified.
domain assumption Published accelerator numbers from other papers are accurate and directly comparable across process nodes, precisions, and workloads.
Section IV.B compares FPGA resources and ASIC power/energy with TrueNorth, SATA, a Transformer accelerator, and inference chips without normalization; unfair comparisons would invalidate the 'outstands others' claim.

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Cite this review

Pith. "Pith review of Energy-Oriented Computing Architecture Simulator for SNN Training." pith.science (2026). https://pith.science/paper/PFJHUK7C

@misc{pith2026250524137,
  author       = {Pith},
  title        = {Pith review of: Energy-Oriented Computing Architecture Simulator for SNN Training},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PFJHUK7C}},
  note         = {Machine review of arXiv:2505.24137}
}

read the original abstract

With the growing demand for intelligent computing, neuromorphic computing, a paradigm that mimics the structure and functionality of the human brain, offers a promising approach to developing new high-efficiency intelligent computing systems. Spiking Neural Networks (SNNs), the foundation of neuromorphic computing, have garnered significant attention due to their unique potential in energy efficiency and biomimetic neural processing. However, current hardware development for efficient SNN training lags significantly. No systematic energy evaluation methods exist for SNN training tasks. Therefore, this paper proposes an Energy-Oriented Computing Architecture Simulator (EOCAS) for SNN training to identify the optimal architecture. EOCAS investigates the high sparsity of spike signals, unique hardware design representations, energy assessment, and computation patterns to support energy optimization in various architectures. Under the guidance of EOCAS, we implement the power-aimed optimal hardware architecture through Verilog HDL and achieve low energy consumption using Synopsys Design Compiler with TSMC-28nm technology library under typical parameters. Compared with several State-Of-The-Art (SOTA) DNN and SNN works, our hardware architecture outstands others in various criteria.

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Reference graph

Works this paper leans on

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

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