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REVIEW 2 major objections 5 minor 14 references

A 40.68-MHz, 200-ns-Settling Active Rectifier and TX-Side Load Monitoring for Minimizing Radiated Power in Biomedical Implants

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A 40.68-MHz active rectifier with sample-and-accumulate delay compensation settles in under 200 ns, while a transmitter-side phase-only monitor reduces radiated power by about 10 percent in measurement.

desk verdict The rectifier delay-compensation work is genuinely new and measured; the TX-side PRE load sensing is an interesting idea that is validated at a single link condition, and the abstract oversells simulated results as measured. read the letter →

arxiv 2506.07710 v1 pith:NIJGN5AW submitted 2025-06-09 eess.SY cs.SY

Ronald Wijermars , Yi-Han Ou-Yang , Sijun Du , Dante Gabriel Muratore This is my paper
classification eess.SYcs.SY
keywords activerectifierdelaycompensationwirelesspowertransferbiomedicalimplantsradiatedefficiencysample-and-accumulatetransmitter-sideloadmonitoring40.68MHz
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a wireless-power receiver for implants can settle fast and stay safe at the same time. Its active rectifier replaces the slow feedback amplifier used in prior delay compensation with a direct sample-and-accumulate voltage correction, reaching a worst-case settling of about 200 ns and then correcting within a single 25-ns cycle during load or input steps. On the same 40-nm CMOS chip it reports a measured voltage conversion ratio of 93.9% and a post-layout simulated power conversion efficiency of 90.1%, with the resonance and filter capacitors integrated on chip. The paper further claims that optimizing the link for power radiated efficiency instead of power transfer efficiency reduces radiated power by about 10% in measurement, using only a transmitter-side phase measurement to regulate the link. A sympathetic reader would care because lower radiated power means less tissue heating in implants, and the fast settling keeps efficiency up during ASK downlink communication.

What carries the argument

The load-bearing circuit is the sample-and-accumulate voltage-domain delay compensation: a sampling capacitor captures the error voltage $\Delta V_S$ at the switching instant, identical current sources plus a zero-crossing detector transfer that charge onto a compensation capacitor $C_C$, and the accumulated voltage $V_C = \sum V_S$ directly offsets the comparator, eliminating the intentionally slow feedback loop. A delay line shifts the OFF-trigger point away from the AC-input trough where the derivative of the input voltage is near zero. The link-level mechanism is the power-radiated-efficiency (PRE) optimization rule: during startup the implant draws constant power, the transmitter sweeps $V_{\mathrm{TRANS}}$, the minimum received amplitude marks peak PRE, and the corresponding phase $\Delta\Phi_{\mathrm{OPT}}$ between $V_{\mathrm{TX}}$ and $I_{\mathrm{TX}}$ becomes the setpoint that the transmitter power amplifier regulates against during normal operation.

What would settle it

Hold the receiver tank load fixed and sweep the coil separation or lateral misalignment while recording the transmitter-side phase difference; if the phase changes by more than a few degrees at the same load, the single-startup-calibration assumption fails and the TX-side monitor would require recalibration or the PRE optimum would drift.

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Extended reading notes

Core claim

The paper's central claim is that the two main obstacles to practical 40.68-MHz implant power delivery, slow adaptive delay compensation and receiver-side power optimization, can be removed with one rectifier design and one link-control rule. In the rectifier, the on/off comparator delay is compensated by sampling the error voltage at each switching instant and accumulating it directly onto a compensation capacitor, so the compensation voltage is added in series to the comparator input as the new offset. Because no low-bandwidth feedback loop is needed, the compensation settles in a worst case of about 200 ns and continuously re-corrects within a single 25-ns cycle over load or input variations, leaving a residual delay below 200 ps. At the link level, the paper claims that holding the transmitter-side phase angle between $V_{\mathrm{TX}}$ and $I_{\mathrm{TX}}$ at a value recorded during a one-time startup calibration maintains the receiver tank load at the power-radiated-efficiency optimum, and that this reduces radiated power by about 10% in measurement compared with optimizing for power transfer efficiency.

Load-bearing premise

The load-bearing assumption is that the transmitter-side phase setpoint recorded once at startup remains the correct operating point as the coil link changes, since the phase-to-receiver-load mapping is treated as independent of coupling strength and detuning; Fig. 7(e) shows only one measured link condition.

Editorial extensions

If this is right

  • Implant rectifiers can track fast load steps and ASK downlink data without the microsecond-scale settling reported for earlier adaptive delay-compensated designs, so efficiency stays high during communication.
  • With the switched-capacitor power converter in the architecture, any output load can be transformed to the PRE-optimal receiver tank load, extending the efficiency optimum across the whole load range.
  • The transmitter-side phase measurement closes the control loop without implant-to-transmitter back-telemetry, simplifying the implanted electronics and data link.
  • Integrating the resonance and filter capacitors on chip at 40.68 MHz reduces the implant to a coil plus the chip, a path to smaller implants at a power density of 118 mW/mm².
  • Radiated power, the quantity that sets tissue-heating limits, is lower under PRE optimization than under PTE optimization; the paper measures about 10% improvement including real link losses.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper, the one-time startup calibration could be re-run periodically without hardware changes, turning the single setpoint into a slow background monitor that would absorb coil movement or detuning; the paper does not test this re-calibration scenario.
  • Beyond the paper, because the compensation relies on matched sampling and compensation capacitors, capacitor mismatch likely sets a floor on residual switching delay; measuring settling across process corners would reveal whether the 200-ns worst case is set by matching or by the charge-transfer logic.
  • Beyond the paper, the measured 10% PRE benefit is link-loss dependent, so an extension would sweep coil separation or misalignment and record how the PRE-versus-PTE gap changes to map where the single-calibration assumption starts to fail.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The letter presents a 40.68 MHz wireless power transfer receiver for biomedical implants, with two main contributions. First, it describes a 40 nm CMOS active rectifier using a sample-and-accumulate voltage-domain ON/OFF delay compensation that is claimed to settle in a worst case of 200 ns, achieving a measured VCR of 93.9% and a post-layout simulated PCE of 90.1% in a 0.19 mm^2 area with on-chip resonant and filter capacitors. Second, it proposes a power radiated efficiency (PRE) optimization scheme in which a single startup calibration of the TX-side phase difference ΔΦ is used for TX-side load monitoring and closed-loop power regulation, with a measured ~10% radiated-power improvement compared with PTE optimization. The measured results include steady-state transients, a load-step response, VCR versus load, PRE/PTE versus load, and phase versus load, while the 200 ns settling and the 90.1% PCE are identified in the body as simulated.

Significance. If the claims are confirmed, the fast-settling delay-compensation technique would be a useful step forward for active rectifiers in implantable WPT, since it avoids a slow feedback loop and is compatible with on-chip integration of the resonant and filter capacitors. The PRE concept has genuine safety relevance because it targets radiated power into tissue rather than conventional PTE. The authors deserve credit for reporting measured VCR and load-step behavior, for disclosing that PCE could not be measured, and for providing a comparison table with state-of-the-art designs. The significance is tempered by two gaps: the headline 200 ns settling time is only simulated, and the closed-loop PRE regulator relies on an unvalidated assumption that a single startup phase calibration remains optimal as the link changes. The measured 10% PRE improvement is encouraging, but it is reported for only one link condition.

major comments (2)
  1. [Section II and Fig. 7(e)] The closed-loop PRE regulator is built on the premise that the TX-side phase difference ΔΦ is proportional to R_RX and that a single startup calibration value ΔΦ_OPT remains optimal during operation. The paper provides no derivation of this mapping and shows only one measured link condition (12 mm separation, nominal tuning) in Fig. 7(e). In the coupled-resonator model the TX-side phase depends on the reflected impedance, which is a function of both the RX load and the mutual inductance, and it also shifts with tank detuning. Therefore a fixed ΔΦ_OPT may not correspond to the PRE optimum when the link changes, and the regulator could hold a non-optimal R_RX, causing the claimed radiated-power benefit to shrink or reverse. This is a load-bearing issue for the TX-side load-monitoring contribution. Please provide either an analytical derivation of the phase-load relationship including coupling and detuning dependence, or measurements at multiple separations and detuning conditions, or a calibration/update procedure that maintains validity; and report the PRE improvement across a range of link conditions.
  2. [Section III, Section IV, Fig. 7(b)] The abstract and Table I present '200 ns' and 'fastest reported' settling as a headline result, but in Section III the value is explicitly described as 'simulated worst-case settling <200 ns.' The load-step measurement in Fig. 7(b) is limited by the output pole formed by the on-chip filter capacitor and the load (RC = 150 ns), so it cannot directly confirm the compensation-loop settling time. Please label the 200 ns value as simulated in the abstract and Table I, and provide either a direct measurement that isolates the compensation loop from the output filter or a simulation setup that explicitly separates the two, so that the reader can assess the claimed settling advantage.
minor comments (5)
  1. [Abstract, Table I, Fig. 7(c)] The VCR values are inconsistent: the abstract states a measured VCR of 93.9%, Fig. 7(c) shows a peak of about 93.9% at a 700 Ω load, while Table I lists a peak VCR of 93.8% and a VCR of 92.0% at RL = 500 Ω. Please reconcile these numbers and specify the operating point used for the abstract claim.
  2. [Conclusion and Table I] The conclusion states that VCR and PCE are comparable to the state of the art, but the 90.1% PCE is a post-layout simulated result and the text states that PCE could not be measured. Please qualify the PCE comparison explicitly as simulated in both the conclusion and the table.
  3. [Fig. 1(b) and Section IV] The analytical 30% improvement in Fig. 1(b) differs from the measured ~10% improvement in Fig. 7(d); the text explains that additional link losses shift the curves, but it would be clearer to state the loss assumptions in the analytical model and the exact conditions of the measurement.
  4. [Fig. 3] The caption of Fig. 3(b) appears to label the sampling and compensation capacitors in reverse relative to the text: the text says C_S samples the error voltage and C_C stores compensation, while the caption reads 'Sampling capacitor CC Compensation capacitor CS.' Please correct the labeling or clarify the notation.
  5. [References] Reference [12] lists IEEE J. Solid-State Circuits volume 68 for a 1990 publication; the JSSC volume number appears to be incorrect. Please verify the citation details.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the rectifier settling and PRE claims rest on measurements or external benchmarks, not on self-referential fitting.

full rationale

The paper's derivation chain is self-contained. The active-rectifier settling claim is supported by a measured load-step transient whose 150 ns output pole is consistent with the observed settling, plus a simulated sub-200 ns delay-compensation settling; the comparison to prior work uses external published benchmarks, not self-citations. The PRE concept is introduced by definition (POUT/PRAD versus POUT/PIN), and the quoted 30% analytical improvement is a model calculation while the 10% measured improvement is a direct comparison of measured PRE and PTE curves, not an output of fitted parameters. The TX-side load-sensing scheme does use an empirical startup calibration of ΔΦOPT, but that calibration is performed against a directly observed proxy for peak PRE (minimal VTRANS amplitude) and is then tracked in regulation; it is not used to predict the measured radiated-power improvement, which is reported as a measurement. The paper invokes no uniqueness theorem and no load-bearing self-citation: reference [7], cited for the phase-measurement concept, is an external prior work by different authors. The main weakness, that the phase-to-RRX mapping is only demonstrated at one link condition, is an unvalidated assumption about robustness rather than a circular reduction of the claims to their inputs.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

No free parameters are fitted to data; the PRE optimization is a definition, and the phase calibration is an empirical setpoint rather than a fitted parameter. No new physical entities are introduced. The axioms listed are the modeling assumptions behind the PRE proxy and the delay-loss estimates.

assumptions (3)
  • domain assumption VTRANS amplitude is approximately proportional to the radiated power from the TX antenna.
    Stated in Section II ('since VTRANS is approximately proportional to the radiated power') and used to justify finding the PRE optimum by minimizing VTRANS during startup calibration. No derivation or tissue model is provided.
  • domain assumption The phase difference between VTX and ITX is proportional to the RX tank load RRX and can be used to track PRE.
    Used in Section II for TX-side load sensing. Fig. 7(e) shows a measured relationship for one link configuration, but 'proportional' and invariance across coupling/detuning are not established.
  • domain assumption The rectifier and link can be modeled with a sinusoidal AC source and a resistive load RRX such that comparator delay losses follow the energy-fraction curve in Fig. 5.
    The 200 ps residual delay claim and the <1% energy loss estimate rely on the idealized sinusoidal model in Fig. 5 with VCR=0.95; real waveforms with harmonics and parasitic coupling may differ.

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Cite this review

Pith. "Pith review of A 40.68-MHz, 200-ns-Settling Active Rectifier and TX-Side Load Monitoring for Minimizing Radiated Power in Biomedical Implants." pith.science (2026). https://pith.science/paper/NIJGN5AW

@misc{pith2026250607710,
  author       = {Pith},
  title        = {Pith review of: A 40.68-MHz, 200-ns-Settling Active Rectifier and TX-Side Load Monitoring for Minimizing Radiated Power in Biomedical Implants},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NIJGN5AW}},
  note         = {Machine review of arXiv:2506.07710}
}
abstract

This letter describes a 40.68 MHz wireless power transfer receiver for implantable applications focused on minimizing tissue heating. The system features a novel power radiated efficiency optimization strategy and a fast-settling active rectifier that maintains high efficiency during load and link variations required for downlink communication. The power radiated efficiency optimization explicitly reduces tissue heating while enabling transmitter-side load monitoring for closed-loop control. The active rectifier was fabricated in 40nm CMOS and achieves a voltage conversion ratio of 93.9% and a simulated power conversion efficiency of 90.1% in a 0.19 $mm^2$ area, resulting in a 118 mW/$mm^2$ power density while integrating the resonance and filter capacitors. The worst-case settling of the on- and off-delay compensation in the active rectifier is 200 ns, which is the fastest reported to date.

Figures

Figures reproduced from arXiv: 2506.07710 by the authors.

Figure 1
Figure 1. (a) System architecture of WPT-link and PMU, (b) [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Illustration of the load sensing concept enabled by the [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. (a) The proposed delay compensation, (b) simplified operation of the sample-and-accumalate and (c) transient waveform [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: (a) Schematic of the delay compensation loops, (b) [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 5
Figure 5. Figure 5: Impact of comparator delay on rectifier efficiency [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 7
Figure 7. Figure 7: Measurement results for, (a) steady state transient, (b) [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

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Reference graph

Works this paper leans on

14 extracted references · 14 canonical work pages

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