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REVIEW 4 major objections 5 minor 1 cited by

Leveraging Photonic Interconnects for Scalable and Efficient Fully Homomorphic Encryption

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A photonic interconnect design called OptoLink is claimed to feed fully homomorphic encryption accelerators at 1.6 TB/s, 300 times the bitrate of an electrical link, with 10 ps latency.

desk verdict Plausible idea and a small real simulation, but the 1.6 TB/s headline is an unjustified 10x extrapolation from a 10 Gb/s demo; not ready for serious peer review. read the letter →

arxiv 2506.12962 v1 pith:ZK5AUDGZ submitted 2025-06-15 cs.ET

Dewan Saiham , Di Wu , Sazadur Rahman This is my paper
classification cs.ET
keywords fullyhomomorphicencryptionphotonicinterconnectwavelengthdivisionmultiplexingnumbertheoretictransformmemorybandwidthmicro-ringresonatorFHEacceleratorspace
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper is trying to establish that memory bandwidth, not arithmetic throughput, is the limiting resource in fully homomorphic encryption (FHE) accelerators, and that a photonic interconnect can remove that limit. It introduces OptoLink, an optical link that uses wavelength-division multiplexing to move data between memory and number-theoretic-transform (NTT) engines. According to the paper's simulations, 128 optical channels deliver 1.6 TB/s, about 300 times the bitrate of a 128-channel electrical interconnect, with a link latency of 10 ps. If correct, this makes terabyte-scale data movement feasible for FHE workloads such as key switching and polynomial multiplication, which currently stall on memory access.

What carries the argument

The load-bearing mechanism is a wavelength-division-multiplexed photonic link built from micro-ring resonators (MRRs), the ring-shaped optical filters that modulate and filter light at specific wavelengths. A shared laser feeds a waveguide; transmitter MRRs imprint electrical data onto distinct wavelength channels, filter MRRs at the receiver pick out those wavelengths, and photodetectors convert the light back to electrical signals, with multiple parallel waveguides (space-division multiplexing) adding another axis of parallelism. Each wavelength carries one bit per channel, and the paper cites a prior result of up to 64 wavelengths per waveguide as the basis for scaling. This optical datapath is what converts a hard electrical bandwidth ceiling into a scalable optical one, and it is also where the paper's extrapolation from a demonstrated 10 Gb/s link to 100 Gb/s per channel lives.

What would settle it

Run the same single-channel simulation at 100 Gb/s instead of 10 Gb/s, or fabricate a 128-channel photonic link and measure bit error rate and per-channel insertion loss at full aggregate bandwidth; if error-free 100 Gb/s per channel is not achieved, or if loss and crosstalk at 128 channels force a lower bitrate or higher laser power, the 1.6 TB/s claim collapses.

Watch

Extended reading notes

Core claim

The paper's central claim is that replacing electrical wires with a photonic network based on wavelength-division and space-division multiplexing lets an FHE accelerator move ciphertexts, twiddle factors, and intermediate results at terabyte-scale bandwidth with picosecond latency. In the paper's account, a single OptoLink channel runs at 100 Gb/s (12.5 GB/s), and 128 channels give 1.6 TB/s, compared with 5.26 GB/s at 3.04 ns for an equivalent electrical network at 128-bit width; scaling to 192 and 1024 channels yields 2.4 TB/s and 12.8 TB/s. The paper argues that compute acceleration alone cannot make FHE practical because data transportation dominates execution time in large-parameter settings, and photonic interconnects close that gap.

Load-bearing premise

The whole throughput claim rests on the assumption that the demonstrated 10 Gb/s per-wavelength optical link can be scaled tenfold to 100 Gb/s per channel and replicated across 128 channels without extra optical loss, crosstalk, thermal drift, or packaging penalties.

Editorial extensions

If this is right

  • An FHE accelerator using OptoLink could move NTT inputs, twiddle factors, and outputs at 1.6 TB/s, removing the memory-transfer stall the paper identifies as the dominant cost in large-parameter FHE.
  • Adding channels scales the link: 192 channels reach 2.4 TB/s and 1024 channels reach 12.8 TB/s without widening the electrical datapath.
  • With 10 ps link latency, read-after-write conflicts and pipeline stalls in NTT dataflow become far less expensive, simplifying memory scheduling.
  • The same photonic datapath can carry key-switching and basis-conversion traffic, since it transports raw data rather than NTT-specific logic.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's power numbers show OptoLink drawing roughly three to four orders of magnitude more power than the electrical links it replaces; a fair system comparison would need to credit the power saved by shorter execution time, which the paper does not quantify.
  • Because the only shown waveform is a 10 Gb/s PRBS, the 100 Gb/s per-channel figure is an extrapolation; a direct multi-wavelength prototype at 100 Gb/s would be the natural next test.
  • If terabyte-scale interconnect bandwidth becomes real, the FHE bottleneck may shift back to the NTT compute units, making on-chip arithmetic rather than data movement the next design target.
  • The same WDM/SDM approach could serve other memory-bound lattice-cryptography workloads, such as zero-knowledge proofs or post-quantum signatures, which share the same polynomial-multiplication data movement pattern.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This manuscript proposes OptoLink, a silicon-photonic WDM/SDM interconnect intended to connect NTT modules and memory in FHE accelerators. The authors describe an architecture using microring modulators and filters, waveguides, photodetectors, and TIAs, and they report a Synopsys OptoCompiler simulation of two optical channels carrying a 64-bit PRBS at 10 Gb/s over a 1 mm waveguide with 10 ps latency. They then compare timing, power, and area against an electrical network synthesized with a 32 nm library. The headline claims are 1.6 TB/s aggregate throughput over 128 channels, 2.4 TB/s for 192 channels, and "300 times" the bandwidth of electrical interconnects.

Significance. The motivation is real and well documented: FHE/NTT workloads are memory-bandwidth-limited, and existing accelerators need multi-TB/s interconnect bandwidth. A photonic interconnect with validated per-channel data rates and physically grounded scaling rules would be a useful contribution to the FHE accelerator literature. The paper also gives a clear high-level architecture and uses commercial EDA tools for the optical link, which is a strength in principle. However, the central quantitative claims are not established by the reported experiments: the only optical simulation runs at 10 Gb/s per channel, and the 1.6 TB/s figure is an arithmetic product of an assumed 100 Gb/s per channel and an assumed 128 channels. As a result, the paper's main finding rests on an unverified extrapolation rather than on measurement or simulation.

major comments (4)
  1. [Sec. IV-A] The sentences "Data was sent at 10Gb/s" and "Each OptoLink channel achieved a data rate of 100Gb/s" are in direct contradiction. The PRBS simulation produces 64 bits in 6.4 ns, i.e., 10 Gb/s per channel, and no simulation, measurement, or derivation at 100 Gb/s is presented. Since the aggregate throughput of 1.6 TB/s = 128 × 12.5 GB/s is built entirely from the 100 Gb/s assumption, the headline result is circular with respect to the input assumptions and cannot be claimed as a demonstrated outcome. At 100 Gb/s OOK the unit interval is 10 ps, equal to the reported waveguide latency, so the 10 Gb/s simulation does not exercise modulator, photodetector, TIA, dispersion, or crosstalk behavior at the claimed rate.
  2. [Sec. IV-A and Table III] The electrical baseline is not specified. The table reports 5.26 GB/s at 3.04 ns latency for a 128-bit bus, but no clock frequency, signaling standard, wire model, or link-level simulation is given. If 5.26 GB/s is obtained as 128 bits divided by 3.04 ns, that conflation of latency with bit period yields a 42 Gb/s bus, which is not representative of any conventional electrical interconnect. The 300x speedup claim requires a documented electrical baseline, such as a specific SerDes or parallel bus with a stated clock rate and signaling scheme.
  3. [Sec. III-A, Sec. III-C, and Fig. 4] The 128-channel implementation is not described. The text cites a 64-wavelength WDM limit from [27], while Fig. 4 instantiates 24 wavelengths across five waveguides. The paper does not specify how 128 channels are obtained—whether by multiple waveguides (SDM), polarization multiplexing, or wavelength reuse—nor does it provide a loss budget or crosstalk estimate for that configuration. Without this, the 1.6 TB/s figure is not tied to a concrete physical design.
  4. [Sec. IV-B and Table IV] The power analysis omits the dominant term. Equation (4) defines Ptotal = Plaser + PTX + PRX, but no derivation of Plaser is given, and the quoted per-channel PTX + PRX of 1.22 mW + 0.92 mW = 2.14 mW cannot produce the reported 6.59 W for 128 channels, which implies about 51.5 mW per channel. The laser power must be derived from the Table II loss budget, and the receiver sensitivity or BER target must be stated, before the power comparison in Fig. 7 can be interpreted.
minor comments (5)
  1. [Fig. 1 caption] The caption reads "fully holomorphic encryption" and should be "fully homomorphic encryption."
  2. [Sec. IV-A and Sec. V] There are several typos: "architectures scalibility" should be "architecture's scalability," and "optomized" should be "optimized."
  3. [Sec. III-A] Reference [27] is cited for 64 wavelengths at 10 Gb/s, not 100 Gb/s per wavelength; the paper should either use that citation consistently or supply a separate reference for 100 Gb/s-class WDM links.
  4. [Table III] The table column labeled "Bitwidth" mixes electrical bus width with optical channel count; the optical-side columns should be labeled "number of optical channels" to avoid confusion.
  5. [Sec. IV-B] The sentence giving per-channel power says "PTX = 1.22mW and PTX = 0.92mW," where the second quantity should presumably be PRX.

Circularity Check

1 steps flagged · score 8.0 of 10

Headline 1.6 TB/s throughput is an assumed 100 Gb/s per channel times an assumed 128 channels, presented as a measurement after a 10 Gb/s two-channel simulation.

  1. fitted input called prediction [Section IV-A, Timing Analysis]
    "Data was sent at 10Gb/s via a pseudo-random bit sequence (PRBS) generator, which needed 6.4ns to produce a complete sequence. ... Each OptoLink channel achieved a data rate of 100Gb/s or 12.5GB/s, with a total bandwidth of 1.6TB/s for 128 channels, sufficient for FHE workloads."

    The only simulated evidence in this section is a 10 Gb/s PRBS over two wavelengths, yielding 64 bits in 6.4 ns. The next sentence jumps to 100 Gb/s per channel, a 10x increase, and then multiplies by 128 channels to obtain 1.6 TB/s. Neither the per-channel rate nor the channel count is derived from any measurement, link-budget, BER, crosstalk, or bandwidth-penalty analysis; Table II is a static loss budget with no data-rate dependence. The headline throughput is therefore the product of assumed inputs, relabeled as an achieved result.

full rationale

The paper's central performance claim is not an independent result: 1.6 TB/s = 12.5 GB/s × 128, where both factors are assumptions rather than measurements. The only demonstrated rate is 10 Gb/s per channel on two channels, so the 100 Gb/s per-channel figure is an extrapolation presented as 'achieved.' This is a reduction-by-construction of the headline number. The paper does not rely on self-citation or a uniqueness theorem imported from the authors' prior work, and the separate power and area analyses are self-contained estimates. However, because the abstract and conclusion advertise the 1.6 TB/s as the main contribution, the core result reduces to the assumed parameters, warranting a high circularity score.

Assumptions & free parameters 3 free parameters · 3 assumptions · 1 invented entities

The paper's central throughput claim rests on assumed per-channel data rates and a chosen channel count, plus literature-derived photonic parameters that are not validated at scale. The electrical baseline is insufficiently specified, making the comparative claims unverifiable.

free parameters (3)
  • per-channel optical data rate = 100 Gb/s (assumed)
    The paper multiplies this assumed per-channel rate by 128 channels to obtain 1.6 TB/s. The simulation in Sec IV-A actually transmits at 10 Gb/s, so this rate is a free parameter chosen to reach the headline number.
  • number of optical channels = 128 (design choice)
    The choice of 128 channels yields 1.6 TB/s at 100 Gb/s each; 64, 192, and 1024 channel variants are also projected without additional simulation.
  • electrical baseline bitrate = 5.26 GB/s at 128-bit
    The electrical interconnect is claimed to deliver only 5.26 GB/s at 128-bit (Table III), producing the 300x ratio. No clock frequency, wire model, or synthesis report is given, so this baseline is effectively a chosen number.
assumptions (3)
  • ad hoc to paper A 10 Gb/s single-channel optical link simulation is representative of a 128-channel system running at 100 Gb/s per channel.
    Sec IV-A demonstrates two channels at 10 Gb/s; the paper then assumes each channel in the full system runs at 100 Gb/s without modeling crosstalk, thermal drift, packaging, or laser power scaling.
  • domain assumption The photonic parameters in Table II (laser 5 dB, coupler 1 dB, etc.) and the per-transceiver powers from Ref. [29] remain valid when scaling to 128 channels.
    Power and area estimates in Sec IV-B and IV-C rely on these literature values, but no integrated simulation or measurement validates them at the claimed scale.
  • ad hoc to paper The electrical interconnect synthesized with a 32 nm library is a fair baseline for comparing bandwidth and latency against a photonic link.
    The electrical numbers (3.04 ns latency, 5.26 GB/s, sub-mW power) are not accompanied by a described netlist, frequency, or wire length, so the comparison is not established.
invented entities (1)
  • OptoLink architecture
    purpose: A WDM/SDM photonic interconnect connecting NTT modules to memory in FHE accelerators to overcome memory bandwidth bottlenecks.
    The only evidence is a Synopsys OptoCompiler simulation of two channels at 10 Gb/s over a 1000 um waveguide (Fig. 6). The claimed 100 Gb/s per channel and 1.6 TB/s aggregate are not measured or independently verified.

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Cite this review

Pith. "Pith review of Leveraging Photonic Interconnects for Scalable and Efficient Fully Homomorphic Encryption." pith.science (2026). https://pith.science/paper/ZK5AUDGZ

@misc{pith2026250612962,
  author       = {Pith},
  title        = {Pith review of: Leveraging Photonic Interconnects for Scalable and Efficient Fully Homomorphic Encryption},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZK5AUDGZ}},
  note         = {Machine review of arXiv:2506.12962}
}
read the original abstract

Fully Homomorphic Encryption (FHE) facilitates secure computations on encrypted data but imposes significant demands on memory bandwidth and computational power. While current FHE accelerators focus on optimizing computation, they often face bandwidth limitations that result in performance bottlenecks, particularly in memory-intensive operations. This paper presents OptoLink, a scalable photonic interconnect architecture designed to address these bandwidth and latency challenges in FHE systems. OptoLink achieves a throughput of 1.6 TB/s with 128 channels, providing 300 times the bandwidth of conventional electrical interconnects. The proposed architecture improves data throughput, scalability, and reduces latency, making it an effective solution for meeting the high memory and data transfer requirements of modern FHE accelerators.

Figures

Figures reproduced from arXiv: 2506.12962 by the authors.

Figure 1
Figure 1. Computational flow in fully holomorphic encryption (FHE). [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Two transmitters and receivers are connected by a WDM photonic [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Schematic representation of the OptoLink architecture connecting four NTT modules via five waveguides. Wavelengths λ1 − λ16 are allocated for input data transmission, while λ17 −λ24 handle output data transmission. C. Scalable OptoLink Network Architecture The OptoLink architecture, depicted in [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: Simulation configuration for a single channel in the [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: (a-b) Electrical input signals supplied to modulator MRRs across [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

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Forward citations

Cited by 1 Pith paper

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