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REVIEW 4 major objections 4 minor 29 references

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design

T0 review · 4 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read An LLM-based framework generates working analog testbench code from research paper descriptions, with all pipeline stages reporting success above 80 percent on a 63-experiment benchmark.

desk verdict A useful engineering paper on LLM-generated analog testbenches whose headline accuracy is real only under perfect upstream inputs and against author-built golden models; worth refereeing despite that. read the letter →

arxiv 2507.09965 v1 pith:GVMA7QAC submitted 2025-07-14 cs.MA cs.AR

Weiyu Chen , Chengjie Liu , Wenhao Huang , Jinyang Lyu , Mingqian Yang , Yuan Du , Li Du , Jun Yang This is my paper
classification cs.MAcs.AR
keywords analogcircuitdesigntestbenchgenerationlargelanguagemodelsmulti-agentsystemTEDcodeVerilog-Averificationretrieval-augmentedautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

AnalogTester is an LLM-based framework that targets the last manual bottleneck in analog circuit automation: building the testbench that stimulates a circuit, checks its outputs, and computes performance metrics. Its pipeline reads a paper's text, figures, and tables through information-extraction agents, turns the extracted simulation requirements into concrete experimental schemes, and writes runnable testbench code in the TED analog design environment. The authors report that on eight published papers covering op-amps, bandgap references, and low-dropout regulators, all three pipeline stages succeed more than 80 percent of the time across 63 experiments, with a full paper's testbenches produced in under an hour. The point of the work is that if these numbers hold, replicating and optimizing published analog circuits no longer requires an expert to hand-build verification setups, and the resulting code and knowledge bases become training material for further design automation.

What carries the argument

The load-bearing machinery is a three-stage LLM agent pipeline paired with two curated knowledge bases and a verification loop. The first knowledge base is a repository of 36 experimental templates, each specifying PVT conditions, testbench architecture, simulation type, and computation method for one performance metric. The second is a hand-curated database of 72 TED functions—TED being a Python-based analog design environment—that supplies the LLM with the function names, arguments, and usage patterns needed to write valid testbench code. The verification loop runs each generated testbench against a golden Verilog-A model of the circuit, compares the computed metric to the model's expected value, and sends execution errors back to the LLM for repair, repeating until the result matches. The same loop, extended by jointly generating new Verilog-A models and TED code, is what the paper uses to scale the framework to new circuit types.

What would settle it

Run the generated testbenches for all eight benchmark papers against transistor-level simulations of the actual circuits and compare the computed metrics; if a bandgap-reference or low-dropout testbench that passed the golden-model check reports wrong values at the transistor level, the claimed success rates measure self-consistency rather than correct measurement.

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Extended reading notes

Core claim

The paper's central claim is that analog testbench generation, previously done manually by experienced designers, can be decomposed into three LLM-driven tasks and made reliable through curated knowledge and iterative repair. AnalogTester first extracts simulation conditions, targets, and cited figures and tables from a paper; the extraction agent then checks its own output against a spec list and refines it. A second agent matches each extracted experiment to one of 36 templates covering the standard performance metrics for op-amps, bandgap references, and LDOs, adapting the template with the paper's specific conditions. A third agent writes TED testbench code using a hand-built database of 72 TED functions, executes the code against a golden Verilog-A model of the device under test, and feeds syntax and functional errors back to the LLM until the results match the golden model. Across a benchmark of eight papers and 63 experiments, the authors report success rates of 84 percent for information extraction, 86 percent for scheme generation, and 89 percent for testbench code generation, with an average of roughly two minutes per experiment; for one example op-amp, the generated testbenches reproduced all 11 metrics obtained with manually constructed testbenches in a commercial EDA tool, and the framework can generate new templates and Verilog-A models for circuits outside the initial three types.

Load-bearing premise

The results stand on the assumption that the authors' golden Verilog-A models faithfully represent the real circuits from the benchmark papers, because those models are the only reference against which every generated testbench is judged.

Editorial extensions

If this is right

  • A paper's testbench suite can be generated automatically in under an hour, so researchers can replicate published op-amp, bandgap-reference, and LDO designs without manual verification setup.
  • The generated testbenches can feed a closed-loop design-automation flow, allowing schematic generation, simulation, and optimization to run without human-written testbenches.
  • The TED function database and the generated code corpus become a training set for LLMs specialized in analog design, reducing the data scarcity that limits current models.
  • The paper's expansion loop generates a new experimental template and a matching golden Verilog-A model, then verifies the pair through the mutual TED-and-Verilog-A check.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural next experiment would run every generated testbench against transistor-level simulations of the eight benchmark circuits; the paper only cross-checks the op-amp against a commercial EDA tool, so the functional success rates for bandgap references and LDOs are not yet validated against real transistor behavior.
  • Because the evaluation delivers manually verified upstream inputs to each stage, the per-stage success rates are upper bounds on what an unattended end-to-end run would achieve; an integrated experiment without human aid would give the user-facing accuracy.
  • The expansion loop still passes through human validation before a new template enters the repository, so the claimed scalability depends on expert labor until that validation step is itself automated or replaced by a stronger reference model.
  • If the golden Verilog-A models were constructed using the same metric definitions and simulation assumptions as the template database, the functional checks mainly demonstrate self-consistency; correlating generated results against measured silicon would test whether the testbenches measure the real circuits.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. AnalogTester is a multi-agent LLM framework that takes a research paper as input and produces TED testbench code for analog circuits. The pipeline has three stages: information extraction from text, tables, and figures; experimental scheme generation from a 36-template database with retrieval-augmented generation; and TED code generation from a 72-function database with iterative syntax and functional repair. The evaluation covers 8 papers (3 op-amps, 3 BGRs, 2 LDOs) and 63 experiments, reporting 84%, 86%, and 89% success rates for extraction, scheme generation, and code generation, plus ablations showing that RAG, the TED function database, and iterative repair improve performance. The authors further claim that a full paper can be processed in under an hour and that the framework can generate training data for analog-EDA LLMs.

Significance. If the headline numbers were measured against trustworthy ground truth, the paper would be a useful contribution: automatic analog testbench generation is a real bottleneck, and the task decomposition plus knowledge repositories are sensible engineering choices. The paper's strengths include a concrete 63-experiment benchmark across three circuit families, a modular architecture that is easy to extend, and an honest reporting of several evaluation constraints. The main weakness is that the reference used for functional verification consists of author-built Verilog-A models covering the same metrics as the templates, with only one OTA cross-checked against Cadence Virtuoso, and the per-task accuracies are conditional on manually corrected upstream inputs. These issues prevent the quantitative central claim from being accepted as stated, but they are addressable in revision.

major comments (4)
  1. [Section III-C] The verification loop uses author-built 'golden Verilog-A' models that are constructed to cover the same performance metrics as the experimental template database. Task 3's 89% accuracy in Table III therefore measures whether the generated TED code reproduces the authors' behavioral models, not whether it correctly measures the real circuits described in the benchmark papers. Only one OTA is cross-checked against Cadence Virtuoso (Table II), and no transistor-level validation is reported for any BGR or LDO. The central claim requires either independent validation of the golden models (e.g., transistor-level simulation for all or a representative sample of benchmark circuits) or a re-scoped claim that the framework achieves self-consistency with respect to author-defined reference models.
  2. [Section V-A and Table III] The statement 'We manually ensure that the inputs upstream task for each task is correct, decoupling the success rates between tasks' means the three >80% rates are component-level conditional accuracies, not end-to-end pipeline accuracies. The abstract's claim of 'automated Testbench generation capabilities' and the conclusion's 'successfully generates testbenches' are therefore stronger than the evidence supports. Please report an end-to-end success rate over the 63 experiments without manual upstream correction, and report human correction and confirmation time separately from the sub-hour-per-paper claim. Section IV's 'After manual confirmation' step should also be included in this accounting.
  3. [Table II and Section IV] Table II reports numerically identical TED and Cadence Virtuoso results for all ten metrics. Please clarify whether the golden Verilog-A model for this OTA was calibrated to the Virtuoso results or derived independently, and state whether the same calibration procedure applies to the BGR and LDO golden models. If the golden models are fitted to the same quantities they are later used to verify, the Table II cross-check does not break the self-consistency concern.
  4. [Section V-B, Figures 7 and 8] The ablation results demonstrate that retrieval augmentation and iterative repair improve functional success within the same golden-model loop. However, because the loop's reference is the author-built Verilog-A models, the ablations do not establish correctness with respect to real circuit behavior; they show internal consistency of the generated code with the reference models. The text should state this limitation explicitly when interpreting the ablation results, and the phrase 'functional verification' should be qualified accordingly.
minor comments (4)
  1. [Section I] The contribution list contains 'operated amplifiers' where 'operational amplifiers' is intended; please correct the typo.
  2. [Section V-A and V-B] The main evaluation does not state the maximum iteration count used for Task 3; Section V-B mentions a maximum of 9 iterations only for the control group. Please specify the setting used for the Table III experiments to enable reproduction.
  3. [General] The paper would benefit from a data/code availability statement or an appendix with the exact prompts, the TED function database schema, and the simulator backend, since LLM-based systems are highly sensitive to prompt and toolchain details.
  4. [References] Reference [13] is incomplete: it lacks a publication venue and year; please complete the entry.

Circularity Check

2 steps flagged · score 6.0 of 10

Table III's 80%+ accuracy is scored against author-built golden Verilog-A models that cover the same performance metrics as the template database, and Section V-A manually corrects upstream task inputs; the figures certify self-consistency and conditional component accuracy, not independent end-to-end correctness.

  1. self definitional [Section III-C, Testbench Code Generation]
    "At the same time, we have also modelled the Verilog-A models of op-amp, BGR and LDO for the performance metrics included in the experimental scheme template database mentioned earlier. These golden Verilog-A are used to verify the generated TED code."

    The 'golden' reference is not an independent ground truth: the authors built these Verilog-A models specifically for the same performance metrics that appear in the experimental template database used to generate the schemes and code. The generated TED testbench is therefore judged correct when its simulation results match a model that encodes the same template assumptions (idealized op-amp/BGR/LDO behavior) that guided generation. This makes Task3's 89% a self-consistency score between the generator and the authors' own models. The only independent calibration is one OTA in Table II; no BGR or LDO in the 8-paper benchmark is checked against transistor-level simulation or measured silicon.

  2. fitted input called prediction [Section V-A, Basic Evaluation Method]
    "We manually ensure that the inputs upstream task for each task is correct, decoupling the success rates between tasks."

    The full-pipeline claim ('the full process of constructing a paper's testbench' under an hour) is evaluated after manually fixing the output of every upstream task. Thus the reported Task1/Task2/Task3 accuracies are conditional on perfect prior outputs, not the probability that the automatic pipeline produces a correct testbench from a raw paper. The 'prediction' of end-to-end automation is not derived by the system; the inputs to each stage are hand-supplied, so the success rates in Table III cannot be combined as an end-to-end success rate.

full rationale

The core generation chain (paper -> extracted specification -> experimental scheme -> TED code) is not itself circular: the TED code is genuinely synthesized from extracted paper text and template-based schemes, and one OTA (Table II) is cross-checked against Cadence Virtuoso, which is independent evidence that the loop can work for at least one circuit. However, the Task3 verification oracle is the authors' own golden Verilog-A models, constructed to cover exactly the same performance metrics as the experimental template database that drives testbench generation. Passing 'functional verification' therefore means the generated testbench reproduces numbers from models that encode the same idealizations as the generator's own inputs; for the 8-paper benchmark this is self-consistency, not validation against real transistor-level or measured behavior. The Section V-A statement that upstream task inputs are manually ensured correct further decouples the three tasks, so Table III reports conditional component accuracies rather than end-to-end automatic performance. The self-citations to prior author work (refs [13], [14]) are background examples of LLM analog design and are not load-bearing for the verification premise, so they do not raise the score further. Overall, the central benchmark claim is partially circular because the definition of 'correct' Task3 output is fixed by the authors' own models, while the one independent OTA check prevents the entire result from reducing to pure tautology.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The framework's central claims rest on manually curated datasets, author-built reference models, and a commercial LLM. None of these are independently released or benchmarked. The ledger lists the configuration choices and background assumptions that a reader must accept without direct evidence.

free parameters (4)
  • maximum iteration count = 9
    The repair loop configures a maximum of 9 iterations; ablation compares single-pass with 9 iterations but provides no sensitivity analysis to justify this number.
  • LLM sampling temperature = 0
    Temperature 0 is chosen for deterministic outputs; the effect of this choice on generation success is not examined.
  • experimental template database size = 36 templates
    The database of 36 templates is manually curated with LLM assistance and human validation; coverage is assumed complete for op-amp, BGR, and LDO metrics in Table I.
  • TED function database size = 72 functions
    A manually curated corpus of 72 TED functions is asserted to cover testbench construction, but no coverage analysis is shown.
assumptions (4)
  • domain assumption The golden Verilog-A models correctly represent the benchmark circuits' real behavior.
    Section III-C uses these models as the verification reference; without independent validation, the loop only confirms that generated code reproduces the authors' models.
  • domain assumption GPT-4o with RAG can reliably extract structured simulation info from papers and generate syntactically correct TED code.
    All three agents rely on LLM competence; errors are repaired iteratively but no failure taxonomy is reported.
  • domain assumption TED is a valid, complete environment for analog testbench construction.
    Adopted from reference [10]; the paper does not independently evaluate TED's coverage or fidelity.
  • domain assumption Manually correcting upstream inputs does not invalidate per-task success rates.
    Section V-A decouples tasks by manual correction, implicitly assuming each stage's success is independent and representative.

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Cite this review

Pith. "Pith review of AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design." pith.science (2026). https://pith.science/paper/GVMA7QAC

@misc{pith2026250709965,
  author       = {Pith},
  title        = {Pith review of: AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/GVMA7QAC}},
  note         = {Machine review of arXiv:2507.09965}
}
read the original abstract

Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation.

Figures

Figures reproduced from arXiv: 2507.09965 by the authors.

Figure 1
Figure 1. The system workflow of AnalogTester. • Picture extraction: Screen different types of experimental result graphs through visual multimodal LLM and design prompts for them separately. Then, conduct in-depth processing on the horizontal and vertical coordinates, leg￾ends, text annotations, curve trends, etc. of the pictures. • Table extraction: Mainly for the comparison work tables and experimental result tables, summa… view at source ↗
Figure 2
Figure 2. Experimental Scheme and Experimental Template Generation Frame [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Collaborative Generation and Verification of Testbench and Verilog-A. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: The extracted experimental information is in JSON [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 4
Figure 4. Figure 4: Core prompt and example of results of information extraction agent. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: An example of experimental scheme generation result. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 8
Figure 8. Figure 8: Results of AnalogTester Iteration Framework Ablation Experiment. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 7
Figure 7. Figure 7: Ablation experiment on TED generation task with maximum iteration [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

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