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Solving the compute crisis with physics-based ASICs

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper argues that application-specific chips which compute with natural physical dynamics, rather than enforcing digital abstractions, can overcome the AI energy and scaling crisis.

desk verdict A clear, honest roadmap paper that reframes existing physics-based computing work under one umbrella, but the 'necessary evolution' claim outruns the evidence it cites. read the letter →

arxiv 2507.10463 v1 pith:PT4PVQUU submitted 2025-07-14 cs.ET cs.AR

Maxwell Aifer , Zach Belateche , Suraj Bramhavar , Kerem Y. Camsari , Patrick J. Coles , Gavin Crooks , Douglas J. Durian , Andrea J. Liu
show 6 more authors
Anastasia Marchenkova Antonio J. Martinez Peter L. McMahon Faris Sbahi Benjamin Weiner Logan G. Wright
This is my paper
classification cs.ETcs.AR
keywords physics-basedASICscomputecrisishardware-softwareco-designenergyefficiencyprobabilisticcomputingthermodynamicIsingmachinesanalogneuralnetworks
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that the path out of the AI compute crisis—unsustainable data-center energy use, billion-dollar training runs, and faltering CMOS scaling—is to stop fighting the physics of silicon. It proposes physics-based ASICs, application-specific integrated circuits that deliberately use the natural dynamics of circuits, including stochasticity, memory, feedback, and asynchrony, as the computation itself, rather than spending energy to enforce idealized digital behavior such as statelessness, unidirectionality, determinism, and synchronization. The paper lays out a design strategy in which algorithms and hardware are co-designed so that applications such as diffusion models, sampling, optimization, neural inference, and molecular simulation land in the set of operations a physical device can do natively, and it quantifies the attainable gain with runtime and energy ratios under Amdahl's Law. If the argument holds, specialized physics-based chips could deliver substantial energy savings and new capabilities that general-purpose digital hardware cannot reach, shifting future high-performance computing toward heterogeneous systems of specialized physical processors.

What carries the argument

The central object is the physics-based ASIC itself, defined by relaxing the four conventional abstractions of statelessness, unidirectionality, determinism, and synchronization so that computation is realized directly as a physical process. The argument's quantitative engine is algorithmic co-design: applications define a set of possible algorithms, physical structures define a set of algorithms they can run efficiently, and the design goal is to maximize their overlap while respecting Amdahl's Law, which limits the attainable speedup to a factor of $1/(1-x)$ where $x$ is the fraction of runtime movable onto the physics-based ASIC. Performance is assessed by runtime and energy ratios relative to state-of-the-art digital hardware, and the paper also proposes physical machine learning, in which the hardware itself learns its parameters from physical dynamics, as a route to co-design without a separate digital training loop.

What would settle it

A concrete test is to build a tile-based physics-based ASIC scaled to a production-size problem in diffusion sampling or combinatorial optimization, co-design an algorithm for it, and measure end-to-end runtime and energy against a state-of-the-art GPU; the central claim fails if the measured speedup and energy ratios are not both above 1 at that scale, or if the Amdahl fraction $x$ falls below $1 - 1/S$ for the claimed speedup $S$.

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Extended reading notes

Core claim

The paper's central claim is that the compute crisis can be addressed by a class of chips it calls physics-based ASICs: circuits that let computation be carried out by the natural physical dynamics of the device instead of forcing the device to imitate an ideal digital machine. Conventional ASICs spend energy, time, and complexity to approximate four abstractions that are not exactly realizable in physics: statelessness, unidirectionality, determinism, and synchronization. The paper argues that when these constraints are relaxed, components can be stateful, bidirectionally coupled, stochastic, and asynchronous, and a computed result becomes the outcome of a real physical process—for example, thermodynamic relaxation performing sampling or linear algebra. It claims this can fuse many operations, save power, and in several demonstrated or predicted cases beat CPU and GPU solvers in speed or energy, citing a latch-based Ising machine solving 1440-spin problems over 1000 times faster than a CPU solver and optical neural networks operating below one photon per scalar multiplication. The paper concludes that physics-based ASICs are not just an alternative but a necessary evolution of computing, deployed in heterogeneous systems alongside CPUs and GPUs.

Load-bearing premise

The roadmap holds only if, after algorithmic co-design, a large enough fraction of each real workload can be run on the physics-based ASIC, and the cost of moving data on and off the chip stays small enough, that Amdahl's Law does not erase the raw efficiency gain; the paper itself notes in its Phase-1 discussion that larger prototypes often lose their speed-up to exactly these data-transfer costs.

Editorial extensions

If this is right

  • If the central claim is right, the first practical demonstrations will be domain-specific: small physics-based ASICs will beat CPU or GPU solvers on particular workloads such as Ising optimization, sampling, or linear algebra, before they compete on general-purpose tasks.
  • Co-design becomes the main engineering lever: pushing algorithmic complexity into subroutines that run on the ASIC increases the fraction $x$ that Amdahl's Law rewards, so new algorithms will be judged by how much of their runtime can be made physical.
  • Heterogeneous systems will emerge in which CPUs, GPUs, and multiple physics-based ASICs share a workload, with a compiler mapping each step of a high-level program to the best device.
  • Energy efficiency is expected to arrive before raw speed: early physics-based ASICs may match a GPU's output while consuming far less power, especially for diffusion, sampling, and stochastic neural-network workloads.
  • Once scaled and integrated, the technology could enable computations that digital machines cannot do affordably, such as approximation-free Bayesian inference for reliable AI predictions and large-scale molecular dynamics.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the hardware-lottery dynamic the paper describes is real, the largest effect of a successful physics-based ASIC may be to change which algorithms researchers choose to work on: algorithms that map naturally to physical dynamics would begin to win over algorithms tuned for GPUs.
  • A testable extension of the roadmap is to measure, for each candidate workload, the Amdahl fraction $x$ and the data-transfer energy at production scale; the paper's own Phase-1 caveat suggests that these, not the raw on-chip gain, will separate the workloads that benefit from those that do not.
  • The energy-time-accuracy tradeoff the paper notes could be developed into a quantitative design criterion: for a given physical device, the optimal operating point in voltage, clock rate, and noise level would be chosen by optimizing a three-way tradeoff rather than by maximizing determinism.
  • If physical machine learning matures, the same hardware that computes could also learn its own parameters without a digital co-processor, which would invert the usual assumption that hardware must be designed to be trainable by software.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper is a perspective/roadmap paper arguing that physics-based ASICs—chips that exploit natural physical dynamics rather than enforcing digital abstractions such as statelessness, unidirectionality, determinism, and synchronization—could provide order-of-magnitude gains in energy efficiency and throughput for AI and scientific workloads. It defines the paradigm, surveys platforms (memristors, Ising machines, p-bits, thermodynamic computers, photonic systems), proposes a top-down/bottom-up co-design strategy, introduces kernel-level speedup and energy ratios RT(ℓ) and RE(ℓ), invokes Amdahl's law, discusses physical machine learning and physical learning, lists target applications (neural networks, diffusion models, sampling, optimization, scientific simulation, analog data analysis), and lays out a three-phase roadmap from proof-of-concept to system integration. The paper contains no new measurements, derivations, or system-level models; its argument is qualitative and vision-oriented.

Significance. If the central claim were established, the paper would identify a high-impact direction for post-CMOS computing and address real concerns about AI energy and hardware scaling. The manuscript is useful as a synthesis and a call to action: it explicitly acknowledges Amdahl's law, memory-bandwidth limitations, the difficulty of physical machine learning optimization, barren plateaus, and sim2real gaps, and it names concrete prototype results. Its main weaknesses are that the load-bearing evidence consists largely of kernel-level or small-scale demonstrations, several from the authors' own prior work, and that no end-to-end system-level accounting is provided. As a perspective, the paper is coherent and readable, but the strength of the conclusions currently exceeds the strength of the evidence.

major comments (3)
  1. [III.B–III.C and V, Phase 1] The performance framework in Eqs. (1) and (2) defines RT(ℓ) and RE(ℓ) at the kernel level, and the Amdahl discussion in Section III.C uses only an unaccelerated runtime fraction x. Neither accounts for the time and energy of loading data onto the physics-based ASIC and reading results off it. Section V, Phase 1 then concedes that for larger problems the latch-based Ising prototype 'often cannot achieve the same speed-up, due to the cost of loading data onto and reading data off of the physics-based ASIC' [12]. Since the cited evidence does not include an end-to-end system-level demonstration, the paper's central claim of substantial system-level gains is not supported by the presented material. The manuscript should either add a quantitative system-level model that includes I/O and memory bandwidth or explicitly scope its claims to kernel-level advantages.
  2. [V, Phase 2] The scalability discussion asserts that tile-based designs and reconfigurable coupling 'could potentially get as large as GPUs' but provides no quantitative treatment of the costs that dominate at large scale: inter-tile communication bandwidth, minor-embedding overhead for arbitrary sparse graphs, analog noise accumulation, and on-chip routing of mixed-signal blocks. Because the 'compute crisis' motivating the paper is specifically a large-scale problem, these omissions are load-bearing. The passage should be labeled as conjecture unless accompanied by scaling estimates or references to validated large-scale designs.
  3. [VI.A] The conclusion that physics-based ASICs are 'not only a viable alternative but a necessary evolution in how we compute' is an evaluative claim that outruns the evidence in the manuscript. The paper itself lists major open challenges—PML optimization difficulty, sim2real gaps, bandwidth-limited prototypes, and the absence of demonstrated large-scale integration—so the evidence supports a promising research direction rather than a demonstrated necessity. The conclusion should be rephrased to match the evidentiary level, or the authors should supply the missing system-level demonstration or model.
minor comments (5)
  1. [I] 'Miniturization effects' should be 'miniaturization effects'.
  2. [III.B, Eqs. (1)–(2)] In the sentence after Eq. (2), 'either RT(ℓ) or RT(ℓ) is greater than one' should read 'either RT(ℓ) or RE(ℓ) is greater than one'.
  3. [IV.A.4] 'quadratic unconstained binary optimization' should be 'quadratic unconstrained binary optimization'.
  4. [VI.B] 'paralellism' should be 'parallelism'.
  5. [References] Reference [2] lists the year as 2014, but the cited arXiv paper (2405.21015) appeared in 2024.

Circularity Check

0 steps flagged · score 2.0 of 10

No formal circularity: this is a position/roadmap paper, and its cited examples (including some from the authors) are external demonstrations rather than fitted inputs; the main weakness is an acknowledged I/O evidence gap, not a circular derivation.

full rationale

The paper does not contain a derivation whose conclusion is built into its assumptions. Section III.B defines RT(ell) and RE(ell) as ratios of SOTA runtime/energy to physics-based-ASIC runtime/energy; these are definitions of a performance criterion, not fitted quantities later relabeled as predictions. Section III.C invokes Amdahl's Law as an upper bound, not as a measured result. The evidence for 'substantial gains' includes several works by the current authors (e.g., thermodynamic-computing refs. [19,26,34-39], physical-learning refs. [10,11], and optical-network refs. [47,74]), but those are published demonstrations and asymptotic analyses cited as support; the paper does not reduce its central claim to those citations, and the same claims are also supported by external work (e.g., latch-based Ising [12], coupled-oscillator Ising [13,76], and photonic inference [74]). No equation in the paper is constructed so that its output equals its input. The most important caveat is an evidence gap rather than circularity: Section V Phase 1 concedes that for larger problems latch-based Ising prototypes 'often cannot achieve the same speed-up, due to the cost of loading data onto and reading data off of the physics-based ASIC,' so the system-level 'necessary evolution' claim is not demonstrated end-to-end. This is a correctness/evidence risk and should be weighed there, not as circularity. Score 2 reflects minor self-citation in the supporting evidence without a circular derivation chain.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The paper fits no model and introduces no free parameters or new physical entities. It relies on domain assumptions about the cost of digital abstraction, the scalability of analog and physical substrates, and the effectiveness of co-design in beating Amdahl's law.

assumptions (4)
  • domain assumption Enforcing statelessness, unidirectionality, determinism, and synchronization in conventional ASICs incurs costs that grow quickly, and relaxing them yields large energy and time savings.
    Invoked in Sections II.B and II.D to justify the whole premise; no quantitative account of these costs is given.
  • domain assumption Useful computations can be implemented as exact physical processes with sufficient accuracy and programmability for real workloads, despite device variability and noise.
    The paper acknowledges in Sections II.B, III.E, and IV.A.1 that noise, sim2real gap, and precision are challenges, but the roadmap assumes they can be overcome.
  • domain assumption After algorithmic co-design, the fraction x of workload amenable to physics-based ASICs is large enough that Amdahl's Law does not erase the advantages.
    Section III.C introduces Amdahl's Law and Section III.D argues complexity can be pushed to increase x, but no quantitative demonstration is provided.
  • domain assumption Scalable silicon manufacturing can host stateful, bidirectional, nondeterministic, and asynchronous devices at GPU-like scale.
    Section II.C excludes non-scalable platforms and Section V Phase 2 discusses tiling and reconfigurability as open research, not demonstrated achievements.

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Cite this review

Pith. "Pith review of Solving the compute crisis with physics-based ASICs." pith.science (2026). https://pith.science/paper/PT4PVQUU

@misc{pith2026250710463,
  author       = {Pith},
  title        = {Pith review of: Solving the compute crisis with physics-based ASICs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PT4PVQUU}},
  note         = {Machine review of arXiv:2507.10463}
}
read the original abstract

Escalating artificial intelligence (AI) demands expose a critical "compute crisis" characterized by unsustainable energy consumption, prohibitive training costs, and the approaching limits of conventional CMOS scaling. Physics-based Application-Specific Integrated Circuits (ASICs) present a transformative paradigm by directly harnessing intrinsic physical dynamics for computation rather than expending resources to enforce idealized digital abstractions. By relaxing the constraints needed for traditional ASICs, like enforced statelessness, unidirectionality, determinism, and synchronization, these devices aim to operate as exact realizations of physical processes, offering substantial gains in energy efficiency and computational throughput. This approach enables novel co-design strategies, aligning algorithmic requirements with the inherent computational primitives of physical systems. Physics-based ASICs could accelerate critical AI applications like diffusion models, sampling, optimization, and neural network inference as well as traditional computational workloads like scientific simulation of materials and molecules. Ultimately, this vision points towards a future of heterogeneous, highly-specialized computing platforms capable of overcoming current scaling bottlenecks and unlocking new frontiers in computational power and efficiency.

Figures

Figures reproduced from arXiv: 2507.10463 by the authors.

Figure 1
Figure 1. FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
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Figure 2. FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
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Figure 3. FIG. 3 [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
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Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
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Figure 5. Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]

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Forward citations

Cited by 3 Pith papers

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    Synchronization: Usually, signals in differ- ent parts of a conventional ASIC are syn- chronized with each other according to a centralized clock. 4 These properties are not physically realizable in an exact sense: real components exhibit mem- ory effects, feedback, noise, and thermal fluctua- tions. Enforcing these ideal behaviors incurs en- ergy, latenc...

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    Components that are not responsi- ble for storing information are assumed to behave as if their outputs depend only on FIG

    Statelessness: In conventional ASICs there is usually a clear separation between mem- ory and computation, which are handled by separate components in different loca- tions. Components that are not responsi- ble for storing information are assumed to behave as if their outputs depend only on FIG. 2. Traditional ASICs vs. Physics-based ASICs. As illustrate...

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    For example, a NOT gate should re- spond to changes at its input, but its out- put should not affect its input

    Unidirectionality: Primitive components of conventional ASICs are designed to propa- gate information in a single direction; they have designated input and output termi- nals. For example, a NOT gate should re- spond to changes at its input, but its out- put should not affect its input. Because of this, creating feedback loops in conven- tional ASICs requ...

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.