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REVIEW 4 major objections 5 minor 1 cited by

OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper presents OpenGCRAM, an open-source compiler that takes user memory specifications and produces gain-cell memory bank layouts for TSMC 40 nm, with HSPICE-verified area, delay, and power.

desk verdict OpenGCRAM is a real, useful step forward for open-source memory compilation of Si-Si GCRAM, but the OS-OS results are model-in-the-loop predictions rather than validated compiler output. read the letter →

arxiv 2507.10849 v1 pith:3SKSP753 submitted 2025-07-14 cs.AR cs.SYeess.SY

Xinxin Wang , Lixian Yan , Shuhan Liu , Luke Upton , Zhuoqi Cai , Yiming Tan , Shengman Li , Koustav Jana
show 5 more authors
Peijing Li Jesse Cirimelli-Low Thierry Tambe Matthew Guthaus H.-S. Philip Wong
This is my paper · ORCID
classification cs.ARcs.SYeess.SY
keywords gain-cellmemory(GCRAM)compilerdesign-spaceexplorationAIworkloadsoxide-semiconductortransistorsretentiontimeTSMC40nmon-chip
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

OpenGCRAM is an attempt to make gain-cell memory as straightforward to produce as SRAM by automating the whole macro-generation flow. The paper claims that a user can specify word size, number of words, and peripheral options, and receive a complete dual-port GCRAM bank: a SPICE netlist, a layout that passes foundry design-rule and schematic-matching checks for TSMC 40 nm, and HSPICE-simulated area, delay, and power. This matters because GCRAM stores a bit with two transistors instead of six, so it can shrink on-chip memory and cut leakage, while its retention can be tuned from microseconds to seconds to match different AI workload lifetimes. The paper further claims that an oxide-semiconductor variant, in which both gain-cell transistors are oxide-semiconductor devices, reduces the bitcell to 11 percent of a 6T SRAM cell's area, with millisecond retention. If these claims hold, designers can explore the GCRAM design space quickly and generate tapeout-ready macros without hand-drawn analog layout.

What carries the argument

The central mechanism is the two-transistor gain cell, which stores a bit as charge on a storage node: one transistor writes through a write bitline when the write wordline is high, and a second transistor reads the stored charge onto a single-ended read bitline, so read and write are separate ports and no cross-coupled inverter pair is needed. The carrying architecture is OpenGCRAM's script-based compiler flow, in which user configuration drives automatic generation of the bitcell array, address and data peripherals, control logic, SPICE netlists, GDS layouts, and HSPICE measurement setups. For the OS-OS variant the load-bearing additions are a compact Verilog-A model of an ultra-low-leakage ITO transistor, calibrated against TCAD and one experimental device, and back-end-of-line layer definitions and design rules that let the two transistors be placed between tight-pitched metal layers on top of the silicon circuits.

What would settle it

Fabricate an OS-OS GCRAM bank from an OpenGCRAM-generated TSMC 40 nm layout and compare measured retention and leakage with the compiler's HSPICE predictions; if the ITO write transistor's off-state leakage is far above $10^{-18}$ A/µm or stored data does not persist for milliseconds at the specified operating voltage, the OS-OS claims are contradicted.

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Extended reading notes

Core claim

On its own terms, the paper establishes that SRAM-style compiler automation can be extended to gain-cell memories. OpenGCRAM generates a GCRAM bank from user parameters: a bitcell array of two-transistor cells with separate write and read wordlines and bitlines, dual-port address and data peripherals, an added reference generator for single-ended readout, and predischarge or precharge logic depending on the cell variant. The generated TSMC 40 nm banks pass DRC and LVS for capacities from 256 bits to 16 Kb, and the compiler automatically writes HSPICE stimuli to report operating frequency, effective bandwidth, leakage, and retention. The paper reports that a 2T Si-Si GCRAM bitcell is 31 percent smaller than a 6T SRAM cell, that an OS-OS GCRAM bitcell is 89 percent smaller, that the Si-Si GCRAM bank area is larger than SRAM at small capacities and becomes smaller only above roughly 256 Kb because of dual-port peripherals, and that OS-OS banks are smaller at all tested sizes. It also reports microsecond retention for Si-Si GCRAM, millisecond retention for OS-OS GCRAM with an ITO write transistor, and tunability beyond 10 seconds through threshold-voltage and material choices. Using an application-guided workload profiler, it constructs Shmoo plots, pass/fail maps over bank configuration and workload, showing which GCRAM bank sizes meet read-frequency and lifetime demands for L1 and L2 caches across seven AI workloads.

Load-bearing premise

The load-bearing premise is that the compact oxide-semiconductor transistor model, fitted to TCAD calibrated from a single measured ITO device, accurately predicts retention and leakage for the back-end-of-line transistors in a real TSMC 40 nm layout.

Editorial extensions

If this is right

  • A chip team can go from a GCRAM configuration to a TSMC 40 nm layout that passes foundry design checks and to HSPICE area, delay, and power numbers without hand-laying-out analog blocks, greatly reducing memory design time.
  • Because gain-cell read and write use separate ports, a generated GCRAM bank gives dual-port bandwidth, and bitcell leakage is nearly zero since there is no direct VDD-to-ground path, so on-chip memory power can fall well below SRAM.
  • Retention can be matched to workload data lifetime, with microseconds for activation caches and seconds or longer for weight storage, by choosing threshold voltage, channel material, and whether a write-wordline level shifter is included.
  • The porting methodology is not tied to one cell or process; the paper argues it extends to more advanced nodes and to other single-bitline memories such as 1T1C DRAM and RRAM, so the compiler could become a general memory-generation platform.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural next step, not reported in this paper, is silicon measurement of an OpenGCRAM-generated bank; the compiler's OS-OS claims are currently backed by simulation through a TCAD-calibrated model rather than by a fabricated memory.
  • The paper's main area comparison is dual-port GCRAM against single-port SRAM. Because a dual-port SRAM bank is roughly twice the area of a single-port one, a like-for-like comparison would make the GCRAM area crossover appear at smaller capacities.
  • The Shmoo exploration assumes one bank per cache level. Extending the compiler to multibank GCRAM, listed as future work, may be the right response to the paper's finding that shared L2 caches demand much higher read frequency than per-core L1 caches.
  • If the OS compact model is confirmed in silicon, OS-OS GCRAM's 11 percent-of-SRAM bitcell, placed in the back-end metal stack, would effectively add memory capacity on top of logic and change how much on-chip memory an accelerator can afford.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents OpenGCRAM, an open-source memory compiler that extends the OpenRAM framework to generate gain-cell (GCRAM) memories. For a user-specified bank size, word width, and peripheral options, the compiler is claimed to produce SPICE netlists, GDS layouts, DRC/LVS-clean layout views, and HSPICE-based area/delay/power characterizations in TSMC 40nm. The authors describe a methodology for porting OpenRAM to new PDKs and memory types, then apply it to 2T Si-Si and 2T OS-OS GCRAM. Results include bitcell and bank area comparisons against SRAM, frequency/bandwidth/leakage simulations for Si-Si GCRAM, retention simulations for both variants, and a design-space exploration for AI cache workloads using the GainSight profiler.

Significance. If the central claims hold, OpenGCRAM would fill a real gap: researchers currently lack an open, automated, layout-generating GCRAM compiler, and the porting methodology could be reused for other PDKs and memory technologies. The paper gives explicit credit for its open-source release, its modular extension of OpenRAM, and its automatic HSPICE stimulus generation and simulation flow for Si-Si GCRAM. The design-space exploration for AI workloads is also a useful demonstration. However, the strongest OS-OS claims and the large-capacity area-crossover conclusion rest on projections and extrapolations rather than on validated compiler outputs, so the significance is conditional on the additional evidence requested below.

major comments (4)
  1. [V-A] The central claim that OpenGCRAM generates DRC/LVS-clean, tapeout-ready GCRAM layouts for TSMC 40nm is not supported by the evidence presented: Section V-A states that "we resolved all DRC and LVS errors" for bank sizes from 256 bits to 16Kb, but no DRC or LVS reports, error summaries, or rule-deck versions are shown, and no commit hash or artifact identifier is provided for the released code. Since this claim is load-bearing for the paper's main contribution, the authors should supply the actual check reports (or a reproducible script that regenerates them) and a pinned repository version; without these, a reader cannot verify that the layouts are clean or reproduce the result.
  2. [V-D, VI] The OS-OS GCRAM results—ultra-low leakage (<1e-18 A/µm), 89% area reduction, millisecond retention, and the Shmoo design space in Fig. 10—rest on a Verilog-A compact model that was fitted to TCAD results, and the TCAD was calibrated using a single experimental ultra-low-leakage ITO transistor (Section V-D). No evidence is given that this device is representative of the BEOL OS transistors assumed in the TSMC 40nm layout, and Section VI states that HSPICE simulation of OS-OS banks is future work, so operating frequency, bandwidth, and power for OS-OS are not evaluated by the compiler. These OS-OS conclusions should be presented as model-based projections with a clear statement of the underlying assumptions, and ideally validated against an OS device fabricated in the target BEOL or against foundry-supported OS device models.
  3. [V-B, Fig. 6(c)] The claim that Si-Si GCRAM bank area becomes smaller than SRAM for bank sizes beyond 256 Kb is based on polynomial trendlines extrapolated from only three simulated bank sizes (1, 4, and 16 Kb) in Fig. 6(c). Polynomial extrapolation over two orders of magnitude is not justified without error bounds, goodness-of-fit measures, or generated layouts at larger capacities, and the plotted comparison is against single-port SRAM even though the GCRAM banks are dual-port; the authors note that a fair dual-port SRAM comparison would roughly double the SRAM area, but this is not reflected in the figure. The crossover claim should be reworded as a projection or supported by actual compiler runs at larger bank sizes.
  4. [V-E, Fig. 10] The Shmoo plots in Fig. 10 claim to show whether a GCRAM bank can work for each L1/L2 cache task, but the text does not define the success criterion (e.g., frequency margin, retention versus required data lifetime, write/read timing, or noise margin). Without a precise definition of what makes a configuration "work," the design-space exploration results are difficult to interpret or reproduce. The authors should state the pass/fail metric and the simulation conditions used to generate the Shmoo plots.
minor comments (5)
  1. [I, VI] There are several typos that should be corrected, including "ABSRTACT" in Section I and "bandiwdth" in Section VI.
  2. [V-D, Fig. 8] The caption for Fig. 8 labels two subfigures as "(d)"; the second one should be "(e)", and the text should be checked for corresponding cross-references.
  3. [References] References [6] and [27] are duplicate entries for the same paper; please consolidate and renumber.
  4. [Footnote 1] The footnote states that the TSMC 40nm tech script and proprietary custom cells are protected by NDA; for reproducibility, please provide a manifest of which parts of the repository are included versus NDA-protected, and add a commit hash to the arXiv version.
  5. [Fig. 7] The green data points used in Fig. 7(a) may be hard to distinguish in black-and-white print; consider using distinct marker shapes or gray shading.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: OpenGCRAM's compiler flow is validated against DRC/LVS and OpenRAM-style generation, and the OS-OS retention claim is a model-based simulation rather than a self-referential prediction.

full rationale

The paper's central contribution is an open-source compiler that extends OpenRAM to GCRAM with TSMC 40nm DRC/LVS-clean layout generation and HSPICE simulation for Si-Si GCRAM. The derivation chain for area, frequency, bandwidth, and leakage comparisons is based on generated netlists, automatically produced layouts, and standard DRC/LVS checks, not on a self-defined target. The OS-OS retention results (Section V-D) are explicitly presented as simulations using a Verilog-A compact model 'calibrated ... to fit the TCAD results,' with TCAD calibrated against an experimental ITO transistor; this is a conventional model-fitting flow in which the fitted target is the device I-V behavior, while retention is a downstream circuit-level simulation, so the retention number is not equivalent to the fit input by construction. The GainSight profiler [26] is a same-author tool used to supply workload cache requirements; it is an external input to the design-space exploration and does not define the compiler's correctness. The paper's own Future Work section concedes that OS-OS HSPICE frequency/bandwidth/power simulation is not yet implemented, which is a completeness limitation rather than a circularity. No load-bearing argument reduces to a self-citation or to a parameter renamed as a prediction.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the reliability of the TSMC 40nm PDK models, the calibrated OS transistor model, and the DRC/LVS flow. The free parameters are confined to the OS model fit and the area extrapolation curve; the compiler itself does not introduce invented physical entities.

free parameters (2)
  • OS transistor compact model parameters = not reported (fit to TCAD results)
    Section V-D: 'developed and calibrated a SPICE-compatible verilog-A model to fit the TCAD results.' The OS-OS GCRAM retention time and design-space conclusions depend on this fitted model.
  • Polynomial trendline coefficients for area extrapolation = not reported (fit to 1-16 Kb data)
    Section V-B and Fig. 6(c): 'Polynomial trend lines for the three curves are added and extrapolated to 64 Kb and 256 Kb.' The claim that GCRAM bank area becomes smaller than SRAM beyond 256 Kb rests on this extrapolation.
assumptions (5)
  • domain assumption OpenRAM's memory compiler architecture can be generalized to single-ended GCRAM with separate read/write ports without loss of correctness.
    Section IV-B describes modifications to bitcell array and peripherals; the resulting DRC/LVS-clean layouts are taken as evidence, but the compiler's correctness for arbitrary configurations is not proven.
  • domain assumption HSPICE simulations using TSMC 40nm PDK models accurately predict the frequency, power, and retention of generated GCRAM banks.
    Sections V-C and V-D report simulation results as performance ground truth; no silicon measurement of the generated banks is provided.
  • ad hoc to paper The Verilog-A compact model for the ITO OS transistor, calibrated to TCAD of an experimental transistor, is representative of the BEOL OS devices in the generated OS-OS GCRAM layout.
    Section V-D: model is fit to TCAD calibrated to an ultra-low leakage ITO transistor. The OS-OS retention claims depend on this model.
  • domain assumption Passing DRC and LVS is sufficient to call a layout tapeout-ready.
    The paper claims 'The generated GDS files are ready for tape out with TSMC' based on DRC/LVS clean, but no sign-off, DFM, or silicon validation is shown.
  • domain assumption GainSight profiling on NVIDIA H100 scaled to GT 520M accurately captures L1/L2 cache read frequency and lifetime demands of the listed AI workloads.
    Section V-E uses GainSight outputs to derive Shmoo plots; the scaling methodology is not described in this paper and is cited as prior work [26].

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Cite this review

Pith. "Pith review of OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads." pith.science (2026). https://pith.science/paper/3SKSP753

@misc{pith2026250710849,
  author       = {Pith},
  title        = {Pith review of: OpenGCRAM: An Open-Source Gain Cell Compiler Enabling Design-Space Exploration for AI Workloads},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3SKSP753}},
  note         = {Machine review of arXiv:2507.10849}
}
read the original abstract

Gain Cell memory (GCRAM) offers higher density and lower power than SRAM, making it a promising candidate for on-chip memory in domain-specific accelerators. To support workloads with varying traffic and lifetime metrics, GCRAM also offers high bandwidth, ultra low leakage power and a wide range of retention times, which can be adjusted through transistor design (like threshold voltage and channel material) and on-the-fly by changing the operating voltage. However, designing and optimizing GCRAM sub-systems can be time-consuming. In this paper, we present OpenGCRAM, an open-source GCRAM compiler capable of generating GCRAM bank circuit designs and DRC- and LVS-clean layouts for commercially available foundry CMOS, while also providing area, delay, and power simulations based on user-specified configurations (e.g., word size and number of words). OpenGCRAM enables fast, accurate, customizable, and optimized GCRAM block generation, reduces design time, ensure process compliance, and delivers performance-tailored memory blocks that meet diverse application requirements.

Figures

Figures reproduced from arXiv: 2507.10849 by the authors.

Figure 1
Figure 1. Flow chart of (a) porting the compiler to new technology nodes and [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. The layouts of (a) 2T Si-Si GCRAM, (b) 2T OS-OS GCRAM and [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 2
Figure 2. The schematics of (a) 2T Si-Si GCRAM, (b) 2T OS-OS GCRAM [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: The Architecture of a GCRAM bank. The OpenGCRAM compiler [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: The layout of a 32x32 GCRAM bank generated by OpenGCRAM. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: (a) Operating frequency, (b) effective bandwidth and (c) leakage power [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: (a) The Id − Vg properties of Si transistors. (b) Data written to Si-Si GCRAM can be retained for microseconds. (c) The retention of Si-Si GCRAM can be enhanced by adjusting the VT of the write transistor and adding a WWL level shifter. (d) The Id − Vg properties of OS…
Figure 9
Figure 9. Figure 9: The demands on L1 and L2 caches in terms of (a) read frequency [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: Design choices for implementing (a) L1 and (b) L2 caches with [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Reducing Power Consumption of Embedded Dynamic Memories with ECCs

    cs.IT 2026-07 conditional novelty 5.0 of 10

    For retention-limited GCRAM, the minimum-power ECC is workload-dependent — strong BCH codes win when refresh dominates, light codes win under heavy access — giving modeled total-power reductions of 46.8-94.8%.

Reference graph

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.