Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators

Convolution remains the most compute-intensive operation in AI acceleration, often constituting over 80-90% of the workload. Existing approaches in spatial architectures such as coarse-grained reconfigurable arrays (CGRAs) and field-programmable gate arrays (FPGAs) frequently rely on loop unrolling or GEMM-based matrix transformations, introducing significant overhead in both data movement and instruction control. This paper presents a new framework designed to systematically demystify the 7-dimensional convolution loop nest by reinterpreting it as a hardware-centric data and instruction streaming problem. Instead of treating the loop nest as a fixed computational construct, our approach exposes its structure as a set of spatial and temporal mappings governed by hardware parameters such as compute element distribution, interconnect topology, and reconfigurability. This abstraction supports lightweight, flexible deployment of convolution without reliance on heavyweight transformations or reordering schemes. We demonstrate the application of our approach on the MAVeC accelerator. We detail the implementation of convolution operations in MAVeC and extend the framework to support full model execution on VGG-16. Our profiling reveals high PE utilization (over 90%), significant fold reuse, and scalable throughput up to 1.56 TFLOPs/sec and 12.7 KIPS for end-to-end VGG-16 inference. These results validate the efficacy of our approach in minimizing control overhead, improving data locality, and enabling efficient large-scale convolution execution without reliance on conventional transformation-based methods.