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REVIEW 4 major objections 6 minor 49 references

In-Memory Non-Binary LDPC Decoding

T0 review · 4 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims the first hardware processing-in-memory implementations of non-binary LDPC decoders—FFT-based sum-product and min-max—running on UPMEM and reaching 76 Mbit/s, competitive with low-power edge GPUs.

desk verdict First PiM NB-LDPC hardware mapping is real; 'competitive with edge GPUs' is unproven because no BER/FER is reported and the GPU baseline is not matched. read the letter →

arxiv 2508.03567 v1 pith:6DWJUQ7M submitted 2025-08-05 cs.DC cs.CE

Oscar Ferraz , Vitor Silva , Gabriel Falcao This is my paper · ORCID
classification cs.DCcs.CE
keywords Processing-in-memoryUPMEMNon-binaryLDPCFFT-SPAMin-MaxdecodingMulticodewordFixed-pointquantizationEmbeddedGPU
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Non-binary LDPC decoding is a computationally heavy error-correction workload that usually runs on parallel processors, moving large amounts of data between memory and compute units. This paper claims the first hardware processing-in-memory (PiM) implementations of two NB-LDPC decoders—the FFT-based sum-product algorithm and the min-max algorithm—running on the UPMEM system, where simple RISC cores sit inside DRAM. The implementations decode short codes of 16 to 64 symbols over fields GF(4) through GF(256), decode many codewords concurrently on 2540 in-memory cores, and use quantized fixed-point arithmetic to avoid floating-point emulation. The headline measured result is 76 Mbit/s for the FFT-SPA decoder in 32-bit integer mode, which the authors report as competitive with low-power embedded GPUs from the Jetson family. What the paper is establishing is that processing-in-memory is a workable platform for batch NB-LDPC decoding, not just a theoretical proposal.

What carries the argument

The central mechanism is the UPMEM DRAM Processing Unit (DPU): a 32-bit in-order RISC core embedded beside a 64 MB DRAM bank, with a 14-stage pipeline, up to 24 hardware threads, a 64 KB SRAM scratchpad (WRAM), an 8-bit native multiplier, and no floating-point unit. The argument is carried by a specific mapping strategy: Tanner graph topology and frequently accessed messages stay in WRAM, larger auxiliary buffers spill to MRAM, Galois-field multiplications become look-up table reads and barrel shifts, the FFT-SPA uses a radix-2 FFT with edge-level parallelism and stage barriers, and the Min-Max decoder computes its forward, backward, and beta matrices with comparison passes. With 2540 DPUs each decoding an independent codeword, the design hides per-core latency through massive multicodeword parallelism and converts the data-movement bottleneck into computation performed next to the data.

What would settle it

Run the implemented C1, C2, and C3 decoders over an AWGN channel with BPSK modulation at several signal-to-noise ratios, using the exact 8-bit quantized FFT-SPA and Min-Max kernels, and compare their bit-error and frame-error rates against a floating-point reference at the same iteration count. If the quantized versions show more than about 0.1 dB degradation or any error floor in the simulated range, the competitive throughput claim would be describing a computing engine rather than a usable error-correcting decoder.

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Extended reading notes

Core claim

The central claim is that the UPMEM processing-in-memory system, despite its low clock rate and simple ALUs, can execute non-binary LDPC decoding at throughputs comparable to low-power GPUs. The authors design an FFT-SPA decoder (floating-point, 32-bit integer, and 8-bit variants) and a Min-Max decoder (32-bit and 8-bit fixed-point), using a multicodeword mapping in which each DRAM Processing Unit decodes its own codeword, eliminating inter-DPU synchronization. The mapping keeps the Tanner graph and hot buffers in WRAM, offloads less-used buffers to MRAM, performs Galois-field multiplication as look-up table reads and barrel-shift permutations, and parallelizes the radix-2 FFT and forward/backward matrix passes over edges with barrier synchronization. On codes of sizes (16,8), (32,16), and (64,32), the multi-DPU FFT-SPA reaches 76.7 Mbit/s in 32-bit integer mode and the Min-Max reaches 145.2 Mbit/s at GF(8). In the GF(16) FFT-SPA comparison, the published results place the UPMEM system between the Jetson TX2 and the Jetson Xavier, and the authors argue the performance difference is set mainly by the number of cores rather than per-core capability.

Load-bearing premise

The load-bearing premise is that the implemented decoders actually correct errors at usable quality: the paper never reports bit-error or frame-error rates, instead citing a published quantization study to argue that 8-bit fixed-point arithmetic costs less than roughly 0.1 dB, so the throughput figures describe a compute engine whose error-correction performance still needs to be demonstrated.

Editorial extensions

If this is right

  • Processing-in-memory hardware, not just simulated models, can run complete FFT-SPA and Min-Max NB-LDPC decoders, opening a concrete low-power path for error-correction workloads in memory-centric systems.
  • For short CCSDS-family codes at GF(16), the UPMEM system's throughput sits between a Jetson TX2 and a Jetson Xavier, indicating near-memory decoding can compete with low-power GPUs when the data-movement bottleneck is dominant.
  • Fixed-point quantization to 32-bit and 8-bit integers keeps the decoders inside a practical performance band without floating-point units, based on the cited quantization study.
  • The one-codeword-per-DPU multicodeword strategy removes inter-DPU synchronization, and throughput scales with the number of DPUs, so adding PiM modules increases decoding capacity without redesign.
  • The reported figures are compute-only at a fixed number of iterations, deliberately excluding parity-check verification and early stopping, so they provide an SNR-independent throughput baseline.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the paper never reports bit-error or frame-error rates, the natural test of its central claim is to connect the same kernels to an AWGN channel simulator and measure actual decoding quality; until then, the throughput figures describe the compute engine, not a verified error-correcting decoder.
  • The 8-bit FFT-SPA variant (20.7 Mbit/s) is slower than the 32-bit variant (76.7 Mbit/s), which suggests the limiting resource on short kernels is instruction issue and pipeline utilization rather than arithmetic width; a testable extension would pack two 8-bit symbols per 32-bit word and remeasure.
  • The paper's 'add more modules' scalability is a linear-scaling hypothesis; a direct check is to measure throughput on one, two, and four UPMEM modules at a fixed code and field and compare the scaling exponent, rather than inferring from the modular architecture.
  • Reading the paper's batch-decoding conclusion (massive MIMO, optical receivers, cloud-RAN), the result is aimed at high-density parallel decoding of many codewords; in single-stream low-latency links, the host-to-DPU transfer and setup latency would dominate, so this is not a general replacement for GPU decoding.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. This manuscript reports implementations of non-binary LDPC decoders, specifically FFT-SPA and Min-Max, on UPMEM processing-in-memory hardware. It describes the mapping to the UPMEM memory hierarchy (WRAM/MRAM), multithreading with 16 threads per DPU, and multicodeword execution across 2540 DPUs, and reports operation counts, execution times, and throughput for three short CCSDS-derived codes over GF(4) through GF(256). The central claim is that the UPMEM implementation is the first PiM-based NB-LDPC decoder and that its maximum 76 Mbit/s throughput is competitive with low-power edge GPUs.

Significance. If properly validated, this would be a useful first demonstration of NB-LDPC decoding on commercial PiM hardware, providing concrete data on WRAM/MRAM placement, 8-bit quantization, loop unrolling, and multicodeword throughput. The complexity validation in Sec. 5.1 (Fig. 5) is valuable because it ties counted UPMEM operations to theoretical expressions without fitted constants. The main limiting factor is that the throughput claims are not yet attached to verified error-correction performance or a matched GPU operating point, so the significance of the headline comparison is currently conditional.

major comments (4)
  1. [Sec. 5.2 (Figs. 6–8); Sec. 4.1] No BER/FER validation is reported anywhere in the manuscript; Section 5.2 measures only execution time and throughput. Section 4.1 justifies 8-bit quantization by citing reference [47], but that reference addresses log-sum-product decoding and does not validate the probability-domain FFT-SPA or Min-Max kernels for the code lengths and field sizes used here. Because the decoders exclude parity-check verification from timing and no syndrome or error-rate result is given, the 76 Mbit/s figure is not tied to a demonstrated error-correcting decoder. Please add BER/FER curves versus SNR for each algorithm, quantization mode, and code, with a floating-point reference, and report syndrome-validated operation.
  2. [Sec. 5.4, Fig. 10] The comparison to edge GPUs is not shown to be at a common operating point. The manuscript does not report the maximum iteration count Imax used in the UPMEM runs or in the GPU results taken from [13], nor whether the GPU numbers include parity-check overhead or use the same early-termination policy. Since both sets of numbers come from the authors' own implementations, reporting matched conditions is feasible. Without a stated iteration cap and matched protocol, the claim that UPMEM is 'competitive with edge GPUs' is not established. Please specify Imax, quantization, and early-termination status for both platforms, and report throughput at matched error-correction performance or at equal iteration counts.
  3. [Sec. 5.2, Fig. 7] The abstract's headline 76 Mbit/s is the 32-bit integer FFT-SPA maximum from Fig. 7, whereas the 8-bit FFT-SPA reaches 20.729 Mbit/s. This is important because the quantization discussion in Sec. 4.1 motivates the 8-bit decoder, and the conclusion describes 'message quantization' as a key balance. The headline should either refer to the validated/deployed configuration or be qualified as the 32-bit integer implementation.
  4. [Sec. 5; Algorithms 1 and 2] The maximum iteration count Imax is never disclosed, despite being an input to Algorithms 1 and 2 and determining throughput when early termination is disabled and parity-check processing is excluded from the timing. Please report Imax for all experiments and, ideally, report throughput per iteration so that the numbers can be compared across platforms and reproduced.
minor comments (6)
  1. [Fig. 3 caption] The caption contains the typo 'strucutre'; it should read 'structure'.
  2. [Sec. 4.1 and Fig. 7] The manuscript alternates between '32-bit fixed-point' and '32-bit integer' for the same implementation; please use one consistent term.
  3. [Sec. 5.2] The sentence 'The performance decreases from 2.5× to 1.5× for every GF increment' is ambiguous; please state explicitly whether this is a multiplicative slowdown and over which GF range it applies.
  4. [Sec. 5.4] The comparison uses 2540 DPUs for UPMEM but 16,384 or 32,768 decoders for the GPUs; reporting a per-decoder throughput or a power-normalized metric would clarify whether the comparison reflects the architecture or simply the number of parallel workers.
  5. [Sec. 5.1, Fig. 5] The method used to obtain the counted 'UPMEM Ops' and 'UPMEM Mem.' values is not described; please state briefly how the counts were instrumented.
  6. [General] No code or PCM definitions are provided; including the parity-check matrices or a public source for them would improve reproducibility.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the throughput and complexity results are independent measurements and counts; the only self-referential element is the GPU baseline from the authors' prior work, which weakens benchmark independence but does not make the derivation circular.

full rationale

This is an empirical implementation paper rather than a mathematical derivation, so the circularity test is whether any claimed result reduces by construction to an input or to a self-citation. The decoding equations in Sec. 2.2 (Algorithms 1 and 2) are standard textbook FFT-SPA and Min-Max updates, and the complexity expressions in Sec. 2.3 are direct operation/memory-transaction counts read off Table 1; neither is fitted to the measured numbers. The headline throughput is computed in Sec. 5.2 as TP = N·q/t from raw DPU cycle counts (perfcounter_config), with no fitted constant and no dependence on any target result, so the 76 Mbit/s figure does not reduce to an input. The quantization-loss justification in Sec. 4.1 relies on an external reference [47] rather than measured BER/FER, and Sec. 5 reports only execution times with no syndrome or BER/FER validation; this is a missing-validation and correctness-risk issue, not circularity. The one self-referential element is Fig. 10, where the low-power GPU throughput values are quoted from the authors' own prior work [13]. Since the UPMEM measurements are taken independently and are not derived from those GPU values, the self-citation is a benchmark-independence caveat rather than a load-bearing circular step. Accordingly, no circular step meeting the quote-and-reduction bar is present.

Assumptions & free parameters 3 free parameters · 5 assumptions · 0 invented entities

The central claim rests on standard decoding algorithms, an assumed CCSDS code family, a quantization-loss result taken from the literature, and the choice to compare compute-only throughput. No new entities are introduced and no constants are fit to data, but the undisclosed maximum iteration count is a de facto free parameter that controls the reported throughput.

free parameters (3)
  • Maximum decoding iterations (Imax) = unspecified
    Throughput T = N*q/t directly depends on the number of decoding iterations executed. The paper fixes iterations to ensure a fair comparison but never states Imax, so throughput values cannot be reproduced or compared on an equal basis.
  • Quantization bit width = 8-bit and 32-bit fixed-point
    Selected by hand in Sec. 4.1 to trade arithmetic cost for error-correction capability; the BER impact is borrowed from the literature rather than measured for these decoders.
  • Thread count per DPU = 16
    Chosen as the first power of two above 11 to fill the UPMEM pipeline (Sec. 4); synchronization count and throughput depend on this choice.
assumptions (5)
  • domain assumption FFT-SPA and Min-Max are valid NB-LDPC decoding algorithms
    Algorithms 1 and 2 are taken from Davey-MacKay and Savin; the paper provides no independent error-rate verification of its implementations.
  • domain assumption CCSDS-derived matrices for C1, C2, C3 exist for GF(2^2)..GF(2^8) with dc=4, dv=2
    Sec. 5 states the code construction from [1], but the PCMs and the subfield derivation are not shown.
  • standard math Radix-2 FFT computes the CNP product correctly after Fourier transform
    The FFT block in Sec. 4.2 relies on the standard convolution theorem; this is standard mathematics.
  • domain assumption 8-bit fixed-point quantization degrades BER by less than 0.1 dB on these codes
    Sec. 4.1 cites Wymeersch et al. [47] for LSPA decoders; no BER measurement is performed here to confirm the transfer.
  • ad hoc to paper Compute-only throughput is the right comparison metric against [13]
    Sec. 5 excludes data transfer and parity-check/hard-decision processing to fix iteration count, but the GPU baseline is not shown to use the same protocol, making this choice assumption-specific.

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Cite this review

Pith. "Pith review of In-Memory Non-Binary LDPC Decoding." pith.science (2026). https://pith.science/paper/6DWJUQ7M

@misc{pith2026250803567,
  author       = {Pith},
  title        = {Pith review of: In-Memory Non-Binary LDPC Decoding},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6DWJUQ7M}},
  note         = {Machine review of arXiv:2508.03567}
}
read the original abstract

Low-density parity-check (LDPC) codes are an important feature of several communication and storage applications, offering a flexible and effective method for error correction. These codes are computationally complex and require the exploitation of parallel processing to meet real-time constraints. As advancements in arithmetic and logic unit technology allowed for higher performance of computing systems, memory technology has not kept the same pace of development, creating a data movement bottleneck and affecting parallel processing systems more dramatically. To alleviate the severity of this bottleneck, several solutions have been proposed, namely the processing in-memory (PiM) paradigm that involves the design of compute units to where (or near) the data is stored, utilizing thousands of low-complexity processing units to perform out bit-wise and simple arithmetic operations. This paper presents a novel efficient solution for near-memory non-binary LDPC decoders in the UPMEM system, for the best of our knowledge the first real hardware PiM-based non-binary LDPC decoder that is benchmarked against low-power GPU parallel solutions highly optimized for throughput performance. PiM-based non-binary LDPC decoders can achieve 76 Mbit/s of decoding throughput, which is even competitive when compared against implementations running in edge GPUs.

Figures

Figures reproduced from arXiv: 2508.03567 by the authors.

Figure 1
Figure 1. A bipartite graph depicting relationships betwee [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. The NB-LDPC Tanner graph representation of matrix [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. UPMEM system strucutre. a) PiM chip is composed of eight DPUs and respective DRAM banks. Each PiM dual in-line memory module comprises 16 PiM chips. b) includes UPMEM PiM module 16 PiM chips, eight at the front and eight at the back. Each PiM chip is composed of eight DPUs. c) UPMEM PiM server contains two CPUs, 20 PiM modules, and four conventional DRAM modules. Courtesy of [42] The hardware threads use a shared in… view at source ↗
Figures from the paper (8 more)
Figure 4
Figure 4. Figure 4: Architecture of a UPMEM PiM chip for LDPC decoding. [PITH_FULL_IMAGE:figures/full_fig_p010_4.png]
Figure 4
Figure 4. Figure 4: An MRAM/WRAM read and write takes between [PITH_FULL_IMAGE:figures/full_fig_p012_4.png]
Figure 5
Figure 5. Figure 5: Number of operations and memory transactions to pe [PITH_FULL_IMAGE:figures/full_fig_p014_5.png]
Figure 6
Figure 6. Figure 6: Execution time of NB-LDPC decoding algorithms in a [PITH_FULL_IMAGE:figures/full_fig_p015_6.png]
Figure 7
Figure 7. Figure 7: Throughput performance for the multi-DPU multith [PITH_FULL_IMAGE:figures/full_fig_p016_7.png]
Figure 8
Figure 8. Figure 8: Throughput performance for the multi-DPU multith [PITH_FULL_IMAGE:figures/full_fig_p016_8.png]
Figure 9
Figure 9. Figure 9: Codeword data transaction time between host and de [PITH_FULL_IMAGE:figures/full_fig_p018_9.png]
Figure 10
Figure 10. Figure 10: Maximum throughput performance comparison betw [PITH_FULL_IMAGE:figures/full_fig_p019_10.png]

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