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REVIEW 3 major objections 5 minor 25 references

Real-Time Piano Note Frequency Detection Using FPGA and FFT Core

T0 review · 3 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read This paper reports that a Spartan-3E FPGA, using a 512-point fixed-point FFT core in burst mode, samples analog piano audio, finds the dominant frequency bin, and displays the frequency on an LCD, with each key press producing a distinct bi

desk verdict A student project report on a standard FPGA FFT pitch detector with a fixable factor-of-two error in the resolution and an uncalibrated sample rate; workable as a teaching demo, not a research contribution. read the letter →

arxiv 2509.00589 v1 pith:B5AHCKHH submitted 2025-08-30 cs.AR cs.SDeess.AS

Shafayet M. Anik , D.G. Perera This is my paper · ORCID
classification cs.ARcs.SDeess.AS
keywords FPGAFFTpianonotedetectionfrequencyestimationSpartan-3EADCsamplingreal-timesignalprocessingLCDdisplay
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This project report describes a hardware-only FPGA system that identifies the fundamental frequency of a single piano note in real time. The authors built a pipeline on a Spartan-3E board: an onboard ADC captures the analog audio, custom Verilog logic stores 512 downsampled samples, a fixed-point FFT core converts them to the frequency domain, a peak detector finds the strongest bin, and an LCD shows the corresponding hertz value. Their central claim is that this resource-constrained design works: each key press translated into a distinct frequency bin output, with example detections around 293.68 Hz and 130.68 Hz. They also claim the configuration achieves about 8.36 Hz per bin at an effective sampling rate of roughly 4.28 kHz, enough to separate common musical notes while leaving close notes and harmonics unresolved. The significance, as the authors frame it, is that real-time frequency-domain analysis is feasible on small FPGAs without software DSP.

What carries the argument

The central mechanism is the sampling-rate chain feeding a 512-point FFT. A 5 MHz system clock is divided by a 73-clock spacing between ADC reads and a further 16:1 downsample, giving an effective sampling rate F_s ≈ 4.28 kHz; the FFT then yields bins spaced by Δf ≈ 8.36 Hz. The transform itself is a Radix-4 Burst I/O FFT core—it loads all 512 time samples in one burst, computes internally, then unloads bins in natural order—with 14-bit fixed-point inputs. A peak detector squares the real and imaginary parts of each output bin, keeps the largest magnitude and its index, and scales that index to a frequency in hertz for the character LCD. A finite state machine synchronizes the ADC, the FFT c

What would settle it

Feed a calibrated sine wave of known frequency, say 440.0 Hz, into the same DC-biased audio input while the system runs, and simultaneously capture the ADC sample clock with a logic analyzer or oscilloscope. If the LCD shows a frequency more than one bin width (about 8.36 Hz) away from 440 Hz, or the measured sample period is not exactly 73 × 16 / 5 MHz, then the nominal sampling-rate assumption is the failure point. Repeating this at 130.68 Hz and 293.68 Hz would test whether the displayed values reproduce the examples in the report.

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Extended reading notes

Core claim

On the paper's own terms, the discovery is that a working real-time piano-note frequency detector can be assembled from standard FPGA blocks: a custom SPI master driving the board's ADC, a vendor FFT core configured for a 512-point Radix-4 Burst I/O transform, a peak-magnitude tracker that compares squared real and imaginary outputs, and a finite state machine that coordinates sampling, FFT feeding, and an LCD update. The report states that every key press produced a distinct frequency bin, confirming the sampling and FFT pipeline. Two captured waveforms show the detected fundamentals at approximately 293.68 Hz and 130.68 Hz. The design deliberately trades transform size and throughput for r

Load-bearing premise

The whole frequency readout assumes the ADC really samples at F_s = 5 MHz / (73 × 16) ≈ 4.28 kHz from the nominal 5 MHz board clock; the report never measures the actual sample timing, so a deviation there would bias every displayed frequency.

Editorial extensions

If this is right

  • A single audio source can be reduced to its dominant frequency using only a small FPGA's logic and block RAM, with no software processor or operating system in the signal path.
  • With the 512-point/4.28 kHz configuration, notes whose fundamentals are separated by more than about 8.36 Hz can be told apart; the report says this distinguishes common piano notes but leaves closely spaced or harmonic-rich cases unresolved.
  • Raising the transform to 1024 points, or switching to Pipelined Streaming mode, fails on this board, so real-time operation on this class of FPGA depends on burst-mode FFT and deliberate downsampling.
  • The detected frequency is a linear function of the assumed sampling rate, so any error in the nominal 5 MHz clock or the delay counts shifts every displayed frequency by the same proportion.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper never verifies the sample clock, so a calibrated-tone test against a measured sample period would tell whether the displayed frequencies are accurate in absolute terms; this is an inference beyond the reported results.
  • Because the bin spacing is 8.36 Hz, adjacent low-piano notes (e.g., C2 to C#2, about 3.9 Hz apart) would fall in the same or neighboring bins, suggesting low-note accuracy needs interpolation even though the mid-range detections in the report are distinct.
  • The pipeline should apply to any periodic sound source with a fundamental below the 2.14 kHz Nyquist limit, not just pianos, since the piano only provides the test tones.
  • Burst-mode FFT means the system takes snapshots rather than streaming continuously; the report's 'real-time' claim is about a complete sample-FFT-display cycle, not sample-by-sample throughput.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The manuscript reports an FPGA-based single-note frequency detector built on a Spartan-3E starter kit. Analog piano audio is captured through the board's LTC1407A ADC, downsampled to a nominal effective rate of 4.28 kHz, stored as 512 samples, processed by a Xilinx FFT IP core in Radix-4 Burst I/O mode, and reduced to a peak magnitude bin. The bin index is converted to a frequency in hertz and displayed on a character LCD. The paper describes the module-level design, the FFT core interface, resource-driven choices (1024-point and streaming FFT configurations were abandoned), and ChipScope debugging. The authors conclude that the system meets the core functional requirements of sampling, FFT processing, and dominant-frequency display, with oscilloscope waveforms as evidence.

Significance. If the frequency-detection claim were quantitatively validated, this would be a modest but useful educational demonstration of FPGA-based FFT signal processing on a resource-constrained board. The paper has several genuine strengths: the DFT/FFT mathematics in Section 3 are correct, the description of the Xilinx FFT core handshaking is careful and consistent with the product behavior, and the resource-driven decision to move from 1024-point/streaming implementations to a 512-point burst configuration is clearly documented. The use of ChipScope waveforms and the explicit derivation of the nominal sampling rate also show good engineering discipline. However, the manuscript does not supply reproducible code, a measured sample-rate calibration, or a quantitative comparison of detected frequencies to ground-truth piano-note frequencies. Those missing elements are load-bearing for the central claim.

major comments (3)
  1. [Section 4 vs. Section 5] There is a direct internal contradiction in the reported frequency resolution. Section 4 derives Δf = F_s/512 ≈ 8.36 Hz/bin for F_s ≈ 4.28 kHz. Section 5 states 'a resolution of approximately 4.28 Hz per FFT bin' for the same 512-point FFT and the same sampling rate of roughly 4.28 kHz. These values differ by a factor of two. A 4.28 Hz/bin resolution would require F_s ≈ 2.19 kHz, not 4.28 kHz. Since the displayed frequency is presumably computed as bin_index × F_s/512 (or an equivalent scaling), this discrepancy implies either the actual sampling rate is not 4.28 kHz or the HDL bin-to-Hz conversion divides by ~1024 instead of 512. This must be resolved because it scales every reported frequency and directly affects the accuracy claim.
  2. [Section 4 and Design Flow step 5] The effective sampling rate is taken as exactly F_s = 5 MHz/(73×16) ≈ 4.28 kHz from the nominal system clock and the chosen downsampling counter values, but the paper never measures the actual sample timing. Any deviation in the ADC SPI transaction length, clock divider behavior, or debounce logic would scale every displayed frequency by a constant factor. The 'Output Calibration' step in Section 2 mentions scaling bin indexes based on the known sampling rate, but no calibration data or measured sample intervals are reported. The authors should either measure the sample cadence with ChipScope or feed a known calibration tone (e.g., a 440 Hz sine) and report the observed bin index and displayed frequency versus the expected value. Without this, the frequency output is unvalidated even if the FFT pipeline works correctly.
  3. [Section 5 and Figures 2-4] The evidence presented supports only the weaker claim that distinct piano keys produce distinct FFT bin outputs. The conclusion that 'each key press translated into a distinct frequency bin output, confirming correct implementation of the FFT and sampling pipeline' does not establish that the displayed frequencies are accurate. Figures 2-4 show oscilloscope waveforms with annotated frequencies (293.68 Hz, 130.68 Hz, 350.26 Hz), but there is no tabulated comparison to the expected piano-note frequencies, no description of how the annotated values were measured, and no stated error metric. For the central claim of detecting and displaying the dominant piano-note frequency, the authors need to compare the FPGA's LCD output to ground-truth signal frequencies for several notes and report the errors.
minor comments (5)
  1. [Equation (2)] The inverse DFT formula is misstated: the left side is written as X(k), but the right side is the synthesis formula for x(n). The 1/N factor is present, but the variable mismatch makes the equation incorrect as written.
  2. [Figures 2-4 captions] It is unclear whether the annotated frequencies (293.68 Hz, 130.68 Hz, 350.26 Hz) are oscilloscope measurements, the FPGA's LCD output, or expected note frequencies. Please state the source of these values in the captions and in the text.
  3. [Section 5 self-citation block] The paragraph citing references [3]-[25] is largely unrelated to the technical content of this project, and the claim that FPGA-based systems are 'currently the best option' is unsupported by the cited analyses in the context of this work. This block should be removed or reduced to the few references that directly inform the design.
  4. [Section 1 and 5] The term 'real-time' is used loosely. The design uses pushbutton-triggered sampling and a burst FFT, which is not continuous streaming analysis. Please either quantify the end-to-end latency or qualify the real-time claim (e.g., 'near-real-time for single notes').
  5. [Section 4] The notation F_s is used with inconsistent capitalization (F_s, Fs, fs). Also, the 73×16 downsampling rationale is not explained beyond resource constraints; a sentence on why these particular values were chosen would help.

Circularity Check

1 steps flagged · score 2.0 of 10

No circular derivation for the frequency-detection result; only a minor, non-load-bearing self-citation block and an internal factor-of-two resolution inconsistency.

  1. self citation load bearing [Section 5, Conclusion paragraph (page 17)]
    "Their analyses [3],[4] shows that FPGA-based systems are currently the best option to support applications and algorithms, such as the ones presented in this report. Also, their previous work on FPGA-based accelerators, architectures, and techniques for various compute and data-intensive applications ... demonstrated that FPGA-based systems are the best avenue to support and accelerate complex algorithms."

    The paper's motivational claim that FPGA is 'the best option' is supported exclusively by references [3] and [4], which are prior publications by the same author (Perera), plus a long chain of further self-citations. This is a self-referential support chain. However, this claim is not load-bearing for the central frequency-detection derivation: the FFT bin selection, sampling-rate computation, and LCD frequency scaling are self-contained and do not depend on these citations. The circularity is therefore minor and does not infect the main result.

full rationale

The central claim—that the FPGA system samples the analog piano signal, runs a 512-point FFT, finds the peak bin, and displays a corresponding frequency—is derived from the paper's own stated parameters: F_s = 5 MHz / (73 × 16) ≈ 4.28 kHz and Δf = F_s / 512 ≈ 8.36 Hz/bin (Section 4). There is no fitted parameter that is later renamed as a prediction, no uniqueness theorem imported from prior work, and no ansatz smuggled in via citation. The displayed frequency is simply bin_index × F_s / N, which is a definitional scaling, not a prediction equivalent to an input. The main correctness gap is that F_s is never measured and Section 5 claims '4.28 Hz per FFT bin' when Section 4 computes 8.36 Hz/bin; this is an internal calibration/validity problem, not a circularity. The large block of self-citations in Section 5 is used only to assert that FPGAs are 'the best option,' which is not essential to the frequency-detection result. Thus the overall circularity score is 2, reflecting one minor non-load-bearing self-citation, with the core derivation self-contained.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The central claim rests on standard signal-processing assumptions and an assumed sampling rate; no new physical entities or fitted parameters are introduced.

free parameters (1)
  • Effective sampling rate F_s = ≈4281 Hz
    Computed from nominal 5 MHz clock and chosen counter values (73-cycle delay, 16x downsampling) in Section 4; never measured, and it directly scales the FFT bin index to frequency.
assumptions (4)
  • domain assumption The Xilinx FFT IP core outputs the correct DFT when driven according to its datasheet timing.
    The design relies on the IP core's correctness in burst I/O mode (Section 3, FFT Engine).
  • domain assumption The ADC samples the analog input at uniform intervals determined by the SPI master's clock.
    All frequency calculations assume evenly spaced sampling (Section 4).
  • domain assumption The piano note is quasi-stationary across the 512-sample capture window (~120 ms) so the highest FFT bin represents the fundamental.
    The peak detector uses a single frame and ignores harmonics and spectral leakage (Section 3, Peak Detection).
  • standard math DFT/FFT mathematical correctness and spectral binning.
    Equation 1 defines the DFT; the paper relies on standard FFT decompositions.

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Cite this review

Pith. "Pith review of Real-Time Piano Note Frequency Detection Using FPGA and FFT Core." pith.science (2026). https://pith.science/paper/B5AHCKHH

@misc{pith2026250900589,
  author       = {Pith},
  title        = {Pith review of: Real-Time Piano Note Frequency Detection Using FPGA and FFT Core},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/B5AHCKHH}},
  note         = {Machine review of arXiv:2509.00589}
}
read the original abstract

Real-time frequency analysis of musical instruments, such as the piano, is an essential feature in areas like electronic tuners, music visualizers, and live sound monitoring. Traditional methods often rely on software-based digital signal processing (DSP), which may introduce latency and require significant computational power. In contrast, hardware platforms such as FPGAs (Field Programmable Gate Arrays) offer the ability to perform such analyses with greater speed and determinism due to their parallel processing capabilities. The primary objective of this project was to analyze analog audio signals from a digital piano using an FPGA-based real-time Fast Fourier Transform (FFT) system.

Figures

Figures reproduced from arXiv: 2509.00589 by the authors.

Figure 10
Figure 10. ILA Debugging Using ChipScope—Verifying ADC Sampling and Signal Activity This waveform shows the real-time behavior of control and data lines using ChipScope. It was used to verify correct data capture from the ADC, timing of control signals like get_sample_oneshot, and to confirm transitions between FSM states [PITH_FULL_IMAGE:figures/full_fig_p018_10.png] view at source ↗
Figure 11
Figure 11. ChipScope Debugging During FFT Feeding and Processing Stage [PITH_FULL_IMAGE:figures/full_fig_p019_11.png] view at source ↗

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Reference graph

Works this paper leans on

25 extracted references · 23 canonical work pages

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