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REVIEW 3 major objections 5 minor 125 references

XBOF: A Cost-Efficient CXL JBOF with Inter-SSD Compute Resource Sharing

T0 review · 3 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read XBOF claims that a JBOF with half the per-SSD computing resources can match a fully equipped JBOF's throughput, by having idle SSDs lend their processors and DRAM over cache-coherent CXL to handle busy SSDs' metadata work.

desk verdict A genuinely new idea for inter-SSD compute harvesting over CXL, well evaluated, but the processor-harvesting path has a real crash-consistency gap and the headline numbers rest on a self-built simulator. read the letter →

arxiv 2509.10251 v1 pith:QJVCCDEW submitted 2025-09-12 cs.OS

Shushu Yi , Yuda An , Li Peng , Xiurui Pan , Qiao Li , Jieming Yin , Guangyan Zhang , Wenfei Wu
show 6 more authors
Diyu Zhou Zhenlin Wang Xiaolin Wang Yingwei Luo Ke Zhou Jie Zhang
This is my paper · ORCID
classification cs.OS
keywords CXLJBOFSSDresourcesharingcachecoherenceflashtranslationlayerstoragevirtualizationI/Oburstscostefficiency
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

XBOF takes on the cost-utilization dilemma of just-a-bunch-of-flash (JBOF) storage servers: enterprise SSDs carry expensive processors and DRAM that sit mostly idle because I/O bursts are sporadic. The paper's central claim is that a JBOF can be built with SSDs carrying only half the normal computing resources and still deliver about the same throughput as a fully equipped JBOF, by letting idle SSDs lend their processors and DRAM over a cache-coherent CXL (Compute eXpress Link) fabric to SSDs that are busy with address translation and metadata caching. If that holds, a JBOF can cut roughly 19% of SSD bill-of-material cost without giving up burst I/O performance, and average SSD resource utilization rises by about 50%. The payoff is that lending happens at the metadata level, so read-dominated workloads also benefit and no data copy-back is needed when lenders are reclaimed.

What carries the argument

The load-bearing mechanism is the combination of disaggregated SSD internals with a cache-coherent CXL 3.0 fabric. Each SSD is split into a compute-end (processor and DRAM, running firmware such as address translation) and a data-end (flash channels, DMA engine, data buffer), and the two parts are independently visible to peers. Idle resource descriptors written into globally shared DRAM let a busy SSD atomically claim a lender's processor or DRAM segments. Processor harvesting works by NVMe queue-pair binding: a borrower queue pair is paired with a lender's shadow queue pair, and a weighted-round-robin load-balance formula splits redirected commands in proportion to both sides' processor utilization. Lender-side execution of borrower firmware is possible only because CXL keeps the borrower's address-translation mapping directory and table coherent in global fabric-attached memory, so the lender can read and update them with ordinary load/store operations. DRAM harvesting uses an online miss-ratio curve predictor to decide which segments can be lent or borrowed, plus redo logs flushed back to the borrower to protect offsite metadata; the paper reports these operations cost hundreds of nanoseconds, small relative to flash I/O.

What would settle it

Measure the round-trip latency and coherence-invalidation cost of a cache-coherent CXL peer-to-peer access between two real SSD controllers, then replay a read-dominated production trace on a two-SSD XBOF prototype: if borrower throughput falls below a conventional fully equipped JBOF by more than the claimed negligible margin, or if lender throughput drops well beyond the reported ~1.3%, the central claim is falsified.

Watch

Extended reading notes

Core claim

The paper claims that inter-SSD resource sharing over a cache-coherent fabric can substitute for per-SSD computing resources. XBOF disaggregates each SSD into a compute-end (processor and DRAM, which run firmware such as address translation) and a data-end (flash channels, DMA engine, data buffer), and exposes them separately over CXL. When one SSD's processor is saturated, typically during read bursts, the modified host NVMe (standard SSD command protocol) driver redirects a fraction of its I/O commands to an idle SSD's shadow queue pair; the lender uses the borrower's mapping tables, kept coherent in the global CXL memory space, to do command parsing and address translation, then sends DMA and flash operations back to the borrower's data-end for the actual data movement. When an SSD's onboard DRAM cannot hold enough of its mapping table, it caches table segments in a lender's DRAM with a log-based crash-consistency protocol. The evaluation claims that with half the per-SSD processors and DRAM, XBOF matches the throughput of a conventional fully equipped JBOF across microbenchmarks and production traces, improves SSD resource utilization by 50.4%, and saves 19.0% of SSD BOM cost, while the lender's own performance loss is about 1.3%.

Load-bearing premise

The whole benefit rests on the assumption that real CXL cache-coherent device-to-device access between SSDs has roughly the latency, bandwidth, and coherence cost that the paper's simulator assigns it; if remote mapping-table access and cache invalidation are several times slower on real hardware, the harvested throughput advantage shrinks toward the overhead.

Editorial extensions

If this is right

  • A JBOF with the same peak throughput can be built for roughly 19% lower SSD bill-of-material cost, so cloud storage suppliers can either serve more capacity per dollar or meet the same performance targets with cheaper hardware.
  • Read-dominated workloads, which data-redirection harvesting cannot accelerate, become shareable: the lender helps with metadata processing while data still flows from the borrower's own flash.
  • Lender reclamation no longer requires copying written data back, so the extra writes and SSD wear that plague data-redirection harvesting disappear.
  • Because resource management is decentralized through globally visible descriptors, the JBOF host's weak CPU need not become the bottleneck of the whole enclosure.
  • The changes stay inside the NVMe driver and SSD firmware, so mainstream operating systems and applications see a normal NVMe device.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same compute/data disaggregation could be applied one level up: with CXL's multi-level switching, an idle rack's SSD processors and DRAM could serve a burst on another rack, effectively pooling metadata processing across the data center rather than just one enclosure.
  • If real CXL silicon arrives with higher coherence-invalidation costs than the simulator assigns, the margin that should be tested first is the sub-microsecond remote mapping-table access; the paper's FPGA prototype cannot yet bound that cost because it states that public CXL 3.0 hardware is unavailable.
  • The mechanism is not limited to SSDs: any metadata-hungry device with bursty compute demand, such as computational storage drives, smart NICs, or memory-semantic SSDs, could borrow peer compute for address translation or index lookup while its own data path stays local.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes XBOF, a JBOF design that disaggregates each SSD into a compute-end (processor and DRAM) and a data-end (flash and DMA), and uses CXL 3.0 cache-coherent peer-to-peer communication so that idle SSDs can lend their processors and DRAM to busy SSDs. The claimed benefits are a 50.4% improvement in SSD resource utilization, a 19.0% reduction in BOM cost, and performance comparable to a conventional JBOF while using only half the per-SSD computing resources. The evaluation combines SimpleSSD-based simulation with an integrated CXL simulator (ESF), microbenchmarks and production traces, sensitivity studies, a 10-run complex scenario, and a NUMA-based end-to-end prototype.

Significance. If the central claim holds, XBOF is a significant result: it offers a concrete path to reduce JBOF BOM costs substantially while preserving performance, and it is one of the first system designs to exploit CXL 3.0 Type-2 coherent peer-to-peer access for storage resource harvesting. The paper has notable strengths: the evaluation is broad and uses third-party components where possible (SimpleSSD, public traces), the design narrative is internally consistent, and the authors provide a hardware prototype of part of the firmware path. The headline percentages are simulation outputs rather than fitted constants, and the workloads are public traces, which makes the evaluation largely falsifiable. The main weaknesses are the PLP gap in the processor-harvesting path and the dependence of the result on CXL hardware parameters that have not yet been validated on real Type-2 CXL 3.0 hardware.

major comments (3)
  1. [§4.4] Section 4.4 describes the processor-harvesting path, in which the lender executes FTL address translation and updates the borrower's mapping table via CXL load/store. The crash-consistency mechanism in §4.5 covers only the DRAM-harvesting path, where offsite metadata in the lender's DRAM is protected with log pages and cacheline flush instructions (DCCSW). The processor-harvesting path has no analogous flush or fence before I/O completion, so dirty mapping lines held in the lender's write-back cache are not reachable by the borrower's power-loss protection circuit. On borrower power loss, the completed flash write can be orphaned or the mapping can revert, violating the PLP requirement that §4.5 itself states. This is a load-bearing correctness gap for enterprise deployment and must be addressed in the design.
  2. [§4.6, §5.1, §5.4] The evaluation of the core benefit depends on the ESF CXL simulator (ref [4]) for the latency and coherence cost of Type-2 CXL peer-to-peer access, and §4.6 acknowledges that no CXL 3.0 hardware is publicly available. The central claim of XBOF rests on sub-microsecond coherent remote access and small lock/invalidation overhead, yet §5.4 varies only processor cores, DRAM capacity, and borrower/lender ratios; it never varies CXL latency, bandwidth, or coherence overhead. Please add a sensitivity study sweeping these parameters and, if possible, validate ESF against a real CXL 3.0 Type-2 device or against published hardware measurements of such devices.
  3. [§5.2, Abstract] The abstract claims a 50.4% resource-utilization improvement as a general result, but the 50.4% figure in §5.2 is reported for a single workload (256 KB sequential read, Figure 9c). Similarly, the claim of 'comparable performance to Conv in all workloads' is presented as an average over many workloads, but Figure 11 shows per-workload differences without confidence intervals or statistical significance. Please report per-workload deltas and variance, and qualify the utilization and performance claims so they are not over-generalized.
minor comments (5)
  1. [§3.2] The challenge numbering is confusing: 'Challenge 2 and 3.1' and 'Challenge 3.2' suggest that Challenge 3 has sub-challenges, but the list in §3.1 presents only three numbered challenges. Please renumber for consistency.
  2. [§5.2] The BOM cost saving of 19.0% rests on assumed market prices and a 10% premium for CXL-enabled controllers and DRAM taken from prior work (ref [95]). A short sensitivity analysis over these price inputs would materially strengthen the cost-efficiency claim.
  3. [§4.4] The load-balance formula uses variables such as W_shadowSQ and W_borrowerSQ but the notation is not fully explained in the text, making the formula hard to reproduce. Please expand the variable definitions.
  4. [Figure 9c] Figure 9c is difficult to read: the x-axis is labeled 'Time (ms)', but the harvesting-start marker and the relationship between the time axis and the workload throughput curves are not clearly explained in the caption.
  5. [General] The paper does not include an artifact availability statement. Given the 18K LOC simulator extension and the 1K/2K LOC driver and firmware modifications, releasing these artifacts would substantially improve reproducibility.

Circularity Check

1 steps flagged · score 4.0 of 10

Performance-parity claim rests on the same team's CXL simulator (ESF); otherwise the evaluation is self-contained.

  1. self citation load bearing [Section 4.6 (Simulator) and Section 5.3 (Extra latency); Ref [4]]
    "Due to the lack of publicly available CXL 3.0 hardware, we prototype the firmware-side modification of our disaggregated SSD designs on DaisyPlus OpenSSD board [45, 96]. ... To evaluate the CXL fabrics, we integrate ESF [4], a cycle-accurate CXL simulator, which can accurately model the features defined in CXL 3.0 standard [15]."

    Ref [4] (ESF) shares authors with this paper (An, Yi, Li, Wang, Luo, and Zhang). The paper's conclusion that XBOF 'takes minor Inter-SSD time (up to 2.9%)' because CXL 'delivers sub-microsecond remote access' (Section 5.3) is generated by this same-team simulator; no public CXL 3.0 hardware is used, and the NUMA emulator (Section 5.6) does not exercise CXL cache coherence. Thus the central premise of the performance-parity claim is supported by a self-citation that is not independently verified. This is load-bearing, but it is not a by-construction fit, so the rest of the evaluation retains independent content.

full rationale

The evaluation is largely self-contained: SimpleSSD is a third-party simulator, all workloads are public traces, and the cost model uses stated market prices plus an external 10% CXL-premium estimate [95]; none of the headline numbers are fitted constants or renamed inputs. The 50.4% utilization number measures the borrowed cycles directly, and the 19.0% cost saving is arithmetic from stated prices, so neither is circular. The one load-bearing self-citation is ESF [4], the same team's CXL 3.0 simulator, used in Section 4.6 to produce the sub-microsecond remote-access cost on which 'negligible performance loss' rests. Since no CXL 3.0 hardware was available and the NUMA emulation does not test CXL coherence, the quantitative core of the central claim is self-referential. This raises the score to 4; it is not 6+ because the performance parity is a simulator output conditioned on that model, not a quantity equal to its inputs by construction. XHarvest [74] appears only as related work and is not load-bearing. The power-loss-protection gap in Section 4.4 is a correctness risk rather than a circular step and does not affect this score.

Assumptions & free parameters 5 free parameters · 5 assumptions · 3 invented entities

The ledger is dominated by design parameters and modeling assumptions rather than fitted constants. The paper discloses most of them, but the headline cost and utilization numbers inherit uncertainty from the price inputs and from ESF's unvalidated CXL model.

free parameters (5)
  • busy/underutilized watermark = 75%
    Configurable trigger in Section 4.4 that decides when SSDs lend or borrow processors and data-ends. No sensitivity analysis is reported for this threshold.
  • DRAM harvesting segment size = 2 MB default
    Section 4.5 sets the granularity of DRAM lend/borrow and of the associated log pages; measured results may shift with segment size.
  • resource descriptor sync period = 10 ms
    Periodic idle-resource-descriptor updates in Sections 4.3 and 4.4 affect how quickly borrowing reacts to I/O bursts.
  • BOM price inputs = NAND $4.95/128GB, DRAM $7.2/GB, controller $48, other $6
    Section 5.2 market-price inputs; the 19.0% savings headline is arithmetic on these estimates and the paper gives no sensitivity range.
  • CXL controller/DRAM premium = 10% over Shrunk
    Section 5.2, taken from prior work [95]; it directly sets XBOF's cost disadvantage versus Shrunk and therefore its savings versus Conv.
assumptions (5)
  • domain assumption CXL 3.0 provides cache-coherent peer-to-peer access among up to 4096 points with HDM-DB coherency and sub-microsecond remote latency
    Sections 3.2 and Table 1; the entire harvesting mechanism assumes lender processors can coherently read and write borrower mapping tables at the modeled cost.
  • domain assumption ESF accurately models CXL 3.0 features
    Section 5.1 cites only ref [4], the same team's arXiv report; no independent validation of ESF appears in the paper.
  • domain assumption SimpleSSD faithfully models SSD firmware, ARM processor, DRAM, and flash timing
    Sections 4.6 and 5.1; all non-CXL SSD behavior inherits SimpleSSD's fidelity, extended by 18K LOC written by the authors.
  • domain assumption SHARDS predicts the miss ratio curve accurately enough for DRAM lend/borrow decisions
    Section 4.5 relies on SHARDS to decide when DRAM segments can be lent or should be borrowed.
  • domain assumption Reader-writer locks over remote mapping tables preserve FTL consistency across SSDs
    Section 4.4 inherits prior multi-core SSD locking schemes and applies them over CXL remote memory without a new correctness argument.
invented entities (3)
  • compute-end/data-end disaggregated SSD architecture
    purpose: Exports processor and DRAM separately from flash so resources can be harvested at fine grain
    Validated only by the authors' prototype and simulator; no real CXL SSD product implements this split.
  • shadow QP I/O redirection in the NVMe driver
    purpose: Transparently redirects borrower NVMe commands to a lender's processor
    A proposed NVMe driver mechanism whose evidence is the 1K LOC driver change and simulation only.
  • idle resource descriptor table in global fabric-attached memory
    purpose: Decentralized lending and borrowing of processor and DRAM resources among SSDs
    A new shared data structure whose correctness and overhead are shown only within the paper's own design.

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Cite this review

Pith. "Pith review of XBOF: A Cost-Efficient CXL JBOF with Inter-SSD Compute Resource Sharing." pith.science (2026). https://pith.science/paper/QJVCCDEW

@misc{pith2026250910251,
  author       = {Pith},
  title        = {Pith review of: XBOF: A Cost-Efficient CXL JBOF with Inter-SSD Compute Resource Sharing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QJVCCDEW}},
  note         = {Machine review of arXiv:2509.10251}
}
read the original abstract

Enterprise SSDs integrate numerous computing resources (e.g., ARM processor and onboard DRAM) to satisfy the ever-increasing performance requirements of I/O bursts. While these resources substantially elevate the monetary costs of SSDs, the sporadic nature of I/O bursts causes severe SSD resource underutilization in just a bunch of flash (JBOF) level. Tackling this challenge, we propose XBOF, a cost-efficient JBOF design, which only reserves moderate computing resources in SSDs at low monetary cost, while achieving demanded I/O performance through efficient inter-SSD resource sharing. Specifically, XBOF first disaggregates SSD architecture into multiple disjoint parts based on their functionality, enabling fine-grained SSD internal resource management. XBOF then employs a decentralized scheme to manage these disaggregated resources and harvests the computing resources of idle SSDs to assist busy SSDs in handling I/O bursts. This idea is facilitated by the cache-coherent capability of Compute eXpress Link (CXL), with which the busy SSDs can directly utilize the harvested computing resources to accelerate metadata processing. The evaluation results show that XBOF improves SSD resource utilization by 50.4% and saves 19.0% monetary costs with a negligible performance loss, compared to existing JBOF designs.

Figures

Figures reproduced from arXiv: 2509.10251 by the authors.

Figure 1
Figure 1. Comparison of different JBOF designs. From the scale-out aspect, SSD suppliers cluster tens of high￾performance SSDs as just a bunch of flash (JBOF) [29, 34, 67, 92, 94], which aggregates the hardware resources from every SSD to deliver extremely high throughput. Unfortunately, these technical trends place SSD consumers in a cost-utilization dilemma. To be more precise, while the increasing hardware resources elevat… view at source ↗
Figure 2
Figure 2. Details of the traditional JBOF system. I/O path. Figure 2c illustrates the I/O path in JBOF systems. When I/O requests arrive, the NVMe driver in the host sub￾mits NVMe commands to submission queues (SQ, 1 ). It then notifies the SSD of the command arrivals by ringing the SQ doorbells corresponding to the queues ( 2 ). Afterward, the SSD firmware operates the host interface controller to fetch NVMe commands from SQ… view at source ↗
Figure 3
Figure 3. Analysis of the cost-utilization dilemma. 0 2 4 6 8 1 01 2 0 1 2 3 4 N o r m al i z e d t h r o u g h p u t 0. 00 0. 05 0. 1 0 0. 1 5 0 20 40 60 80 1 00 Workl oad 0 Workl oad 1 Mi s s r a ti o ( % ) (c) MRC compari son . 25% 64K GB DRAM / TB fl ash B read 4KB wri te 0 20 40 60 80 1 00 1 20 R e s o u r c e u ti l i z a ti o n ( % ) (b) Resou rce u ti l i zati on . Proc. Fl ash I/O depth = 64 (a) Scal abi l i ty. # of… view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: Overview of XBOF. Host Interface Controller Type-2 CXL Controller Data-End Data Buffer DMA Engine Flash Ctrl. Flash Backbone DDR Ctrl. Es GC, WL Firmware Cmd. Parse Addr. Trans. Daemon XBOF Daemon Resource Monitor Resource Manager Data-End Agent Compute-End Weaker Proc…
Figure 6
Figure 6. Figure 6: Disaggregated SSD architecture. the borrower can directly cache parts of its mapping table in the lender’s DRAM ( 8 ). This harvested DRAM improves the cache hit ratio and avoids frequent flash access for the mapping table, leading to a higher I/O performance. 4.2 Disa…
Figure 7
Figure 7. Figure 7: Data structures for resource management. In the compute-end, an XBOF daemon is implemented in SSD firmware and runs on the ARM processor. It con￾tains three components: (1) A resource monitor is deployed to monitor the resource utilization of both compute-end and data-…
Figure 9
Figure 9. Figure 9: Performance benefits of processor harvesting. 4K-SeqRd 4K-Ran dRd 4K-SeqWr 4K-Ran dWr 0 50 300 350 400 450 L ate n c y (u s) Mi s s r ati o XBOF(borrow) XBOF(l en d) 0. 0 0. 2 0. 4 0. 6 0. 8 1 . 0 [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]
Figure 15
Figure 15. Figure 15: Sensitivity study on different processor resources. Host is the time consumed by the host I/O stack (e.g., NVMe driver). Host-SSD is the time for data and NVMe command transfer between the host and SSD. Processor is the time consumed to execute SSD firmware (e.g., I/O…
Figure 14
Figure 14. Figure 14: Overhead analysis (latency and energy). DRAM) in Shrunk and VH consume halved costs. According to prior work [95], we estimate the prices of CXL-enabled SSD controller and DRAM in XBOF are 10% higher than those in Shrunk. As shown in [PITH_FULL_IMAGE:figures/full_fig…
Figure 16
Figure 16. Figure 16: Analysis of varied DRAM resources. 0 20 40 60 80 1 00 0 2 4 6 8 1 0 1 2 Ban dwi dth (GB/s) C D F ( % ) Con v Sh ru n k XBOF (a) Ban dwi dth CDF. (b) Compl eti on time. 0 1 2 3 4 5 6 7 8 9 0. 0 0. 5 1 . 0 1 . 5 N o r m al i z e d tim e Grou p Con v Sh ru n k XBOF 80 90…

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