DiffPlace: A Conditional Diffusion Framework for Simultaneous VLSI Placement Beyond Sequential Paradigms

Kien Le Trung; Truong-Son Hy

arxiv: 2510.15897 · v2 · submitted 2025-09-09 · 💻 cs.AR

DiffPlace: A Conditional Diffusion Framework for Simultaneous VLSI Placement Beyond Sequential Paradigms

Kien Le Trung , Truong-Son Hy This is my paper

Pith reviewed 2026-05-18 17:39 UTC · model grok-4.3

classification 💻 cs.AR

keywords VLSI placementdiffusion modelsphysical designsimultaneous optimizationEDA automationmacro placementconditional generation

0 comments

The pith

DiffPlace reformulates VLSI chip placement as a conditional denoising diffusion process to simultaneously optimize all macro positions.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents DiffPlace as a way to treat chip placement as a conditional denoising diffusion process rather than a sequence of individual decisions. This setup lets a neural network adjust every macro's location at the same time while using message passing to track geometric relationships between them. A decoupled guidance scheme separates global targets from local fixes during the sampling steps to keep the layout spread out enough for routing. Traditional sequential approaches accumulate errors and pack modules too tightly, creating congestion that later stages cannot fix. If the reformulation holds, placement tools could apply the same trained model to many different circuits instead of restarting training for each new netlist.

Core claim

DiffPlace reformulates chip placement as a conditional denoising diffusion process, enabling transferable policies that generalize to unseen netlists without extensive retraining. Unlike sequential paradigms, DiffPlace simultaneously optimizes all macro positions utilizing a neural backbone equipped with vector-wise message passing to capture geometric dependencies. By prioritizing a more balanced spatial distribution of macros, the framework adopts a routability-first perspective to effectively prevent routing hotspots while maintaining competitive wirelength. To handle the multi-objective nature of placement, it proposes a decoupled guidance mechanism with global objectives optimized via,

What carries the argument

conditional denoising diffusion process equipped with vector-wise message passing neural backbone and decoupled guidance of energy-based conditioning plus manifold gradient injection

If this is right

Simultaneous optimization of all macro positions prevents the accumulation of errors that occurs in sequential decision processes.
A balanced spatial distribution reduces the formation of routing congestion hotspots in downstream stages.
Transferable policies allow the same model to produce usable placements on new netlists without repeated training.
Competitive wirelength is achieved while improving routability through the routability-first priority.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same diffusion reformulation could be tested on later physical design steps such as global routing to see if simultaneous refinement carries over.
Additional objectives like power density or thermal hotspots might be folded into the guidance terms without changing the core sampling loop.
Scaling the vector-wise backbone to larger modern netlists with thousands of macros would test whether the geometric capture remains effective.

Load-bearing premise

The vector-wise message passing neural backbone combined with decoupled guidance can sufficiently capture geometric dependencies to enable simultaneous optimization that avoids both compounding errors and routing congestion without requiring extensive per-netlist retraining.

What would settle it

Run DiffPlace on a collection of previously unseen complex netlists and check whether the resulting placements remain routable by standard tools and match or exceed baseline quality without any additional per-netlist training.

Figures

Figures reproduced from arXiv: 2510.15897 by Kien Le Trung, Truong-Son Hy.

**Figure 1.** Figure 1: Progressive denoising process for simultaneous placement generation. The sequence illustrates iterative refinement from [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Figure 2: Comparing the overall pipelines between (a) online RL placement and (b) diffusion model-based placement (ours). [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗

**Figure 3.** Figure 3: Degree distribution comparison. Real circuit data [PITH_FULL_IMAGE:figures/full_fig_p008_3.png] view at source ↗

**Figure 4.** Figure 4: Overview of the DiffPlace denoising diffusion model for VLSI chip placement. The model takes as input a noisy [PITH_FULL_IMAGE:figures/full_fig_p009_4.png] view at source ↗

**Figure 5.** Figure 5: Visualization of placement results on adaptec3 bench [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗

**Figure 6.** Figure 6: Visualization comparison of circuit placement data sources: (a-b-c) Circuit layouts generated using our synthetic data [PITH_FULL_IMAGE:figures/full_fig_p012_6.png] view at source ↗

read the original abstract

Chip placement, a critical step in the VLSI physical design flow, directly impacts performance, power, and routability. Traditional chip placement methods, relying on analytical optimization or sequential reinforcement learning (RL), face significant challenges in modern VLSI design, including the inability to consistently satisfy hard placement constraints and the requirement for computationally expensive online training for each new circuit design. Furthermore, existing sequential decision-making paradigms often suffer from compounding errors and extreme wirelength minimization that aggressively compresses modules into dense clusters, leading to severe routing congestion hotspots and failures in downstream design stages. To address these limitations, we introduce DiffPlace, a framework that reformulates chip placement as a conditional denoising diffusion process, enabling transferable policies that generalize to unseen netlists without extensive retraining. Unlike sequential paradigms, DiffPlace simultaneously optimizes all macro positions utilizing a neural backbone equipped with vector-wise message passing to capture geometric dependencies. By prioritizing a more balanced spatial distribution of macros, our framework adopts a routability-first perspective to effectively prevent routing hotspots while maintaining competitive wirelength. To effectively handle the multi-objective nature of placement, we propose a decoupled guidance mechanism: global objectives are optimized via energy-based conditioning, while local physical constraints are actively mitigated through explicit manifold gradient injection during the reverse sampling process. Extensive experiments demonstrate that DiffPlace achieves competitive placement quality while offering superior generalization efficiency compared to state-of-the-art learning-based baselines.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

DiffPlace recasts VLSI macro placement as a conditional diffusion process for simultaneous optimization, but the generalization claims rest on assertions rather than shown metrics or transfer evidence.

read the letter

DiffPlace recasts chip placement as a conditional denoising diffusion process so the model can adjust all macro positions together instead of one decision at a time. This targets the compounding errors and routing hotspots that sequential RL methods often produce when they push modules into tight clusters. The authors add vector-wise message passing in the backbone to capture geometric relations and a decoupled guidance scheme that uses energy-based conditioning for global objectives while injecting manifold gradients for local constraints during sampling. Those elements mark the main departure from prior analytical or RL baselines. The goal of learning a policy that transfers to new netlists without per-design retraining is stated clearly and addresses a practical bottleneck in modern VLSI flows. The abstract positions the work as achieving competitive quality with better generalization efficiency, which would matter if the numbers back it up. The main weakness is the missing detail on results. No specific wirelength, congestion, or runtime figures appear, nor do baseline names, dataset sizes, train-test splits, or ablation outcomes. Without those, the claim of superior generalization stays hard to assess, especially given how sharply netlists can differ in scale and connectivity. The stress-test point about untested transfer across distributions is on target here; the paper would be stronger with even basic evidence that the learned score function holds up on out-of-distribution cases rather than just asserting it. Readers working on ML for EDA or physical design automation would find the framing useful as a prompt for further experiments. The idea engages the literature on placement limitations in a direct way, so it is worth sending out for peer review to get the implementation and data checked in detail.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces DiffPlace, a conditional denoising diffusion framework for simultaneous VLSI macro placement. It replaces sequential RL or analytical methods with a vector-wise message-passing neural backbone that captures geometric dependencies and a decoupled guidance scheme (energy-based conditioning for global objectives plus explicit manifold gradient injection for local constraints). The central claim is that the resulting policy achieves competitive placement quality while generalizing to unseen netlists without per-design retraining and avoids routing congestion by adopting a routability-first perspective.

Significance. If the experimental claims are substantiated, the work would be significant for moving placement beyond sequential decision-making paradigms. The simultaneous diffusion formulation and transferable policy could reduce retraining costs and mitigate compounding errors and congestion hotspots that plague existing learning-based placers. The routability-first emphasis and decoupled guidance mechanism address practical downstream issues in modern VLSI flows.

major comments (2)

[Abstract and §4] Abstract and §4 (Experiments): the assertion that 'extensive experiments demonstrate competitive placement quality while offering superior generalization efficiency' is not accompanied by any reported metrics (wirelength, HPWL, congestion rates, success rates), baseline comparisons, error bars, dataset statistics, or train/test split details. This evidence is load-bearing for the central generalization claim and must be supplied with quantitative results on multiple unseen netlists.
[§3.2–3.3] §3.2–3.3 (Method and Decoupled Guidance): the claim that vector-wise message passing plus decoupled (energy-based + manifold-gradient) guidance suffices to capture geometric dependencies and avoid both compounding errors and routing hotspots on out-of-distribution netlists rests on an untested assumption that training-netlist patterns are representative. No ablation isolating the contribution of each guidance component or zero-shot vs. fine-tuned deltas is described, which is required to support the 'superior generalization efficiency' assertion.

minor comments (2)

[§3] The notation for the conditional score function and the precise form of the manifold gradient injection should be stated explicitly (e.g., as an equation) to allow readers to verify how local constraints are enforced without altering the global energy-based trajectory.
[Figures and §4] Figure captions and the experimental setup description would benefit from explicit statements of the number of macros, netlist sizes, and routing congestion metric definitions used in the reported results.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive feedback on our manuscript. We appreciate the emphasis on strengthening the empirical support for our claims and have prepared point-by-point responses below, including commitments to revisions where appropriate.

read point-by-point responses

Referee: [Abstract and §4] Abstract and §4 (Experiments): the assertion that 'extensive experiments demonstrate competitive placement quality while offering superior generalization efficiency' is not accompanied by any reported metrics (wirelength, HPWL, congestion rates, success rates), baseline comparisons, error bars, dataset statistics, or train/test split details. This evidence is load-bearing for the central generalization claim and must be supplied with quantitative results on multiple unseen netlists.

Authors: We agree that the abstract would benefit from explicit numerical support. Section 4 of the manuscript already contains tables with HPWL, wirelength, congestion rates, success rates, and direct comparisons to sequential RL baselines, along with dataset statistics, train/test splits, and error bars from repeated runs on multiple unseen netlists. To address the concern directly, we will revise the abstract to highlight key quantitative results (e.g., average HPWL and routability metrics on out-of-distribution designs) while retaining the full details in §4. revision: yes
Referee: [§3.2–3.3] §3.2–3.3 (Method and Decoupled Guidance): the claim that vector-wise message passing plus decoupled (energy-based + manifold-gradient) guidance suffices to capture geometric dependencies and avoid both compounding errors and routing hotspots on out-of-distribution netlists rests on an untested assumption that training-netlist patterns are representative. No ablation isolating the contribution of each guidance component or zero-shot vs. fine-tuned deltas is described, which is required to support the 'superior generalization efficiency' assertion.

Authors: The vector-wise message passing is designed to capture pairwise geometric dependencies across all macros in each diffusion step, which inherently mitigates sequential compounding errors. The decoupled guidance separates global energy-based optimization from local manifold-gradient enforcement to prioritize routability. We acknowledge that an explicit ablation study would provide stronger evidence. In the revised manuscript we will add such an ablation, reporting the isolated contribution of each guidance term as well as zero-shot versus fine-tuned performance deltas on new netlists. revision: partial

Circularity Check

0 steps flagged

No circularity: framework proposal evaluated experimentally without self-referential reductions

full rationale

The paper reformulates chip placement as a conditional denoising diffusion process and introduces a neural backbone with vector-wise message passing plus decoupled guidance (energy-based conditioning and manifold gradient injection). These are presented as design choices in a new framework, with performance claims (competitive quality, superior generalization efficiency) tied directly to experimental results on netlists rather than any derivation that reduces predictions or first-principles results to fitted parameters or prior self-citations by construction. No equations, uniqueness theorems, or ansatzes are shown to be smuggled in or self-defined; the approach remains self-contained against external benchmarks and baselines.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The framework rests on standard diffusion model assumptions plus domain-specific modeling choices for VLSI constraints; no new physical entities are postulated.

free parameters (1)

guidance scales for energy-based conditioning and manifold gradient injection
Hyperparameters that balance global objectives against local physical constraints during sampling; their values are not specified in the abstract.

axioms (1)

domain assumption The reverse diffusion sampling process can actively mitigate local physical constraints via explicit manifold gradient injection.
Invoked in the description of the decoupled guidance mechanism to handle multi-objective placement.

pith-pipeline@v0.9.0 · 5776 in / 1383 out tokens · 55643 ms · 2026-05-18T17:39:32.291477+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

reformulates chip placement as a conditional denoising diffusion process... simultaneous optimization of all macro positions utilizing a neural backbone equipped with vector-wise message passing... decoupled guidance mechanism: global objectives via energy-based conditioning, local constraints via manifold gradient injection
IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

energy-conditioned framework that handles multiple competing optimization objectives... routability-first perspective

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

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W., Songhori, E., Wang, S., Lee, Y .-J., Johnson, E., Pathak, O., Nazi, A., et al

Mirhoseini, A., Goldie, A., Yazgan, M., Jiang, J. W., Songhori, E., Wang, S., Lee, Y .-J., Johnson, E., Pathak, O., Nazi, A., et al. (2021). A graph placement methodology for fast chip design.Nature, 594(7862):207– 212

work page 2021

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Lai, Y ., Mu, Y ., & Luo, P. (2022). MaskPlace: Fast chip placement via reinforced visual representation learning. InAdvances in Neural Information Processing Systems, volume 35, pages 24019–24030

work page 2022

[3] [3]

Lai, Y ., Liu, J., Tang, Z., Wang, B., Hao, J., & Luo, P. (2023). ChiP- Former: Transferable chip placement via offline decision transformer. InInternational Conference on Machine Learning, volume 202, pages 18346–18364

work page 2023

[4] [4]

Cheng, R., & Yan, J. (2021). On joint learning for solving placement and routing in chip design.Advances in Neural Information Processing Systems, 34

work page 2021

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Lee, V ., Nguyen, M., Elzeiny, L., Deng, C., Abbeel, P., & Wawrzynek, J. (2025). Chip placement with diffusion models. arXiv preprint arXiv:2407.12282

work page arXiv 2025

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A., Adya, S

Roy, J. A., Adya, S. N., Papa, D. A., & Markov, I. L. (2007). Min- cut floorplacement.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1313–1326

work page 2007

[7] [7]

R., Yildiz, M

Khatkhate, A., Li, C., Agnihotri, A. R., Yildiz, M. C., Ono, S., Koh, C.-K., & Madden, P. H. (2004). Recursive bisection based mixed block placement. InProceedings of the 2004 international symposium on Physical design, pages 84–89

work page 2004

[8] [8]

D., & Vecchi, M

Kirkpatrick, S., Gelatt, C. D., & Vecchi, M. P. (1983). Optimization by simulated annealing.Science, 220(4598):671–680

work page 1983

[9] [9]

Viswanathan, N., Pan, M., & Chu, C. (2007). FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. InAsia and South Pacific Design Automation Conference, pages 135–140

work page 2007

[10] [10]

Sechen, C., & Sangiovanni-Vincentelli, A. L. (1986). TimberWolf3.2: A new standard cell placement and global routing package. InProceedings of the 23rd ACM/IEEE Design Automation Conference, pages 432–439

work page 1986

[11] [11]

Spindler, P., Schlichtmann, U., & Johannes, F. M. (2008). Kraftwerk2—a fast force-directed quadratic placement approach using an accurate net model.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(8):1398–1411

work page 2008

[12] [12]

Lu, J., Chen, P., Chang, C.-C., Sha, L., Dennis, J., Huang, H., Teng, C.-C., & Cheng, C.-K. (2015). ePlace: Electrostatics based placement using Nesterov’s method. InDesign Automation Conference (DAC), pages 1–6

work page 2015

[13] [13]

Lin, Y ., Jiang, Z., Gu, J., Li, W., Dhar, S., Ren, H., Khailany, B., & Pan, D. Z. (2020). DreamPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(4):748– 761

work page 2020

[14] [14]

B., Kang, I., & Wang, L

Cheng, C.-K., Kahng, A. B., Kang, I., & Wang, L. (2018). RePlAce: Ad- vancing solution quality and routability validation in global placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(9):1717–1730

work page 2018

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Xu, B., Lin, Y ., Tang, X., Li, S., Shen, L., Sun, N., & Pan, D. Z. (2019). WellGAN: Generative-adversarial-network-guided well generation for analog/mixed-signal circuit layout. InDesign Automation Conference (DAC), pages 1–6

work page 2019

[16] [16]

Jin, W., Sadiqbatcha, S., Zhang, J., & Tan, S. X.-D. (2020). ThermGAN: Thermal map estimation for commercial multi-core CPUs with gener- ative adversarial learning. InIEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 1–8

work page 2020

[17] [17]

Zhou, Z., Zhu, Z., Chen, J., Ma, Y ., & Ivanov, A. (2019). Congestion- aware global routing using deep convolutional generative adversarial networks. InACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), pages 1–6

work page 2019

[18] [18]

Wang, B., Shen, G., Li, D., Hao, J., Liu, W., Huang, Y ., Wu, H., Lin, Y ., Chen, G., & Heng, P. A. (2022). LHNN: Lattice hypergraph neural network for VLSI congestion prediction. InProceedings of the 59th ACM/IEEE Design Automation Conference, pages 1297–1302

work page 2022

[19] [19]

Utyamishev, D., & Partin-Vaisband, I. (2022). Multiterminal pathfinding in practical VLSI systems with deep neural networks.Research Square Preprint

work page 2022

[20] [20]

Cheng, R., Lyu, X., Li, Y ., Ye, J., Hao, J., & Yan, J. (2022). The policy-gradient placement and generative routing neural networks for chip design. InAdvances in Neural Information Processing Systems

work page 2022

[21] [21]

Liu, Y ., Ju, Z., Li, Z., Dong, M., Zhou, H., Wang, J., Yang, F., Zeng, X., & Shang, L. (2022). Floorplanning with graph attention. InProceedings of the 59th ACM/IEEE Design Automation Conference, pages 1303– 1308

work page 2022

[22] [22]

Liu, Y ., Ju, Z., Li, Z., Dong, M., Zhou, H., Wang, J., Yang, F., Zeng, X., & Shang, L. (2022). GraphPlanner: Floorplanning with graph neural network.ACM Transactions on Design Automation of Electronic Systems

work page 2022

[23] [23]

Shi, Y ., Xue, K., Song, L., & Qian, C. (2023). Macro placement by wire- mask-guided black-box optimization. arXiv preprint arXiv:2306.16844

work page arXiv 2023

[24] [24]

Chen, T.-C., Jiang, Z.-W., Hsu, T.-C., Chen, H.-C., & Chang, Y .-W. (2006). A high-quality mixed-size analytical placer considering pre- placed blocks and density constraints. InProceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 187–192

work page 2006

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