Power Hardware-in-the-loop Interfacing via $\mathcal{H}_\infty$ Model Matching

Anil Kumar Bonala; Ashley Meagher; Dmitry Rimorov; James Richard Forbes; Jonathan Eid; Rajendra Thike

REVIEW 3 major objections 5 minor 16 references

Power Hardware-in-the-loop Interfacing via $\mathcal{H}_\infty$ Model Matching

T0 review · 3 major / 5 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read This paper claims that a power hardware-in-the-loop (PHIL) interface designed via H∞ model matching with transparency as the explicit control objective is experimentally viable, achieving accuracy and stability comparable or superior to ide

desk verdict Solid, honest PHIL paper: H-infinity model matching with transparency as the objective, shown experimentally to beat ITM near the stability boundary; the main caveat is exactly the one the authors state—robustness across short-circuit ratios is empirical, not designed in. read the letter →

arxiv 2511.08370 v3 pith:5MD7CYRT submitted 2025-11-11 eess.SY cs.SY

Jonathan Eid , Ashley Meagher , Dmitry Rimorov , Anil Kumar Bonala , Rajendra Thike , James Richard Forbes This is my paper

classification eess.SYcs.SY

keywords powerhardware-in-the-loopH-infinitycontrolmodelmatchingtransparencyidealtransformermethodreal-timesimulationinterfacestabilityshort-circuitratio

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that PHIL interface design can be posed as an H∞ model-matching problem in which the interface must make the simulated grid and the physical device behave as if they were directly interconnected, a property called transparency. Because a transparent interface forces both sides toward the same ideal reference voltages and currents, it is automatically accurate and uses dynamic information from the ideal interconnection that accuracy-only formulations discard. The authors report real-time experiments with a resistive load in which the synthesized controller stayed stable and accurate at short-circuit ratios from 0.1 to 200, while a conventional ideal-transformer-method interface degraded below S=5 and became unstable around S=2. The conclusion is that model matching is a viable alternative to ITM-based interfacing, especially near the ITM instability threshold. The authors also explicitly note that the design does not include robustness considerations, so the observed stability improvement cannot be formally attributed to the method.

What carries the argument

The load-bearing object is the generalized-plant model-matching architecture, in which the controlled plant (grid simulator plus amplifier plus device under test) must match a reference plant representing the ideal direct interconnection of the grid and device. Model matching is a control architecture that makes one plant's transfer behavior match a reference plant's behavior. The performance variable stacks the four voltage and current tracking errors against the reference, plus the actuation commands, so H∞ synthesis minimizes the gain from the grid voltage to these errors. The design also encodes the experimental delay structure, per-channel scaling, and frequency-domain weighting filters

What would settle it

Run the same synthesized controller with a device under test that is not a constant resistance, such as an inductive load or a switching converter, and observe whether the voltage and current errors against the ideal reference remain bounded in the 1-kHz band. If they diverge while the nominal resistive-heater test succeeds, the claimed transparency holds only for the identified amplifier/resistor combination and not for the general PHIL interfacing problem.

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Extended reading notes

Core claim

The paper's central claim is that choosing transparency rather than accuracy as the control objective makes better use of the dynamical information in the PHIL interconnection and yields an interface that is both stable and accurate. The performance variable in the generalized plant is redefined to penalize the differences between the ROS/DUT signals and the signals of an idealized direct interconnection of the grid and device, rather than only the difference between ROS and DUT. This model-matching formulation is solved with H∞ synthesis, using loop-shaping filters, per-channel normalization, and an explicit delay structure. In real-time experiments on a resistive heater load, the model-mat

Load-bearing premise

The design assumes the power amplifier is accurately described by the identified second-order transfer function and that the device under test is the constant resistive load R2=24Ω; if the real amplifier or load deviates from these models, the transparency guarantee is not protected, and the paper itself states that the reported robustness cannot be formally attributed to the model-matching approach.

Editorial extensions

If this is right

If the central claim is correct, PHIL interfacing no longer needs to trade accuracy for stability the way impedance-based ITM variants do; designing for transparency provides both.
The model-matching formulation generalizes: any target interface representable as a transfer matrix can be encoded as the reference plant, so the approach is not limited to the ideal direct interconnection.
The experimental result at short-circuit ratios from 0.1 to 200 implies the model-matching interface operates across a wider range of grid strengths than the tested ITM baseline, which degraded below S=5 and became unstable around S=2.
Because the objective uses all the dynamical information in the ideal interconnection, the synthesized interface is a systematic alternative to heuristic ITM filter tuning, with formal optimization replacing manual trade-offs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A natural extension the authors leave implicit is to test the same architecture with non-resistive or time-varying DUTs, such as motors or converters; the main barrier would be the availability of an accurate reference model for the direct interconnection.
The wider stability range, though not formally guaranteed, may stem from the reference-model structure encoding the physical interconnection rather than from H∞ tuning alone; making robustness an explicit constraint in the model-matching formulation could test this and turn the empirical margin into a formal guarantee.
The per-channel normalization and loop-shaping filters could be adapted online to changing grid impedance, allowing the interface to track operating-point changes instead of being fixed at a single nominal short-circuit ratio.
A quantitative comparison of the achieved H∞ norm against the closed-loop frequency responses for different loads would help determine how much of the transparency property survives beyond the specific identified amplifier and constant-resistance load used in the experiment.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a genuinely useful PHIL paper. Eid et al. reformulate the interface design problem as H∞ model matching with transparency as the explicit objective, and they show on real hardware that it outperforms ITM near the stability boundary. The control machinery is standard; the contribution is the application-level reformulation and the honest experimental story.

What's new: prior H∞ PHIL work used accuracy-flavored objectives. Reformulating so the interface matches the idealized interconnection (transparency) is a real idea, and it makes good engineering sense—transparency implies accuracy, and it uses all the dynamical information in the direct grid–DUT interconnection. The experimental comparison against ITM across short-circuit ratios S ∈ {0.1, 1, 2, 5, 200} is the right kind of evidence: at S = 1 the model-matching interface is clearly better, and at S = 0.1 it remains stable while ITM is not. Those off-nominal results are genuine external checks, not circular.

Soft spots, in proportion: the validation is a single demonstration on a constant resistive heater. No repeated trials, no error bars, and no code or data shipped. That limits how strongly you can read the quantitative accuracy claims. The ITM baseline is described only as “OPAL-RT’s ITM-based interface” with an unspecified filter; a reader can’t reproduce the comparison without more detail. These are fixable in revision.

The stress-test concern about robustness is fair but the authors already flag it. Section V plainly says that no robustness considerations are in the design methodology and the stability-range improvement “cannot be formally attributed” to the model-matching approach. So the claim is not overclaimed—they say the interface was found to be robust in this experiment, not that the synthesis guarantees it. That is an honest limitation, more than a flaw. If they want to claim a general robustness property, they would need uncertainty modeling or repeated experiments with load and amplifier variation. Until then, the contribution is a well-scoped empirical demonstration, not a theorem.

Who this is for: PHIL lab practitioners and control researchers working on interface algorithms. It deserves a serious referee. The formulation is clean, the experiments are real, and the authors are upfront about the gap between design and observed robustness. I'd send it to review rather than desk reject, and I'd encourage the authors to add trials, specify the ITM filter, and publish data/code.

For my own work: yes, I'd cite this. It's a solid data point for transparency-based interface design in PHIL.

Referee Report

3 major / 5 minor

Summary. The paper proposes an H∞ model-matching approach to designing power-hardware-in-the-loop (PHIL) interfaces, using 'transparency' as the frequency-domain control objective rather than the conventional 'accuracy' metric. The interface is synthesized from identified LTI models of the ROS, DUT, and power amplifier, with the reference plant G_REF representing the ideal direct interconnection. The generalized plant includes tracking errors to the ideal voltage/current references and actuation penalties. Experimental validation on an OPAL-RT setup with a resistive heater (R2=24Ω) compares the proposed interface to an OPAL-RT ITM-based interface under varying short-circuit ratios S∈{0.1,1,2,5,200}. The paper reports accuracy comparable or superior to ITM at high S, better accuracy at S=2, and stability at low S where ITM becomes unstable. The conclusion acknowledges that the design methodology includes no explicit robustness guarantees and that the observed stability improvement cannot be formally attributed to the proposed method.

Significance. The conceptual contribution of encoding transparency via H∞ model matching is a clean and sensible reformulation of the PHIL interfacing problem, and the experimental demonstration on a real-time bench is a useful data point. If the central empirical claims were fully supported, the approach would offer a systematic alternative to ITM with potentially wider stability margins. The paper is honest about the missing robustness analysis, which is a positive feature but also a direct limitation of the claims. The manuscript would be valuable if the comparative claims are tightened and the experimental evidence is made quantitative and reproducible. As it stands, the significance is moderate: the formalism is standard and the validation is a single, incomplete demonstration.

major comments (3)

[V and Abstract/Conclusion] The central claim in the abstract and conclusion is that the proposed interface 'achieves accuracy levels and a stability range that are comparable or superior to those of the ITM-based methodology.' However, Section V concedes that 'no considerations of robustness are made in the model matching-based design methodology' and that the reported stability increase 'cannot be formally attributed to the model matching-based approach.' Since the design is synthesized for the nominal S=1 plant, the observed stability over S∈{0.1,1,2,5,200} is an empirical robustness property with no formal support. The H∞ synthesis only certifies the nominal closed loop; Fig. 6 displays nominal gains, not worst-case. This gap between the assertion and the underlying analysis is load-bearing. Either include a robustness analysis (e.g., μ-analysis over the uncertain Z1(s) and delay) or substantially temper the cl
[IV and Fig. 2] The experimental comparison is a single demonstration without repeated trials, error bars, or quantitative error metrics. The time traces in Fig. 2c are illustrative, but no RMS/peak error values are reported to substantiate 'comparable or superior.' The ITM baseline filter is described qualitatively ('a filtered version of the DUT current') with no transfer function or cutoff frequency, making the comparison irreproducible. The DUT is a fixed resistive heater, so the extension to realistic dynamic/uncertain loads is unsupported. Provide multiple runs, error statistics, and the exact ITM filter used.
[III and Fig. 5] The design assumes the one-step delay structure in Fig. 5 exactly represents the real-time latency. No identification of actual delays is presented, and no sensitivity analysis to delay mismatch is provided. In PHIL, delay is a primary stability determinant (see ITM analysis in [15]). Because the H∞ synthesis is model-based, a discrepancy between the modeled and actual delays could invalidate the results. The authors should either justify the delay structure with measurements or include a robustness analysis with respect to delay uncertainty.

minor comments (5)

[II-B and throughout] The symbol z is used both for the z-transform variable and for the performance variable vector (e.g., 'z(z)'). This is confusing; recommend using a different symbol (e.g., ζ or p) for the performance signal.
[IV] The short-circuit ratio S is never explicitly defined. State its formula (e.g., S = |V_grid|^2 / (|Z1| · P_nom)) and how Z1(s) is computed from S and the X/R ratio.
[Table I] Table I has no caption, making it difficult to interpret the scaling factors. Add a descriptive caption.
[II-D/III] The reference plant G_REF in Eq. (6) is derived assuming linear, time-invariant Z1(s) and Z_d(s). The paper would benefit from an explicit statement that the methodology currently applies to LTI loads and that extension to nonlinear or time-varying loads is not addressed.
[Throughout] Minor formatting: 'viaH ∞' in the title line and instances of 'H ∞control' are missing appropriate spaces; also 'and an H ∞ control' in the introduction. Please fix typography.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the transparency objective is defined independently from the accuracy metric used for validation, and the central claims are supported by off-nominal and comparative experiments.

full rationale

The controller is obtained by solving a standard H-infinity model-matching problem: the generalized plant is built from G_ROS, G_DUT, and G_REF (Eqs. (2), (3), (6)), and the performance variable in Eq. (7) is the difference between the physical response and the ideal-interconnection response. G_REF is a first-principles ideal circuit, not a relabeled version of the accuracy errors in Eq. (4); transparency implies accuracy is a deductive consequence of the definitions, not a definitional equivalence. The S=1 experiment is a design-point verification because the controller is synthesized for S=1, but the load-bearing claims are the off-nominal S in {0.1, 2, 5, 200} results and the comparison against ITM, neither of which is encoded in the H-infinity synthesis. No fitted parameter is renamed as a prediction: A(s) is an experimentally identified plant model used for synthesis, and R2=24 Ohm is a fixed test condition. The only author self-citation, Ref. [14] (Caverly & Forbes), is background on LMI synthesis methods and is not load-bearing; Ref. [7] is similarly background on TLM. Section V's explicit caveat that robustness is not guaranteed and that the stability-range improvement 'cannot be formally attributed to the model matching-based approach' is a limitation on generalization, not evidence of circularity. The derivation chain is therefore self-contained and externally checked.

Assumptions & free parameters 4 free parameters · 6 assumptions · 0 invented entities

The central claim rests on an experimentally identified amplifier model, hand-chosen performance weights and filter cutoffs, and a nominal S=1 design point. No new physical entities are introduced; the reference plant is an idealization, not a postulated physical object.

free parameters (4)

Amplifier transfer-function coefficients (A(s) in Eq. 8) = 6.221e9 / (s^2 + 1.255e5 s + 6.099e9)
Obtained by experimental system identification; the H∞ plant model and controller depend on this fitted model, with no uncertainty or validation reported.
Performance scaling factors = Table I values, e.g. z1,z3 weighted by (6 V)^-1, z2,z4 by (0.5 A)^-1, u1 by (200 V)^-1, u2 by (15 A)^-1
Chosen by hand to encode maximum expected or allowable magnitudes; they set the H∞ objective and thus the resulting controller's loop shape.
Loop-shaping filter cutoffs = 1 kHz low-pass on w and z1–z4, 1 kHz high-pass on z5,z6
Chosen by the authors to encode frequency content and bandwidth; performance guarantees are only claimed within this bandwidth.
Nominal design short-circuit ratio S = S=1
The controller is synthesized at S=1 and then applied at S∈{0.1,1,2,5,200}; off-nominal robustness is observed, not designed.

assumptions (6)

domain assumption All PHIL components are LTI and exactly captured by the transfer-matrix models (1)–(3).
Used throughout Section II to build P_c, P_r, and the generalized plant; no nonlinearity or parameter variation is modeled.
domain assumption The power amplifier is accurately represented by the identified second-order transfer function A(s) in Eq. (8).
Central to the DUT/amplifier model; the controller is synthesized from A(s), and no robustness to amplifier uncertainty is designed.
ad hoc to paper The one-step delay structure of Fig. 5 exactly captures the real-time communication and actuation latency.
Delay is inserted to prevent algebraic-loop issues and to model hardware latency; if real latency differs, H∞ guarantees may not hold.
ad hoc to paper The reference plant G_REF in Eq. (6), obtained from the ideal direct interconnection, is the correct target and is achievable within the 1 kHz bandwidth.
The transparency objective assumes matching this idealized interconnection is both meaningful and feasible; the paper does not analyze fundamental performance limits.
domain assumption Continuous-time models can be discretized with bilinear transform (ROS/REF) and zero-order hold (DUT/amplifier) without loss of fidelity relevant to the experiment.
Invoked in Section II-C; invalid discretization would change the frequency-domain matching properties.
standard math H∞ synthesis via LMI solvers produces a stabilizing controller achieving the displayed closed-loop gains.
Standard background used in Section III; no formal proof or code is given for the specific controller.

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Pith. "Pith review of Power Hardware-in-the-loop Interfacing via $\mathcal{H}_\infty$ Model Matching." pith.science (2026). https://pith.science/paper/5MD7CYRT

@misc{pith2026251108370,
  author       = {Pith},
  title        = {Pith review of: Power Hardware-in-the-loop Interfacing via $\mathcalH_\infty$ Model Matching},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5MD7CYRT}},
  note         = {Machine review of arXiv:2511.08370}
}

abstract

This paper presents an $\mathcal{H}_\infty$ model matching control-based approach to the problem of power hardware-in-the-loop (PHIL) interfacing. The objective is to interconnect a grid simulation and a physical device via an interface in a way that is stable and accurate. Conventional approaches include the ideal transformer method (ITM) and its impedance-based variants, which trade accuracy for stability, as well as some $\mathcal{H}_\infty$ control-based approaches, which do not make use of all the available information in their optimization for accuracy. Designing for transparency, as opposed to accuracy as existing approaches do, would achieve both accuracy and stability, while making use of all the dynamical information present in the idealized interconnection of the grid and device. The approach proposed in this paper employs model matching to formulate the PHIL problem as an $\mathcal{H}_\infty$ control problem using transparency as the explicit frequency-domain control objective. The approach is experimentally validated in a real-time resistive-load PHIL setup, and is found to achieve accuracy levels that are comparable or superior to those of an ITM-based interface.

Figures

Figures reproduced from arXiv: 2511.08370 by the authors.

**Figure 2.** PHIL experimental results [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Generalized plant and controller. The rest of the paper is organized as follows. Section II outlines the PHIL interfacing problem and how it is formed as a model matching generalized control problem. Section III outlines the proposed methodology of the interface design. Section IV presents the results of the experimental validation. Concluding remarks are provided in Section V. II. PRELIMINARIES A. Notation Througho… view at source ↗

Figures from the paper (3 more)

**Figure 4.** Figure 4: Generalized plant of the model matching control [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]

**Figure 5.** Figure 5: Illustration of the delay structure inherent to the ex [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: Frequency-domain magnitude response of the normalized closed loop. All component transfer functions have a gain less than 0 dB in the 1-kHz bandwidth, which guarantees that the steady-state time-domain response of the closed loop will be bounded within the prescribed…

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Works this paper leans on

16 extracted references · 1 linked inside Pith

[15]

Contribution to stability analysis of power hardware-in-the-loop simulators,

O. Tremblay, H. Fortin-Blanchette, R. Gagnon, and Y . Brissette, “Contribution to stability analysis of power hardware-in-the-loop simulators,”IET Gener- ation, Transmission & Distribution, vol. 11, no. 12, pp. 3073–3079, 2017

2017
[1]

Assay of renewable energy transition: A systematic literature review,

U. Bhattarai, T. Maraseni, and A. Apan, “Assay of renewable energy transition: A systematic literature review,”Sci. Total Environ., vol. 833, p. 155 159, 2022

2022
[2]

Power Hardware-in-the-Loop (PHIL): A Review to Advance Smart Inverter-Based Grid-Edge Solutions,

A. von Jouanne, E. Agamloh, and A. Yokochi, “Power Hardware-in-the-Loop (PHIL): A Review to Advance Smart Inverter-Based Grid-Edge Solutions,”Energies, vol. 16, no. 2, 2023

2023
[3]

Characteristics and design of power hardware-in-the-loop simulations for electrical power systems,

G. F. Lauss, M. O. Faruque, K. Schoder, C. Dufour, A. Viehweider, and J. Langston, “Characteristics and design of power hardware-in-the-loop simulations for electrical power systems,”IEEE Trans. Ind. Electron., vol. 63, no. 1, pp. 406–417, 2016

2016
[4]

Improve the stability and the accuracy of power hardware-in-the- loop simulation by selecting appropriate interface al- gorithms,

W. Ren, M. Steurer, and T. L. Baldwin, “Improve the stability and the accuracy of power hardware-in-the- loop simulation by selecting appropriate interface al- gorithms,” in2007 IEEE/IAS Ind. Commercial Power Syst. Tech. Conf., 2007, pp. 1–7

2007
[5]

Global transparency analysis of the Lawrence teleoperator architecture,

E. Naerum and B. Hannaford, “Global transparency analysis of the Lawrence teleoperator architecture,” in 2009 IEEE Int. Conf. Robot. Autom., 2009, pp. 4344– 4349

2009
[6]

Stability analysis of power hardware-in- the-loop simulations for grid applications,

S. Resch, J. Friedrich, T. Wagner, G. Mehlmann, and M. Luther, “Stability analysis of power hardware-in- the-loop simulations for grid applications,”Electron- ics, vol. 11, no. 1, 2022

2022
[7]

A multi-time-step transmission line inter- face for power hardware-in-the-loop simulators,

O. Tremblay, D. Rimorov, R. Gagnon, and H. Fortin- Blanchette, “A multi-time-step transmission line inter- face for power hardware-in-the-loop simulators,”IEEE Transactions on Energy Conversion, vol. 35, no. 1, pp. 539–548, 2020

2020

Show all 16 references

[8]

Optimal power hardware-in-the-loop interfacing: Applying modern control for design and verification of high-accuracy interfaces,

B. Lundstrom and M. V . Salapaka, “Optimal power hardware-in-the-loop interfacing: Applying modern control for design and verification of high-accuracy interfaces,”IEEE Trans. Ind. Electron., vol. 68, no. 11, pp. 10 388–10 399, 2021

2021
[9]

A robust power hardware-in-the-loop interface under uncertain software and hardware system,

S. Chakraborty, M. T. Rana, and M. V . Salapaka, “A robust power hardware-in-the-loop interface under uncertain software and hardware system,”IEEE Trans. Ind. Electron., vol. 72, no. 6, pp. 6088–6102, 2025

2025
[10]

Scherer,Theory of Robust Control

C. Scherer,Theory of Robust Control. [Online]. Avail- able:https://www.imng.uni- stuttgart. de/mst/files/RC.pdf
[11]

Skogestad and I

S. Skogestad and I. Postlethwaite,Multivariable Feed- back Control: Analysis and Design. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2005

2005
[12]

K. Zhou, J. C. Doyle, and K. Glover,Robust and Op- timal Control. Englewood Cliffs, NJ, USA: Prentice- Hall, Inc., 1996

1996
[13]

ExtendedH 2 andH ∞ norm characterizations and controller parametrizations for discrete-time systems,

M. C. D. Oliveira, J. C. Geromel, and J. Bernussou, “ExtendedH 2 andH ∞ norm characterizations and controller parametrizations for discrete-time systems,” International Journal of Control, vol. 75, no. 9, pp. 666–679, 2002

2002
[14]

R. J. Caverly and J. R. Forbes,LMI Properties and Applications in Systems, Stability, and Control Theory,
[2024]

[Online]

arXiv:1903.08599 [eess.SY]. [Online]. Available:https : / / arxiv . org / abs / 1903 . 08599

1903 arXiv

Pith tools

Reviewed August 3, 2026 · model on record in the stance chip above.

[1] [15]

Contribution to stability analysis of power hardware-in-the-loop simulators,

O. Tremblay, H. Fortin-Blanchette, R. Gagnon, and Y . Brissette, “Contribution to stability analysis of power hardware-in-the-loop simulators,”IET Gener- ation, Transmission & Distribution, vol. 11, no. 12, pp. 3073–3079, 2017

2017

[2] [1]

Assay of renewable energy transition: A systematic literature review,

U. Bhattarai, T. Maraseni, and A. Apan, “Assay of renewable energy transition: A systematic literature review,”Sci. Total Environ., vol. 833, p. 155 159, 2022

2022

[3] [2]

Power Hardware-in-the-Loop (PHIL): A Review to Advance Smart Inverter-Based Grid-Edge Solutions,

A. von Jouanne, E. Agamloh, and A. Yokochi, “Power Hardware-in-the-Loop (PHIL): A Review to Advance Smart Inverter-Based Grid-Edge Solutions,”Energies, vol. 16, no. 2, 2023

2023

[4] [3]

Characteristics and design of power hardware-in-the-loop simulations for electrical power systems,

G. F. Lauss, M. O. Faruque, K. Schoder, C. Dufour, A. Viehweider, and J. Langston, “Characteristics and design of power hardware-in-the-loop simulations for electrical power systems,”IEEE Trans. Ind. Electron., vol. 63, no. 1, pp. 406–417, 2016

2016

[5] [4]

Improve the stability and the accuracy of power hardware-in-the- loop simulation by selecting appropriate interface al- gorithms,

W. Ren, M. Steurer, and T. L. Baldwin, “Improve the stability and the accuracy of power hardware-in-the- loop simulation by selecting appropriate interface al- gorithms,” in2007 IEEE/IAS Ind. Commercial Power Syst. Tech. Conf., 2007, pp. 1–7

2007

[6] [5]

Global transparency analysis of the Lawrence teleoperator architecture,

E. Naerum and B. Hannaford, “Global transparency analysis of the Lawrence teleoperator architecture,” in 2009 IEEE Int. Conf. Robot. Autom., 2009, pp. 4344– 4349

2009

[7] [6]

Stability analysis of power hardware-in- the-loop simulations for grid applications,

S. Resch, J. Friedrich, T. Wagner, G. Mehlmann, and M. Luther, “Stability analysis of power hardware-in- the-loop simulations for grid applications,”Electron- ics, vol. 11, no. 1, 2022

2022

[8] [7]

A multi-time-step transmission line inter- face for power hardware-in-the-loop simulators,

O. Tremblay, D. Rimorov, R. Gagnon, and H. Fortin- Blanchette, “A multi-time-step transmission line inter- face for power hardware-in-the-loop simulators,”IEEE Transactions on Energy Conversion, vol. 35, no. 1, pp. 539–548, 2020

2020