arxiv: 2603.20486 · v3 · submitted 2026-03-20 · 💻 cs.AR

Recognition: 2 theorem links

· Lean Theorem

COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations

Subhadip Ghosh , Surya Srikar Peri , Ramprasath S. , Sosina A. Berhan , Endalk Y. Gebru , Ramesh Harjani , Sachin S. Sapatnekar

Authors on Pith no claims yet

Pith reviewed 2026-05-15 06:42 UTC · model grok-4.3

classification 💻 cs.AR

keywords RF design automationmm-wave circuitscircuit synthesislayout generationmachine learningelectromagnetic modelingLNAPA

0 comments

The pith

COmPOSER automates RF and mm-wave circuit design from specs to optimized layouts while matching expert performance.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents COmPOSER as an open-source framework that takes target performance specifications for RF and mm-wave circuits and produces complete optimized schematics and physical layouts. It unifies schematic synthesis with layout generation for both active devices and passive components plus placement and routing. Physics-based equations are combined with machine-learning models to predict electromagnetic behavior during the process. Post-layout validation on multiple low-noise amplifiers and power amplifiers operating up to 60 GHz in a commercial 65 nm CMOS process shows the generated designs meet performance targets at levels comparable to those achieved by expert manual designers. The reported outcome is a productivity increase of 100 to 300 times over traditional methods.

Core claim

COmPOSER translates target specifications into optimized circuits with layouts by unifying schematic synthesis, layout generation for actives and passives, and placement/routing while incorporating physics-based equations and machine-learning-driven electromagnetic models; post-layout validation on LNAs and PAs up to 60 GHz in a 65 nm process confirms performance targets are met comparably to expert manual designs.

What carries the argument

Performance-oriented synthesis that integrates physics-based equations with machine-learning electromagnetic models to drive both schematic creation and layout generation.

If this is right

Engineers can generate complete high-frequency circuit layouts from specifications without deep manual tuning.
Design iterations for LNAs and PAs at millimeter-wave frequencies become feasible on much shorter time scales.
The open-source release allows direct reuse and extension of the generated circuits in commercial 65 nm processes.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same synthesis approach could be tested on other analog blocks such as mixers or voltage-controlled oscillators.
Accuracy of the machine-learning models would need re-training when moving to newer process nodes beyond 65 nm.
Integration with foundry-specific layout rules could further reduce the remaining post-synthesis cleanup steps.

Load-bearing premise

The combined physics equations and machine-learning electromagnetic models produce post-layout performance predictions accurate enough to match actual silicon behavior without requiring substantial manual correction.

What would settle it

Measurement data from a fabricated chip built from a COmPOSER-generated layout showing performance that deviates substantially from the predicted targets.

Figures

Figures reproduced from arXiv: 2603.20486 by Endalk Y. Gebru, Ramesh Harjani, Ramprasath S., Sachin S. Sapatnekar, Sosina A. Berhan, Subhadip Ghosh, Surya Srikar Peri.

**Figure 2.** Figure 2: Overview of the proposed RF design automation framework: COmPOSER. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 5.** Figure 5: 2D t-SNE visualization of inductor geometry clusters [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗

**Figure 3.** Figure 3: Scatter plots of (a) 𝐿, (b) 𝑄𝑝𝑒𝑎𝑘 , (c) 𝑓𝑝𝑒𝑎𝑘𝑄 , and (d) 𝑓𝑆𝑅𝐹 . The inverse k-NN-based synthesizer identifies parameters X𝐿 = [𝑡,𝑤, 𝑟, 𝑠] that meet desired EM behavior. Given an 𝐿𝑡𝑎𝑟𝑔𝑒𝑡 from the matching network, the optimal choice among candidates X𝐿 with similar inductance (within 𝜖 = 5% value), maximizing: Í 𝑖∈M 𝑌𝐸𝑀,𝑖(X𝐿) − Í 𝑖∈ F (𝑌𝐸𝑀,𝑖(X𝐿) − 𝑌𝐸𝑀,𝑖,target) 2 , (1) (a) 1 4 -turn ( 1 4 T) (b) 1 2… view at source ↗

**Figure 4.** Figure 4: Fractional-turn variants with similar inductance. [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 6.** Figure 6: Layout primitives (not to scale) for (a) Cascode MOS, (b) Biasing MOS, (c) Resistor, (d) Capacitor, and (e) CPW. Resistors and capacitors. Resistors ( [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗

**Figure 7.** Figure 7: Layouts of LNA{1,2,4} and PA{1,2,3} (drawn to scale) [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗

**Figure 8.** Figure 8: Smith chart showing (a) input matching of LNA de [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗

read the original abstract

This work presents COmPOSER, an open-source, end-to-end framework for RF/mm-wave design automation that translates target specifications into optimized circuits with layouts. It unifies schematic synthesis, layout generation for actives and passives, and placement/routing, incorporating physics-based equations and machine-learning-driven electromagnetic models. Based on post-layout validation on multiple LNAs and PAs operating at up to 60GHz in a commercial 65nm process-kit, COmPOSER meets performance targets, comparable to expert manual designs, while delivering a 100-300x productivity gain. Github repo github[dot]com[slash]UMN-EDA[slash]COmPOSER

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

COmPOSER unifies schematic synthesis, layout generation, and ML EM models into one open-source RF flow, but its claims rest only on post-layout simulations without silicon data at 60 GHz.

read the letter

The core contribution is an end-to-end open-source pipeline that takes specs and produces both schematic and layout for mm-wave LNAs and PAs. It mixes physics equations with ML surrogates for passive EM behavior, then handles placement and routing in a single flow. That level of integration in one package is new compared to earlier piecemeal EDA tools, and the GitHub release helps with checking the implementation directly.

Referee Report

2 major / 1 minor

Summary. The paper presents COmPOSER, an open-source end-to-end framework for RF/mm-wave circuit design automation. It translates target specifications into optimized circuits and layouts by unifying schematic synthesis, layout generation for actives and passives, and placement/routing, using physics-based equations combined with machine-learning-driven electromagnetic models. The central claim is that post-layout validation on multiple LNAs and PAs up to 60 GHz in a commercial 65 nm process-kit shows that the generated circuits meet performance targets, are comparable to expert manual designs, and deliver a 100-300x productivity gain.

Significance. If the post-layout results are shown to correlate closely with silicon measurements and the productivity gains are quantified against clear baselines, the framework could meaningfully accelerate mm-wave/RF design cycles. The open-source release and unification of physics-based and ML surrogate modeling are positive features that would support broader adoption if the validation gaps are addressed.

major comments (2)

Abstract: The headline claim that COmPOSER circuits are 'comparable to expert manual designs' and require 'no substantial manual correction' rests entirely on post-layout netlist results; no measured silicon data, corner-case correlation tables, or fabricated-device performance numbers are supplied for the 60 GHz LNAs and PAs, leaving the accuracy of the ML-driven EM models against real 65 nm substrate coupling and process variation untested.
Abstract and methods summary: No quantitative metrics (e.g., specific gain, noise figure, power, or efficiency values with error bars), baseline manual-design numbers, or exclusion criteria for the 'multiple LNAs and PAs' are reported, making it impossible to verify the 'meets performance targets' and '100-300x productivity gain' assertions.

minor comments (1)

Abstract: The productivity gain range (100-300x) is stated without describing the exact measurement protocol, number of compared designs, or what constitutes a 'manual design' baseline.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive feedback. We address each major comment below, clarifying the scope of our post-layout validation and proposing specific revisions to improve transparency without overstating the results.

read point-by-point responses

Referee: Abstract: The headline claim that COmPOSER circuits are 'comparable to expert manual designs' and require 'no substantial manual correction' rests entirely on post-layout netlist results; no measured silicon data, corner-case correlation tables, or fabricated-device performance numbers are supplied for the 60 GHz LNAs and PAs, leaving the accuracy of the ML-driven EM models against real 65 nm substrate coupling and process variation untested.

Authors: We agree that silicon measurements would provide the strongest possible confirmation of the ML-driven EM models under real substrate coupling and process variation. Our validation is limited to post-layout simulations in a commercial 65 nm PDK that incorporate foundry device models and full-wave EM extraction for passives and interconnects. This is the standard validation level for RF design-automation papers prior to tape-out. We will revise the abstract to explicitly state that all comparisons are post-layout and add a brief discussion of EM-model fidelity against available foundry reference data. revision: yes
Referee: Abstract and methods summary: No quantitative metrics (e.g., specific gain, noise figure, power, or efficiency values with error bars), baseline manual-design numbers, or exclusion criteria for the 'multiple LNAs and PAs' are reported, making it impossible to verify the 'meets performance targets' and '100-300x productivity gain' assertions.

Authors: We accept that the abstract and methods summary should contain explicit quantitative anchors. The full manuscript already includes tables reporting gain, noise figure, power, PAE, and other metrics for each LNA and PA, together with direct numerical comparisons to published manual designs and productivity figures derived from designer-hour estimates. We will update the abstract with representative values and add a short paragraph in the methods section that lists the exact designs evaluated and the criteria used to select them. revision: yes

standing simulated objections not resolved

Silicon measurement data for the 60 GHz LNAs and PAs, as no fabrication was performed in this study.

Circularity Check

0 steps flagged

No significant circularity; derivation relies on external post-layout validation

full rationale

The paper's core chain translates specs via physics equations plus ML EM surrogates into layouts, then validates via post-layout simulation on multiple LNAs/PAs up to 60 GHz in 65 nm. Productivity gain (100-300x) is measured externally against manual expert designs. No equations are shown reducing to parameters fitted from the target result itself, no self-citation chains justify uniqueness or ansatzes, and no fitted-input-called-prediction pattern appears. The framework is presented as self-contained against external benchmarks, with claims resting on reported simulation-to-spec matching rather than definitional closure.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claims rest on the accuracy of physics-based device equations and pre-trained ML electromagnetic models whose training details and assumptions are not enumerated in the abstract.

free parameters (1)

ML model parameters
Machine-learning-driven electromagnetic models are trained on simulation data and therefore contain fitted parameters whose values are not reported.

axioms (1)

domain assumption Physics-based equations combined with ML models accurately capture post-layout mm-wave behavior in 65 nm CMOS
Invoked to justify both synthesis and the claim that generated designs meet targets without manual fixes.

pith-pipeline@v0.9.0 · 5450 in / 1370 out tokens · 63091 ms · 2026-05-15T06:42:58.576596+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

44 extracted references · 44 canonical work pages

[1]

Voinigescu,High-Frequency Integrated Circuits

S. Voinigescu,High-Frequency Integrated Circuits. Cambridge, UK: Cambridge University Press, 2013

work page 2013
[2]

Algorithmic design of CMOS LNAs and PAs for 60-GHz radio,

T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P. Schvan, and S. P. Voinigescu, “Algorithmic design of CMOS LNAs and PAs for 60-GHz radio, ” IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1044–1057, May 2007

work page 2007
[3]

A systematic approach to designing broadband millimeter- wave cascode common-source with inductive degeneration low noise amplifiers,

Y. Hu and T. Chi, “A systematic approach to designing broadband millimeter- wave cascode common-source with inductive degeneration low noise amplifiers, ” IEEE Transactions on Circuits and Systems I, vol. 70, no. 4, pp. 1489–1502, Jan. 2023

work page 2023
[4]

A noise optimization technique for integrated low-noise amplifiers,

J.-S. Goo, H.-T. Ahn, D. Ladwig, Z. Yu, T. Lee, and R. Dutton, “A noise optimization technique for integrated low-noise amplifiers, ”IEEE Journal of Solid-State Circuits, vol. 37, no. 8, pp. 994–1002, 2002

work page 2002
[5]

Design of CMOS power amplifiers,

A. M. Niknejad, D. Chowdhury, and J. Chen, “Design of CMOS power amplifiers, ” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 6, pp. 1784– 1796, 2012

work page 2012
[6]

Tuning of microwave filters by extracting human experience using fuzzy logic,

V. Miraftab and R. Mansour, “Tuning of microwave filters by extracting human experience using fuzzy logic, ” inIEEE MTT-S International Microwave Symposium Digest, 2005, pp. 1605–1608

work page 2005
[7]

A high-level design and opti- mization tool for analog RF receiver front-ends,

J. Crols, S. Donnay, M. Steyaert, and G. Gielen, “A high-level design and opti- mization tool for analog RF receiver front-ends, ” inProceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1995, pp. 550–553

work page 1995
[8]

Optimal RF design using smart evolutionary algorithms,

P. Vancorenland, C. De Ranter, M. Steyaert, and G. Gielen, “Optimal RF design using smart evolutionary algorithms, ” inProceedings of the ACM/IEEE Design Automation Conference, 2000, pp. 7–10

work page 2000
[9]

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel,

T. Pessoa, N. Lourenço, R. Martins, R. Póvoa, and N. Horta, “Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel, ” inProceedings of the Design, Automation & Test in Europe Conference, 2018, pp. 660–665

work page 2018
[10]

Multi-objective Bayesian opti- mization for analog/RF circuit synthesis,

W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng, “Multi-objective Bayesian opti- mization for analog/RF circuit synthesis, ” inProceedings of the ACM/IEEE Design Automation Conference, 2018, (6 pages)

work page 2018
[11]

Bayesian optimization approach for RF circuit synthesis via multitask neural network enhanced Gauss- ian process,

J. Huang, C. Tao, F. Yang, C. Yan, D. Zhou, and X. Zeng, “Bayesian optimization approach for RF circuit synthesis via multitask neural network enhanced Gauss- ian process, ”IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 11, pp. 4787–4795, Aug. 2022

work page 2022
[12]

Robust analog/RF circuit design with projection-based performance modeling,

X. Li, P. Gopalakrishnan, Y. Xu, and L. T. Pileggi, “Robust analog/RF circuit design with projection-based performance modeling, ”IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 2–15, Jan. 2007

work page 2007
[13]

Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization,

W. Cao, M. Benosman, X. Zhang, and R. Ma, “Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization, ” inProceedings of the ACM/IEEE Design Automation Conference, 2022, pp. 1015– –1020

work page 2022
[14]

Artificial neural networks for microwave computer-aided design: The state of the art,

F. Feng, W. Na, J. Jin, J. Zhang, W. Zhang, and Q.-J. Zhang, “Artificial neural networks for microwave computer-aided design: The state of the art, ”IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 11, pp. 4597–4619, Aug. 2022

work page 2022
[15]

Resid- ual network based direct synthesis of EM structures: A study on one-to-one transformers,

D. Munzer, S. Er, M. Chen, Y. Li, N. S. Mannem, T. Zhao, and H. Wang, “Resid- ual network based direct synthesis of EM structures: A study on one-to-one transformers, ” inProceedings of the IEEE Radio Frequency Integrated Circuits Symposium, 2020, pp. 143–146

work page 2020
[16]

Deep learning assisted end-to-end synthesis of mm-wave passive networks with 3D EM structures: A study on a transformer-based matching network,

S. Er, E. Liu, M. Chen, Y. Li, Y. Liu, T. Zhao, and H. Wang, “Deep learning assisted end-to-end synthesis of mm-wave passive networks with 3D EM structures: A study on a transformer-based matching network, ” inProceedings of the IEEE/MTT- S International Microwave Symposium, 2021, pp. 66–69

work page 2021
[17]

PulseRF: Physics augmented ML modeling and synthesis for high-frequency RFIC design,

H. Chae, H. Yu, S. Li, and D. Z. Pan, “PulseRF: Physics augmented ML modeling and synthesis for high-frequency RFIC design, ” inProceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2024, (9 pages)

work page 2024
[18]

Deep-learning-based inverse-designed millimeter-wave passives and power amplifiers,

E. A. Karahan, Z. Liu, and K. Sengupta, “Deep-learning-based inverse-designed millimeter-wave passives and power amplifiers, ”IEEE Journal of Solid-State Circuits, vol. 58, no. 11, pp. 3074–3088, 2023

work page 2023
[19]

Constraint-programmed initial sizing of analog operational amplifiers,

I. Abel, M. Neuner, and H. Graeb, “Constraint-programmed initial sizing of analog operational amplifiers, ” inProceedings of the IEEE International Conference on Computer Design, 2019, pp. 413–421

work page 2019
[20]

GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning,

H. Wang, K. Wang, J. Yang, L. Shen, N. Sun, H.-S. Lee, and S. Han, “GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning, ” inProceedings of the ACM/IEEE Design Automation Conference, 2020, (6 pages)

work page 2020
[21]

AutoCkt: Deep reinforcement learning of analog circuit designs,

K. Settaluri, A. Haj-Ali, Q. Huang, K. Hakhamaneshi, and B. Nikolic, “AutoCkt: Deep reinforcement learning of analog circuit designs, ” inProceedings of the Design, Automation & Test in Europe Conference, 2020, pp. 490–495

work page 2020
[22]

Acceler- ating OTA circuit design: Transistor sizing based on a transformer model and precomputed lookup tables,

S. Ghosh, E. Y. Gebru, C. V. Kashyap, R. Harjani, and S. S. Sapatnekar, “Acceler- ating OTA circuit design: Transistor sizing based on a transformer model and precomputed lookup tables, ” inProceedings of the Design, Automation & Test in Europe Conference, 2025, (7 pages)

work page 2025
[23]

ALIGN: Open-source analog layout au- tomation from the ground up,

K. Kunal, M. Madhusudan, A. K. Sharma, W. Xu, S. M. Burns, R. Harjani, J. Hu, D. A. Kirkpatrick, and S. S. Sapatnekar, “ALIGN: Open-source analog layout au- tomation from the ground up, ” inProceedings of the ACM/IEEE Design Automation Conference, 2019, (4 pages)

work page 2019
[24]

MAGICAL: An open- source fully automated analog IC layout system from netlist to GDSII,

H. Chen, M. Liu, B. Xu, K. Zhu, X. Tang, S. Li, Y. Lin, N. Sun, and D. Z. Pan, “MAGICAL: An open- source fully automated analog IC layout system from netlist to GDSII, ”IEEE Design & Test, pp. 19–26, 2021

work page 2021
[25]

BAG3++: An extensible generator framework for automated layout-aware AMS design,

F. Guo, B. Zhou, A. Biswas, P. Kwon, Z. Liu, K. Ho, V. Stojanović, and B. Nikolić, “BAG3++: An extensible generator framework for automated layout-aware AMS design, ”IEEE Open Journal of Circuits and Systems, pp. 181–191, 2025

work page 2025
[26]

GASPAD: A general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm,

B. Liu, D. Zhao, P. Reynaert, and G. G. E. Gielen, “GASPAD: A general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 169–182, Jan. 2014

work page 2014
[27]

CY- CLONE: Automated design and layout of RF LC-oscillators,

C. De Ranter, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen, “CY- CLONE: Automated design and layout of RF LC-oscillators, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 1161–1170, Oct. 2002

work page 2002
[28]

AdreamDCO: AI-driven robust and efficient design automation for digitally controlled oscillators,

Y. Hu, H. Guo, S. Wang, J. Liu, W. Cao, and T. Chi, “AdreamDCO: AI-driven robust and efficient design automation for digitally controlled oscillators, ” in Proceedings of the ACM/IEEE Design Automation Conference, 2025, (7 pages)

work page 2025
[29]

Fully automatically synthesized mm-wave low-noise amplifiers for 5G/6G applications,

L. Mendes, J. Silva, N. Lourenço, J. C. Vaz, R. Martins, and F. Passos, “Fully automatically synthesized mm-wave low-noise amplifiers for 5G/6G applications, ” IEEE Transactions on Microwave Theory and Techniques, pp. 4828–4841, 2025

work page 2025
[30]

Razavi,RF Microelectronics, 2nd ed

B. Razavi,RF Microelectronics, 2nd ed. New Jersey, USA: Prentice Hall Press, 2011

work page 2011
[31]

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits,

T. Cheung and J. Long, “Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits, ”IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1183–1200, 2006

work page 2006
[32]

Transformer-coupled power amplifier stability and power back-off analysis,

D. Chowdhury, P. Reynaert, and A. M. Niknejad, “Transformer-coupled power amplifier stability and power back-off analysis, ”IEEE Transactions on Circuits and Systems II, vol. 55, no. 6, pp. 507–511, 2008

work page 2008
[33]

L. A. Wolsey,Integer Programming. New Jersey, USA: John Wiley & Sons, Inc., 2020

work page 2020
[34]

A formal basis for the heuristic de- termination of minimum cost paths,

P. E. Hart, N. J. Nilsson, and B. Raphael, “A formal basis for the heuristic de- termination of minimum cost paths, ”IEEE Transactions on Systems Science and Cybernetics, vol. SSC-4, no. 2, pp. 100–107, 1968

work page 1968
[35]

Random forests,

L. Breiman, “Random forests, ”Machine Learning, vol. 45, no. 1, p. 5–32, Oct. 2001

work page 2001
[36]

Nearest neighbor pattern classification,

T. Cover and P. Hart, “Nearest neighbor pattern classification, ”IEEE Transactions on Information Theory, vol. 13, no. 1, pp. 21–27, 1967

work page 1967
[37]

T. H. Lee,The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed. Cam- bridge, UK: Cambridge University Press, 2003

work page 2003
[38]

A broadband 300 GHz power amplifier in a 130 nm SiGe BiCMOS technology for communication applications,

T. Bücher, J. Grzyb, P. Hillger, H. Rücker, B. Heinemann, and U. R. Pfeiffer, “A broadband 300 GHz power amplifier in a 130 nm SiGe BiCMOS technology for communication applications, ”IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2024–2034, 2022

work page 2024
[39]

Optimal cell flipping in placement and floorplanning,

C. w. Sham, E. Young, and C. Chu, “Optimal cell flipping in placement and floorplanning, ” inProceedings of the ACM/IEEE Design Automation Conference, 2006, pp. 1109–1114

work page 2006
[40]

A linear programming-based algorithm for floorplan- ning in VLSI design,

J.-G. Kim and Y.-D. Kim, “A linear programming-based algorithm for floorplan- ning in VLSI design, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 584–592, 2003

work page 2003
[41]

Gurobi Optimizer Reference Manual,

Gurobi Optimization, LLC, “Gurobi Optimizer Reference Manual, ” 2024. [Online]. Available: https://www.gurobi.com

work page 2024
[42]

Stability and power-gain invariants of linear twoports,

J. Rollett, “Stability and power-gain invariants of linear twoports, ”IRE Transac- tions on Circuit Theory, vol. 9, no. 1, pp. 29–32, 1962

work page 1962
[43]

Compact wideband LNA with gain and input matching bandwidth extensions by transformer,

P. Qin and Q. Xue, “Compact wideband LNA with gain and input matching bandwidth extensions by transformer, ”IEEE Microwave and Wireless Components Letters, vol. 27, no. 7, pp. 657–659, 2017

work page 2017
[44]

A 39 GHz T/R front-end module in 65nm CMOS,

X. Zhang, K. Qiao, Q. Chen, Y. Liang, L. Li, and J. Feng, “A 39 GHz T/R front-end module in 65nm CMOS, ” inProceedings of the IEEE International Symposium on Radio-Frequency Integration Technology, 2021, (3 pages)

work page 2021