REVIEW 3 major objections 4 minor 1 cited by
Is RISC-V Ready for Machine Learning? Portable Gaussian Processes Using Asynchronous Tasks
T0 review · 3 major / 4 minor · reviewed 2026-07-13 · grok-4.5
Pith's one-line read Portable Gaussian-process code on HPX lets a 48-core ARM chip beat a 64-core x86 chip by 9% at full node, while the tested RISC-V chip lags by factors of 14–24.
desk verdict Useful node-level GPRat/HPX numbers on one RISC-V server chip vs A64FX and Zen 2; the ISA-family recommendations overreach the single-chip sample. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The GPRat library built on the HPX asynchronous many-task runtime, which turns Gaussian-process prediction and hyperparameter optimization into portable fine-grained tasks that can be scheduled across x86-64, ARM, and RISC-V without rewriting kernels.
What would settle it
Re-run the identical GPRat/HPX prediction and hyperparameter-optimization strong-scaling and problem-size benchmarks on a newer RISC-V board that offers wide vector registers (e.g., 256-bit or 512-bit RVV) and higher memory bandwidth; if single-core and full-node slowdowns fall below a factor of two relative to the A64FX, the claim that current RISC-V is unready for these workloads would be overturned.
Extended reading notes
Core claim
On GPRat/HPX Gaussian-process prediction and hyperparameter optimization, the 48-core Fujitsu A64FX (ARM) outperforms the 64-core Zen 2 (x86-64) by 9% at full node utilization despite a 58% single-core deficit, while the SOPHON SG2042 (RISC-V) lags by up to a factor of 14 in single-core performance and up to a factor of 24 on large-scale parallel workloads; ARM and x86 stay within 23% on problem-size scaling.
Load-bearing premise
The single chips tested for each ISA (one RISC-V, one ARM, one x86) are representative enough of their families that the measured gaps generalize beyond this silicon, compiler, and GPRat/HPX setup.
Editorial extensions
If this is right
- Purpose-built ARM chips can already deliver higher full-node Gaussian-process throughput than comparable x86 parts when the runtime exposes enough parallelism.
- RISC-V platforms will remain uncompetitive for many-task machine-learning codes until they add wide-register vectorization and improved memory subsystems.
- A single portable task-based code base can fairly compare architectural efficiency across ISAs without architecture-specific kernel rewrites.
- Problem-size scaling remains comparable between ARM and x86, so ARM is already a viable host for growing Gaussian-process workloads.
Reading between the lines
- RISC-V silicon that ships full-width RVV comparable to SVE or AVX-512 could close much of the observed gap without any change to the GPRat task graph.
- The same portable evaluation method could be reapplied to other task-based ML kernels (sparse GPs, deep-kernel learning) to test whether the architecture ranking generalizes.
- Memory-bandwidth-bound phases of hyperparameter optimization are a likely dominant reason the RISC-V chip scales poorly; matching bandwidth micro-benchmarks on the same boards would confirm or refute that.
- As more many-task runtimes target RISC-V, the paper’s checklist of wide vectors plus stronger memory subsystems becomes a concrete design target for silicon vendors aiming at HPC and ML.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript extends the GPRat Gaussian-process library, built on the HPX asynchronous many-task runtime, for portability across x86-64, ARM, and RISC-V, and evaluates node-level strong scaling and problem-size scaling for GP prediction and hyperparameter optimization. On a 64-core Zen 2 (x86-64), a 48-core Fujitsu A64FX (ARM), and a SOPHON SG2042 (RISC-V), it reports a 58% single-core advantage for Zen 2 over A64FX that reverses to a 9% full-node win for A64FX; SG2042 lags by up to 14× single-core and 24× on large parallel workloads; and ARM and x86 stay within 23% on problem-size scaling. The authors conclude that purpose-built ARM is increasingly competitive and that RISC-V needs wide-register vectorization and memory-subsystem improvements for many-task GP workloads.
Significance. If the measurements and architectural attributions hold under documented controls, this is a useful empirical portability study of a many-task GP stack on three major ISAs, including early RISC-V server silicon. Strengths include concrete, falsifiable scaling numbers (single-core, full-node, problem-size), an explicit multi-ISA evaluation of GPRat/HPX, and a specific hardware recommendation (wide vectors and memory subsystem) rather than a vague performance claim. The contribution is systems evaluation rather than new GP algorithms; its value to cs.DC and scientific ML hinges on whether the reported gaps can be cleanly attributed to ISA/architecture rather than to a single chip, compiler, or runtime mapping.
major comments (3)
- The abstract’s central recommendation—that RISC-V needs wide-register vectorization and memory-subsystem improvements for many-task GPs—rests on a single evaluated part (SOPHON SG2042) versus one ARM and one x86 part. The claimed factors (up to 14× single-core, 24× parallel) and the generalization from “this chip lags” to “RISC-V is not yet ready / needs these features” are load-bearing. The manuscript must either (a) scope all conclusions strictly to the three evaluated chips and the GPRat/HPX configuration, or (b) add multi-chip sampling, architecture-tuned baselines, or sensitivity to vector width and memory parameters so the ISA-level attribution is supported.
- The reported percentages (58% single-core, 9% full-node, 14×/24× RISC-V, 23% problem-size) cannot be assessed without full methods: compiler versions and flags, BLAS/vector backends (e.g., whether RVV or SVE were used and at what width), NUMA binding, thread/task placement under HPX, and raw timing tables with error bars or repeated runs. Without these, the gaps may be dominated by software maturity rather than architectural traits. These details must appear in the experimental section and be sufficient to reproduce the attribution.
- Attribution of the RISC-V lag specifically to missing wide-register vectorization and memory-subsystem immaturity requires more than end-to-end wall-clock ratios. The paper should include supporting measurements (e.g., vectorization reports, achieved FLOP/s vs peak, bandwidth/roofline or cache-miss data, or controlled ablations with/without vector paths) that separate those factors from compiler quality and runtime mapping. Otherwise the recommendation remains an interpretation of a single-chip slowdown rather than a demonstrated architectural bottleneck.
minor comments (4)
- Clarify in the abstract and introduction what “representative” means for the three chips (one part per ISA by design vs. a broader sample), so readers do not over-read the ISA-family claims.
- State explicitly which GP kernels (prediction vs. hyperparameter optimization) drive the worst-case 14×/24× factors, and whether both workloads share the same bottleneck narrative.
- Ensure figure/table captions report core counts, problem sizes (n), and units so the 9% full-node and 23% problem-size claims are self-contained.
- Briefly define GPRat and HPX for readers outside the authors’ prior stack papers; a one-sentence pointer is enough if full background is elsewhere.
Circularity Check
No significant circularity: empirical multi-ISA node benchmarks, not forced by definition, fit, or self-citation chain.
full rationale
The paper’s load-bearing claims are measured wall-clock ratios on three external chips (Zen 2, A64FX, SOPHON SG2042) for GP prediction and hyperparameter optimization under GPRat/HPX: e.g., Zen 2’s 58% single-core edge, A64FX’s 9% full-node win, RISC-V lag factors up to 14 (single-core) and 24 (large parallel), and ARM/x86 problem-size agreement within 23%. Those numbers are timed runs against silicon and problem sizes outside the authors’ control; they are not algebraically or statistically forced by a fitted constant, a redefined metric, or a uniqueness theorem. Extending the authors’ own GPRat/HPX stack is ordinary software self-use and is not load-bearing for the performance ratios. The abstract contains no self-definitional reduction, no fitted-input-called-prediction, no uniqueness imported from prior author work, and no ansatz smuggled via citation that would make the reported gaps true by construction. Per the analyzer rules, a self-contained external-benchmark study scores 0 with empty steps.
Assumptions & free parameters
assumptions (3)
- domain assumption The SOPHON SG2042, Fujitsu A64FX, and AMD Zen 2 nodes used are representative enough of RISC-V, ARM, and x86-64 for the readiness conclusions drawn.
- domain assumption GPRat on HPX, with the (unstated) compiler and math-library stack, is a fair and architecture-neutral exercise of the three platforms for Gaussian-process ML.
- domain assumption Node-level strong scaling and problem-size scaling of GP prediction and hyperparameter optimization are sufficient proxies for ‘ready for machine learning’.
Cite this review
Pith. "Pith review of Is RISC-V Ready for Machine Learning? Portable Gaussian Processes Using Asynchronous Tasks." pith.science (2026). https://pith.science/paper/GH5NRLXO
@misc{pith2026260400736,
author = {Pith},
title = {Pith review of: Is RISC-V Ready for Machine Learning? Portable Gaussian Processes Using Asynchronous Tasks},
year = {2026},
howpublished = {\url{https://pith.science/paper/GH5NRLXO}},
note = {Machine review of arXiv:2604.00736}
}
read the original abstract
Gaussian processes are widely used in machine learning domains but remain computationally demanding, limiting their efficient scalability across emerging hardware platforms. The GPRat library addresses these challenges using the HPX asynchronous many-task runtime system. In this work, we extend GPRat to enable portability across multiple hardware architectures and evaluate its performance on representative x86-64, ARM, and RISC-V chips. We conduct node-level strong scaling and problem size scaling benchmarks for Gaussian process prediction and hyperparameter optimization to assess single-core performance, parallel scalability, and architectural efficiency. Our results show that while the x86-64 Zen 2 chip achieves a 58% single-core performance advantage over the ARM-based Fujitsu A64FX, superior parallel scaling allows the 48-core ARM chip to outperform the 64-core Zen 2 by 9% at full node utilization. The evaluated SOPHON SG2042 RISC-V chip exhibits substantially lower performance and weaker scalability, with single-core performance lagging by up to a factor of 14 and large-scale parallel workloads showing slowdowns of up to a factor of 24. For problem size scaling, ARM and x86-64 systems demonstrate comparable performance within 23%. These findings highlight the growing competitiveness of purpose-built ARM chips. Furthermore, they underscore the importance of wide-register vectorization support and improvements to the memory subsystem for upcoming RISC-V platforms, especially when targeted by many-task runtimes.
Forward citations
Cited by 1 Pith paper
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From Fork-Join to Asynchronous Tasks: Parallelizing Tiled Cholesky Decomposition with OpenMP and HPX
HPX asynchronous tasks outperform OpenMP by 15-30% on tiled Cholesky with 3.8x lower task overhead; collapsed fork-join closes most of the gap to synchronous tasking.
Reviewed July 13, 2026 · model on record in the stance chip above.
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