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arxiv: 2604.05191 · v2 · submitted 2026-04-06 · 💻 cs.ET

Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit

Xuejian Zhang , John Arnesh Divakaruni Daniel , Neil Dilley , Zhihong Chen , Joerg Appenzeller This is my paper

Pith reviewed 2026-05-10 18:41 UTC · model grok-4.3

classification 💻 cs.ET
keywords probabilistic bitP-Bitstochastic magnetic tunnel junctionCMOS integrationprobabilistic computingneuromorphic computingmagnetic tunnel junction
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The pith

A circuit of three transistors and one stochastic magnetic tunnel junction produces tunable random bits integrated on a CMOS chip.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates the first experimental realization of a probabilistic bit, or P-Bit, fully integrated into a standard CMOS process using only three transistors and one stochastic magnetic tunnel junction. This P-Bit generates stochastic voltage outputs that swing between the full supply rails and can be tuned by applied voltages. The work includes simulations showing the P-Bit operating in probabilistic logic circuits. This approach promises to bring probabilistic computing, which excels at solving problems with inherent uncertainty, into existing semiconductor manufacturing flows for better energy efficiency.

Core claim

The authors have fabricated and tested an on-chip 3T-1MTJ P-Bit that exhibits rail-to-rail stochastic output behavior, marking the first such demonstration with a stochastic MTJ in a complete CMOS integration.

What carries the argument

The 3T-1 sMTJ probabilistic bit circuit, where the stochastic magnetic tunnel junction acts as the source of tunable randomness controlled by the transistor network.

If this is right

  • The P-Bit can serve as a building block for probabilistic logic circuits, as verified through simulations.
  • Integration with CMOS allows for monolithic large-scale probabilistic computing architectures on chips.
  • Such devices support low-power solutions for probability-encoded computational problems.
  • Neuromorphic computing schemes can incorporate this P-Bit for enhanced capabilities.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If scaled, arrays of these P-Bits could solve optimization and sampling problems more efficiently than deterministic methods in certain domains.
  • The successful integration suggests that similar stochastic devices could be combined with digital logic on the same die without process conflicts.
  • Testing in actual probabilistic algorithms beyond simulations would be a next step to validate system-level benefits.

Load-bearing premise

The stochastic switching properties of the magnetic tunnel junction are preserved through the CMOS fabrication steps and electrical environment without significant degradation.

What would settle it

If repeated measurements of the P-Bit output show deterministic rather than stochastic voltage levels or no response to tuning voltages after integration, the central claim would be invalidated.

read the original abstract

Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper claims the first experimental demonstration of a fully CMOS-integrated stochastic MTJ (sMTJ)-based probabilistic bit (P-Bit) realized with a 3T-1MTJ circuit that produces rail-to-rail stochastic output. Simulations are said to confirm functionality within probabilistic logic circuits, with the overall goal of enabling monolithic large-scale probabilistic computing on CMOS chips.

Significance. If the experimental results are substantiated, the work would be significant for probabilistic computing by showing that a minimal 3T-1MTJ topology can be monolithically integrated with standard CMOS while preserving tunable stochastic behavior, thereby supporting low-power, scalable hardware for probability-encoded algorithms.

major comments (1)
  1. [Abstract] The central claim is an experimental demonstration, yet the provided manuscript text contains no measured waveforms, output statistics, error bars, device parameters, or integration-process details to verify that rail-to-rail stochastic switching was achieved post-fabrication. This directly bears on the soundness of the primary result.
minor comments (1)
  1. [Abstract] The abstract uses the informal phrase 'a mere collection of'; a more precise formulation such as 'using only three transistors and one sMTJ' would be appropriate for a journal submission.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the major comment below and will strengthen the manuscript accordingly.

read point-by-point responses

  1. Referee: [Abstract] The central claim is an experimental demonstration, yet the provided manuscript text contains no measured waveforms, output statistics, error bars, device parameters, or integration-process details to verify that rail-to-rail stochastic switching was achieved post-fabrication. This directly bears on the soundness of the primary result.

    Authors: We agree that the manuscript text would benefit from more explicit descriptions of the experimental results. The full manuscript contains measured data from the fabricated 3T-1MTJ circuit, including waveforms demonstrating rail-to-rail stochastic output and supporting statistics. In the revised version we will add detailed textual descriptions of these measured waveforms, output statistics with error bars, extracted device parameters, and the CMOS integration process details to better substantiate the experimental claims. revision: yes

Circularity Check

0 steps flagged

No significant circularity in experimental demonstration

full rationale

The paper is an experimental demonstration of a 3T-1MTJ P-Bit after CMOS integration, with the central claim resting on fabrication, integration, and measurement of stochastic output rather than any derivation chain, first-principles prediction, or fitted model. No equations, ansatzes, or predictions are presented that could reduce to inputs by construction; the abstract and provided text reference simulations only in passing without load-bearing self-citations or uniqueness theorems. The result is therefore self-contained as an empirical finding with no circular steps.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The demonstration rests on the domain assumption that sMTJs retain stochastic behavior after CMOS integration; no free parameters or new entities are introduced in the abstract.

axioms (1)
  • domain assumption Stochastic magnetic tunnel junctions generate tunable randomness suitable for P-bits
    Invoked in the abstract as the basis for the P-bit functionality

pith-pipeline@v0.9.0 · 5480 in / 1130 out tokens · 26649 ms · 2026-05-10T18:41:49.826423+00:00 · methodology

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Reference graph

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