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arxiv: 2604.07523 · v2 · submitted 2026-04-08 · 💻 cs.AR

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration

Xingzhen Chen , Jinming Zhuang , Zhuoping Yang , Shixin Ji , Sarah Schultz , Zheng Dong , Weisong Shi , Peipei Zhou This is my paper

Pith reviewed 2026-05-10 17:19 UTC · model grok-4.3

classification 💻 cs.AR
keywords DNN accelerationflexible architecturereal-time reconfigurationhardware efficiencydesign space explorationVersal FPGAheterogeneous computingaccelerator composition
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The pith

FILCO lets DNN accelerators reconfigure in real time and compose into unified or separate units to match varying workloads.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces FILCO as a flexible composing architecture for DNN acceleration on heterogeneous platforms. It claims that this design supports real-time reconfiguration and can form either one large accelerator or several smaller independent ones, avoiding the resource waste that occurs when fixed dedicated hardware meets mismatched workloads or when overlay designs switch dataflows inefficiently. An analytical model combined with two-stage design space exploration finds the best storage and computation balance for each case. When implemented and tested on a 7 nm AMD Versal VCK190 board, the approach reports 1.3x to 5x gains in throughput and hardware efficiency across diverse DNN workloads. A reader would care because current platforms often keep extra hardware idle or force suboptimal mappings; FILCO offers a single reconfigurable substrate that adapts on demand.

Core claim

FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. The accompanying FILCO framework uses an analytical model with two-stage design space exploration to reach the optimal design point, delivering 1.3x-5x higher throughput and hardware efficiency than prior dedicated or overlay architectures on varied DNN workloads.

What carries the argument

The FILCO flexible composing architecture that supports real-time reconfiguration and on-demand composition into unified or multiple accelerators, driven by an analytical model and two-stage design space exploration to select storage and computation resources.

If this is right

  • Dedicated fixed architectures will continue to suffer workload mismatch while FILCO adapts by recomposing resources at runtime.
  • Overlay designs that only switch dataflow remain limited in granularity; FILCO's composition into independent units removes that constraint.
  • The two-stage DSE reduces the search effort needed to reach an efficient mapping for each new workload.
  • On the evaluated 7 nm Versal board the design shows consistent 1.3x-5x improvements across the tested workload set.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the reconfiguration overhead truly stays low, the same fabric could support dynamic task migration between edge devices and nearby servers without hardware swaps.
  • The composition mechanism might extend naturally to other coarse-grained reconfigurable fabrics, reducing the need for multiple specialized chips in heterogeneous systems.
  • Automated mapping tools built on the analytical model could let software decide at runtime whether to run one large accelerator or several smaller ones for a given batch of inferences.

Load-bearing premise

The two-stage analytical model correctly locates the optimal design point without later manual fixes and the cost of real-time reconfiguration stays small enough not to erase the reported efficiency gains on the target hardware.

What would settle it

Measure actual throughput and efficiency on the AMD Versal VCK190 board for the same mixed DNN workloads; if the gains fall below 1.3x over strong baselines or if reconfiguration latency offsets the benefits, the central claim does not hold.

Figures

Figures reproduced from arXiv: 2604.07523 by Jinming Zhuang, Peipei Zhou, Sarah Schultz, Shixin Ji, Weisong Shi, Xingzhen Chen, Zheng Dong, Zhuoping Yang.

Figure 1
Figure 1. Figure 1: Throughput comparison for different works. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FILCO hardware architecture. the on-chip resources into Compute Units (CU), Flexible Memory Units (FMU), and IO Manager (IOM). Each Compute Unit is featured with an AI Engine (AIE) array, a CU Buffer, and a Mesh Manager, and is responsible for handling the compute-intensive workloads. The Flexible Memory Units explore data reuse by allocating on￾chip buffers on the Programmable Logic (PL). Additionally, th… view at source ↗
Figure 5
Figure 5. Figure 5: Flexible on-chip memory functionality. required to handle diverse workloads, e.g., 128x512 matrix shapes, such a static design method induces much storage overhead, and only achieves 50% efficiency due to unnecessary padding (red block). In reality, the two diverse matrices have the same data size, which can definitely be stored in one buffer. Therefore, proposing a flexible on-chip memory that is able to … view at source ↗
Figure 4
Figure 4. Figure 4: Flexible on-chip memory views. (green blocks), smaller workloads require padding, resulting in significant invalid computation (red blocks). Designing finite in￾struction blocks helps to mitigate the invalid computation, but it has significant limitations in practice. There are only 16KB of instruc￾tion memory in each AIE, and the instruction size for computing MM with a tile size of 32x32x32 is more than … view at source ↗
Figure 6
Figure 6. Figure 6: shows an overview of the FILCO framework. FILCO takes DNN models, platform information, and DDR profiling results as input. After the automated optimization flow and code generation, FILCO generates the binary files by launching the backend com￾pilers. In the first stage, Runtime Parameter Optimizer performs a brute-force search on every layer to find the optimal runtime dataflow, as well as a table with t… view at source ↗
Figure 7
Figure 7. Figure 7: Illustration diagram for GA decoder. #Ops Eff. 5,000 10,000 15,000 20,000 25,000 40,000 35,000 20% 70% 35% 100% 6.4x #Ops flexibility while keeping perf. within 5% of the peak. Flexible AIE programming (Ours) Baseline AIE programming [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Single AIE efficiency under #operations variation. [PITH_FULL_IMAGE:figures/full_fig_p005_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Throughput comparisons on diverse MM workloads. [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: Comparison of search time for MILP and GA solver. [PITH_FULL_IMAGE:figures/full_fig_p006_11.png] view at source ↗
read the original abstract

With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to achieve maximal resource efficiency. However, a mismatch between hardware and workloads always exists in various diverse workloads. Other works discuss overlay architecture that can dynamically switch dataflow for different workloads. However, these works are still limited by flexibility granularity and induce much resource inefficiency. To solve this problem, we propose a flexible composing architecture, FILCO, that can efficiently match diverse workloads to achieve the optimal storage and computation resource efficiency. FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. We also propose the FILCO framework, including an analytical model with a two-stage DSE that can achieve the optimal design point. We also evaluate the FILCO framework on the 7nm AMD Versal VCK190 board. Compared with prior works, our design can achieve 1.3x - 5x throughput and hardware efficiency on various diverse workloads.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript proposes FILCO, a flexible composing architecture for DNN acceleration on heterogeneous platforms. FILCO supports real-time reconfiguration and can be composed into either a unified accelerator or multiple independent accelerators to match diverse workloads for optimal storage and computation resource efficiency. The FILCO framework includes an analytical model paired with a two-stage design space exploration (DSE) procedure to identify optimal design points. Evaluation is performed on the 7 nm AMD Versal VCK190 board, with claims of 1.3×–5× gains in throughput and hardware efficiency versus prior dedicated and overlay architectures across various workloads.

Significance. If the central claims hold, FILCO would represent a meaningful advance in flexible DNN accelerators by bridging the gap between rigid dedicated designs and coarse-grained overlays, delivering measurable efficiency gains on diverse workloads through real-time reconfigurability. The provision of an analytical model and two-stage DSE is a strength that supports systematic optimization and potential reproducibility.

major comments (2)
  1. [Abstract / Evaluation] Abstract and Evaluation section: The 1.3×–5× throughput and hardware-efficiency claims are stated without workload specifications, baseline architectures, error bars, or a clear methodology description (including how reconfiguration overhead was measured and subtracted). This absence prevents verification that the gains are load-bearing and not negated by overhead on the VCK190.
  2. [FILCO framework / Analytical model] Analytical model and two-stage DSE (framework description): The model is used both to generate candidate designs and to assert optimality. No explicit comparison of model-predicted versus measured performance on the target board is referenced, nor is it stated whether DSE parameters were fitted to the same evaluation data; this creates a circularity risk for the optimality claim.
minor comments (2)
  1. [Abstract] The abstract uses the phrase 'various diverse workloads' without enumeration; the main text should list the concrete DNN models, batch sizes, and dataflow variants used.
  2. [Analytical model] Notation for the analytical model (e.g., definitions of storage and computation efficiency metrics) should be introduced with explicit equations and units before the DSE procedure is described.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback. We address each major comment below and outline revisions to improve clarity and address the raised concerns.

read point-by-point responses

  1. Referee: [Abstract / Evaluation] Abstract and Evaluation section: The 1.3×–5× throughput and hardware-efficiency claims are stated without workload specifications, baseline architectures, error bars, or a clear methodology description (including how reconfiguration overhead was measured and subtracted). This absence prevents verification that the gains are load-bearing and not negated by overhead on the VCK190.

    Authors: We acknowledge that the abstract provides only a high-level summary and does not enumerate specific workloads, baselines, error bars, or the overhead measurement procedure. The Evaluation section of the manuscript does detail the workloads (diverse DNN models across convolutional and transformer architectures), the baseline dedicated and overlay accelerators, error bars from repeated board measurements, and the reconfiguration overhead quantification (via direct timing on the VCK190, subtracted from end-to-end execution time). To make these elements immediately verifiable from the abstract and to strengthen the methodology description, we will revise the abstract to include brief workload and baseline references and expand the Evaluation section with an explicit overhead accounting subsection. revision: yes

  2. Referee: [FILCO framework / Analytical model] Analytical model and two-stage DSE (framework description): The model is used both to generate candidate designs and to assert optimality. No explicit comparison of model-predicted versus measured performance on the target board is referenced, nor is it stated whether DSE parameters were fitted to the same evaluation data; this creates a circularity risk for the optimality claim.

    Authors: The analytical model comprises closed-form equations derived directly from the VCK190 hardware specifications and standard DNN operation costs; no parameters were fitted to the evaluation data. The two-stage DSE uses the model solely to rank candidate designs, which are subsequently implemented and measured on the board. To eliminate any appearance of circularity, we will add a dedicated validation subsection that reports side-by-side model-predicted versus measured performance for the final selected designs, thereby confirming the model's independent predictive accuracy. revision: yes

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper describes an analytical model with two-stage DSE to identify optimal design points for the FILCO architecture, followed by hardware evaluation on the AMD Versal VCK190 achieving 1.3x-5x gains. No equations, self-citations, or derivation steps are quoted that reduce the optimality claim, performance predictions, or reconfiguration benefits directly to fitted inputs or prior self-referential results by construction. The central claims rest on external hardware benchmarks rather than internal self-definition or fitted-input renaming, making the derivation self-contained against the stated evaluation.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim depends on an unverified analytical performance model and a two-stage DSE whose accuracy is assumed rather than demonstrated; no independent evidence for the model is provided in the abstract.

free parameters (1)
  • design parameters searched in two-stage DSE
    The DSE searches or fits parameters to reach the claimed optimal design point for storage and computation efficiency.
axioms (1)
  • domain assumption The analytical model correctly predicts real hardware throughput and resource usage for reconfigured designs
    Invoked to justify that the two-stage DSE finds the optimal point and that reported gains are achievable.

pith-pipeline@v0.9.0 · 5505 in / 1261 out tokens · 37186 ms · 2026-05-10T17:19:01.036894+00:00 · methodology

discussion (0)

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