pith. sign in

arxiv: 2604.14027 · v1 · submitted 2026-04-15 · 💻 cs.AR · cs.ET

An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems

Yilmaz Ege Gonul , Baris Taskin This is my paper

Pith reviewed 2026-05-10 12:00 UTC · model grok-4.3

classification 💻 cs.AR cs.ET
keywords ASICoscillator Ising machineKuramoto modelcombinatorial optimizationmax-cutgraph coloringhardware acceleratorprocessing element array
0
0 comments X

The pith

A custom ASIC digitally emulates coupled oscillators via fixed-point Kuramoto equations to solve max-cut and graph coloring at 97-100% accuracy.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that a scalable digital ASIC can emulate oscillator-based Ising and Potts machines by implementing simplified fixed-point Kuramoto model equations in processing elements with direct interconnections. This approach addresses limitations of analog oscillators, such as low coupling resolution and process variations, while avoiding the memory bottlenecks of software emulations on CPUs and GPUs. A 20x20 array prototype with king's graph connectivity is evaluated through post-layout simulations, showing it solves unweighted and weighted max-cut plus graph coloring problems with high accuracy and marked gains in speed and energy. The work demonstrates that algorithmically codesigned ASICs can make oscillator synchronization dynamics practical for NP-hard combinatorial optimization.

Core claim

A custom ASIC architecture digitally emulates OIM/OPM dynamics using simplified fixed-point Kuramoto model equations in a scalable design with processing elements featuring direct interconnections that eliminate shared memory bottlenecks while preserving digital programmability and precision; post-layout simulations of a 20x20 array with king's graph connectivity on max-cut and graph coloring problems achieve 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms.

What carries the argument

The 20x20 processing element array with king's graph connectivity that implements simplified fixed-point Kuramoto model equations for oscillator synchronization, using direct interconnections to avoid shared memory access.

If this is right

  • The architecture solves both unweighted and weighted max-cut problems with up to 100% accuracy.
  • Graph coloring instances are solved with a maximum accuracy of 97%.
  • Direct interconnections remove the irregular memory access patterns that limit energy efficiency on GPUs and CPUs.
  • The same digital emulation framework can be scaled to larger arrays while retaining programmability.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Extending the array size or connectivity patterns could target larger real-world graphs in logistics or circuit design without redesigning the core equations.
  • If the fixed-point approximation holds across more problem classes, the design could serve as a template for other hardware accelerators that blend oscillator dynamics with digital control.
  • Hybrid systems might pair this ASIC with analog front-ends once process variation effects are quantified, potentially improving coupling resolution further.

Load-bearing premise

The simplified fixed-point Kuramoto model equations capture enough of the synchronization dynamics to solve the target optimization problems, and post-layout simulations accurately predict the behavior of a fabricated ASIC.

What would settle it

Fabricate the 20x20 ASIC and measure its actual runtime accuracy, speed, and energy on the same max-cut and graph coloring instances, checking whether results match the post-layout simulations or degrade due to unmodeled variations.

Figures

Figures reproduced from arXiv: 2604.14027 by Baris Taskin, Yilmaz Ege Gonul.

Figure 1
Figure 1. Figure 1: Fs function producing synchronization gradients based on the current phase of the oscillator demonstrated on the unit circle for Ising (N = 2) and 3-state Potts (N = 3) configuration F (2) s (ϕ) = ( −1 if (ϕ mod 0.5) < 0.25 +1 if (ϕ mod 0.5) ≥ 0.25 (3) The proposed simplified Fs extends to the 3-state Potts model, enabling a 3-state (N = 3) representation: F (3) s (ϕ) = ( −1 if ϕ ∈ [0, 1/6) ∪ [1/3, 1/2) ∪ … view at source ↗
Figure 2
Figure 2. Figure 2: An array of coupled oscillators mapped to an array [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Accuracy ranges over 100 runs on the hardware of 400 node unweighted, weighted max-cut problems in OIM mode [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
read the original abstract

Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents a custom ASIC architecture for digitally emulating oscillator-based Ising/Potts machines (OIMs/OPMs) via simplified fixed-point Kuramoto model equations. A 20x20 processing-element array with king's-graph connectivity is prototyped and evaluated exclusively through post-layout simulations on unweighted/weighted max-cut and graph-coloring instances, reporting 97-100% maximum accuracy together with speed and energy gains over general-purpose CPU/GPU platforms.

Significance. If the post-layout results prove predictive of silicon, the work would demonstrate that algorithmically co-designed digital ASICs can combine the synchronization dynamics of analog OIMs with digital programmability and precision, while the direct-interconnect PE array eliminates shared-memory bottlenecks. The explicit use of post-layout simulation with extracted parasitics is a concrete strength that grounds the efficiency claims.

major comments (2)
  1. [Abstract and §4] Abstract and §4 (Evaluation): the headline accuracy figures (97-100%) and the viability claim for algorithmically co-designed ASICs rest entirely on post-layout simulations performed at a single nominal corner with extracted parasitics. No Monte-Carlo runs, process-variation corners, or supply-noise analysis are reported; because solver correctness depends on precise fixed-point phase updates reaching the correct synchronized states, unmodeled threshold-voltage mismatch or clock skew across the king's-graph interconnect could move the observed accuracy outside the claimed range.
  2. [§3] §3 (Architecture and Model): the paper adopts a simplified fixed-point Kuramoto model without quantifying the truncation or discretization error relative to the continuous-time model or to prior analog OIM hardware. For the 20x20 array size and the evaluated problem instances, this approximation is load-bearing for the synchronization dynamics that produce the reported solutions.
minor comments (2)
  1. [Abstract] Abstract: the phrase 'significant speed and energy improvements' should be accompanied by the concrete speedup and energy figures (and the exact CPU/GPU baselines) so that the abstract is self-contained.
  2. [§4] §4: the problem instances (graph sizes, edge weights, coloring constraints) and the exact success metric (e.g., fraction of runs reaching the known optimum) should be tabulated for reproducibility.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments and recommendation for major revision. We address each major comment point by point below.

read point-by-point responses

  1. Referee: [Abstract and §4] Abstract and §4 (Evaluation): the headline accuracy figures (97-100%) and the viability claim for algorithmically co-designed ASICs rest entirely on post-layout simulations performed at a single nominal corner with extracted parasitics. No Monte-Carlo runs, process-variation corners, or supply-noise analysis are reported; because solver correctness depends on precise fixed-point phase updates reaching the correct synchronized states, unmodeled threshold-voltage mismatch or clock skew across the king's-graph interconnect could move the observed accuracy outside the claimed range.

    Authors: We acknowledge that the current results are based on post-layout simulations at a single nominal corner. While these simulations incorporate extracted parasitics and provide a grounded assessment of timing and power, we agree that additional variation analysis would strengthen the claims. In the revised manuscript we will add Monte-Carlo runs across multiple process corners together with supply-noise injection to quantify any effect on synchronization accuracy and solution quality for the evaluated instances. revision: yes

  2. Referee: [§3] §3 (Architecture and Model): the paper adopts a simplified fixed-point Kuramoto model without quantifying the truncation or discretization error relative to the continuous-time model or to prior analog OIM hardware. For the 20x20 array size and the evaluated problem instances, this approximation is load-bearing for the synchronization dynamics that produce the reported solutions.

    Authors: We agree that explicit quantification of the approximation error is warranted. The fixed-point simplification enables an efficient digital implementation while retaining the core synchronization behavior. In the revision we will add a dedicated analysis that compares fixed-point results against high-precision floating-point discrete-time simulations of the same Kuramoto equations on the evaluated max-cut and coloring instances, reporting maximum phase deviation and its impact on final solution accuracy. revision: yes

Circularity Check

0 steps flagged

No significant circularity; performance metrics derived from direct post-layout simulation of the proposed architecture

full rationale

The paper introduces a digital ASIC design that emulates oscillator Ising/Potts dynamics via fixed-point Kuramoto equations on a 20x20 king's-graph array. Accuracy results (97-100% on max-cut and graph-coloring instances) are generated by running post-layout simulations of this explicit hardware model and its interconnections. No load-bearing step redefines a fitted parameter as a prediction, imports uniqueness via self-citation, or reduces the claimed outcome to an input by construction. The derivation chain consists of architecture definition followed by independent simulation-based evaluation, remaining self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that a discretized fixed-point Kuramoto model preserves optimization-relevant dynamics and that post-layout simulation is a reliable proxy for silicon behavior.

free parameters (1)
  • fixed-point bit width
    Chosen to balance numerical precision against hardware area and power; value not specified in abstract.
axioms (1)
  • domain assumption Simplified fixed-point Kuramoto equations retain sufficient synchronization behavior for solving max-cut and graph coloring.
    Invoked when mapping oscillator dynamics to the processing element array.

pith-pipeline@v0.9.0 · 5462 in / 1268 out tokens · 40798 ms · 2026-05-10T12:00:05.719415+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. ROA-Based Subharmonic Injection Locking for Oscillator-Based Ising Machines

    cs.AR 2026-05 unverdicted novelty 5.0

    ROA-based SHIL delivers a stable 2.31 GHz signal under PVT variations and preserves 93-97% solution accuracy on a 324-node max-cut problem in OIMs where ring-oscillator SHIL fails.

Reference graph

Works this paper leans on

26 extracted references · 26 canonical work pages · cited by 1 Pith paper

  1. [1]

    E. Ising. Beitrag zur theorie des ferromagnetismus. Zeitschrift f¨ ur Physik, 31(1):253–258, February 1925

    work page 1925

  2. [2]

    F. Y. Wu. The potts model.Rev. Mod. Phys., 54:235– 268, Jan 1982

    work page 1982

  3. [3]

    A. Lucas. Ising formulations of many np problems. Frontiers in Physics, 2, 2014

    work page 2014

  4. [4]

    I. L. Markov. Limits on fundamental limits to com- putation.Nature, 512(7513):147–154, August 2014

    work page 2014

  5. [5]

    M. W. Johnson, M. H. S. Amin, S. Gildert, T. Lant- ing, F. Hamze, N. Dickson, R. Harris, A. J. Berkley, J. Johansson, P. Bunyk, E. M. Chapple, C. Enderud, J. P. Hilton, K. Karimi, E. Ladizinsky, N. Ladizinsky, T. Oh, I. Perminov, C. Rich, M. C. Thom, E. Tolka- cheva, C. J. S. Truncik, S. Uchaikin, J. Wang, B. Wil- son, and G. Rose. Quantum annealing with ...

    work page 2011

  6. [6]

    Z. Bian, F. A. Chudak, W. G. Macready, and G. Rose. The ising model: Teaching an old problem new tricks. 2010

    work page 2010

  7. [7]

    Honjo, T

    T. Honjo, T. Sonobe, K. Inaba, T. Inagaki, T. Ikuta, Y. Yamada, T. Kazama, K. Enbutsu, T. Umeki, Ry- oichi Kasahara, K. Kawarabayashi, and H. Takesue. 100,000-spin coherent ising machine.Science Ad- vances, 7(40):eabh0952, 2021

    work page 2021

  8. [8]

    Inoue, K

    K. Inoue, K. Yoshida, and S. Kitahara. Coherent potts machine based on an optical loop with a mul- tilevel phase-sensitive amplifier.Optics Communica- tions, 528:129022, 2023

    work page 2023

  9. [9]

    Inaba, T

    K. Inaba, T. Inagaki, K. Igarashi, S. Utsunomiya, T. Honjo, T. Ikuta, K. Enbutsu, T. Umeki, R. Kasa- hara, K. Inoue, Y. Yamamoto, and H. Takesue. Potts model solver based on hybrid physical and digital ar- chitecture.Commun. Phys., 5(1), May 2022

    work page 2022

  10. [10]

    Wang and J

    T. Wang and J. Roychowdhury. Oim: Oscillator- based ising machines for solving combinatorial opti- misation problems. In Ian McQuillan and Shinno- suke Seki, editors,Unconventional Computation and Natural Computation, pages 232–256, Cham, 2019. Springer International Publishing

    work page 2019

  11. [11]

    Ahmed, P

    I. Ahmed, P. Chiu, W. Moy, and C. H. Kim. A prob- abilistic compute fabric based on coupled ring oscilla- tors for solving combinatorial optimization problems. IEEE Journal of Solid-State Circuits, 56(9):2870– 2880, 2021

    work page 2021

  12. [12]

    W. Moy, I. Ahmed, P. Chiu, J. Moy, S. S. Sapatnekar, and C H. Kim. A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solv- ing.Nat. Electron., 5(5):310–317, May 2022

    work page 2022

  13. [13]

    Y. E. Gonul and B. Taskin. A multi-stage potts ma- chine based on coupled cmos ring oscillators. InPro- ceedings of the Design, Automation & Test in Europe (DATE), March 2025

    work page 2025

  14. [14]

    Y. E. Gonul and B. Taskin. Multi-phase coupled cmos ring oscillator based potts machine. InProceed- ings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD ’24, New York, NY, USA, 2025. Association for Computing Machinery

    work page 2025

  15. [15]

    N. Sica, R. Kuttappa, V. Honkote, and B. Taskin. High-speed phase-based computing. InProceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–5, 2024

    work page 2024

  16. [16]

    Y. E. Gonul, C. E. Kayan, I. Mustafazade, N. Kan- dasamy, and B. Taskin. Gpu-accelerated simulated oscillator ising/potts machine solving combinatorial optimization problems. InProceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI ’25, page 112–117, New York, NY, USA, 2025. Association for Computing Machinery

    work page 2025

  17. [17]

    Sreedhara, J

    S. Sreedhara, J. Roychowdhury, J. Wabnig, and P. Srinath. Digital emulation of oscillator ising ma- chines. InDesign, Automation & Test in Europe Con- ference & Exhibition (DATE), pages 1–2, 2023

    work page 2023

  18. [18]

    Roychowdhury and S

    J. Roychowdhury and S. Seal. Oscillator-based potts machine (opm) for the implementation of the vector potts model. Technical Report No. UCB/EECS- 2022-198, EECS University of California, Berkeley, http://www2.eecs.berkeley.edu/Pubs/TechRpts/2022/EECS- 2022-198.html, August 2022

    work page 2022

  19. [19]

    Sreedhara and J

    S. Sreedhara and J. Roychowdhury. A novel oscillator ising machine coupling scheme for high-quality opti- mization. In Da-Jung Cho and Jongmin Kim, editors, Unconventional Computation and Natural Computa- tion, pages 203–218, Cham, 2024. Springer Nature Switzerland

    work page 2024

  20. [20]

    Roychowdhury

    Tianshi Wang, Leon Wu, Parth Nobel, and Jaijeet S. Roychowdhury. Solving combinatorial optimisation problems using oscillator based ising machines.Nat- ural Computing, 20:287 – 306, 2021

    work page 2021

  21. [21]

    Atkinson.An Introduction to Numerical Anal- ysis, 2nd Ed

    K.E. Atkinson.An Introduction to Numerical Anal- ysis, 2nd Ed. Wiley India Pvt. Limited, 2008

    work page 2008

  22. [22]

    G-set benchmarks,https://web.stanford.edu/ ~yyye/yyye/gset/, Accessed: 2025-03-01

    work page 2025

  23. [23]

    Hoos and T

    H. Hoos and T. St¨ utzle.SATLIB: An online resource for research on SAT, pages 283–292. 04 2000

    work page 2000

  24. [24]

    M. K. Bashar and N. Shukla. Designing ising ma- chines with higher order spin interactions and their application in solving combinatorial optimization. Scientific Reports, 13(1), June 2023

    work page 2023

  25. [25]

    Jagielski, R

    T. Jagielski, R. Manohar, and J. Roychowdhury. Fpim: Field-programmable ising machines for solv- ing sat, 2023

    work page 2023

  26. [26]

    R. M. Karp.Reducibility among Combinatorial Prob- lems, pages 85–103. Springer US, Boston, MA, 1972. 5

    work page 1972