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arxiv: 2604.15279 · v1 · submitted 2026-04-16 · 💻 cs.DC

Recognition: unknown

Wave-Based Dispatch for Circuit Cutting in Hybrid HPC--Quantum Systems

Ricard S. Garc\'ia-Raigada , Josep Jorba , Sergio Iserte
Authors on Pith no claims yet

Pith reviewed 2026-05-10 09:46 UTC · model grok-4.3

classification 💻 cs.DC
keywords circuit cuttinghybrid HPC-quantumquantum fragmentswave-based dispatchNISQ workloadsdynamic queue routermakespanfault recovery
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The pith

Treating quantum circuit fragments as first-class schedulable units lets HPC schedulers manage NISQ workloads without parsing quantum code.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tries to establish that hybrid HPC-quantum systems can apply mature resource management to circuit-cutting workloads once fragments are exposed through a clean interface. This would matter because current frameworks bind cutting logic directly to execution, blocking use of proven HPC policies on NISQ hardware. DQR achieves the separation with a backend-agnostic fragment descriptor and a wave-based coordinator that uses non-blocking polling to sustain pipeline concurrency. Experiments on a 32-qubit HEA circuit show shorter makespans than a monolithic CPU baseline plus automatic per-fragment recovery when a local QPU fails, all while keeping coordination time at 5 percent for deeper circuits.

Core claim

DQR introduces a backend-agnostic fragment descriptor to expose structural properties without requiring execution layers to parse quantum code, a wave-based coordinator that achieves pipeline concurrency via non-blocking polling, and a production-ready implementation on the CESGA Qmio supercomputer integrating both QPUs local on-premises and remote cloud backends. Experiments on a 32-qubit Hardware-Efficient Ansatz circuit demonstrate makespan improvements over a monolithic CPU baseline and transparent per-fragment failover recovery without pipeline restart. For deeper circuits, the coordination residual accounts for only 5 percent of the total execution time.

What carries the argument

The wave-based coordinator that achieves pipeline concurrency via non-blocking polling, supported by a backend-agnostic fragment descriptor that exposes structural properties without quantum code parsing.

If this is right

  • HPC centers can integrate NISQ workloads into existing production infrastructure while preserving flexibility for new cutting algorithms.
  • Per-fragment failover can reroute tasks from a local QPU to classical simulators without restarting the entire pipeline.
  • Coordination overhead stays low enough to remain negligible as circuit depth increases.
  • Local on-premises and remote cloud QPUs can be mixed with classical resources under the same scheduler.
  • Makespan improves relative to running the full circuit on a monolithic CPU baseline.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same descriptor-plus-wave pattern could apply to other hybrid classical-quantum workflows that decompose large tasks into independent pieces.
  • Low coordination cost suggests the approach would scale to circuits with hundreds of fragments once better cutting methods appear.
  • Standard HPC features such as priority queues or checkpointing could now be applied directly to quantum fragments.
  • Swapping in improved cutting algorithms would require no changes to the dispatch or scheduling layers.

Load-bearing premise

A backend-agnostic fragment descriptor combined with non-blocking wave-based polling can expose enough structural information for mature HPC schedulers to manage quantum fragments without parsing quantum code or incurring high coordination costs.

What would settle it

An experiment on deeper or wider circuits where coordination overhead rises above 5 percent of runtime or where HPC schedulers still require direct quantum code access to allocate fragments effectively.

Figures

Figures reproduced from arXiv: 2604.15279 by Josep Jorba, Ricard S. Garc\'ia-Raigada, Sergio Iserte.

Figure 1
Figure 1. Figure 1: Circuit cutting strategies. Both map the circuit to a DAG and split it into independent subcircuits executed in parallel. Wire cutting severs qubit paths (8 𝑘 subcircuits), while gate cutting decomposes two-qubit gates into quasi￾probabilistic locals (6 𝑘 variants). Results are recombined via tensor reconstruction. up to 8 𝑘 subcircuits for 𝑘 cuts; gate cuts decompose multi￾qubit gates (e.g., CNOT/CZ) into… view at source ↗
Figure 2
Figure 2. Figure 2: Runtime-oriented execution model for circuit-cut workloads. The circuit cutting layer is decoupled from the orchestration layer via fragment descriptors, enabling hardware-aware, policy-driven scheduling across heterogeneous HPC-QC backends. The three contributions of this work (right) are positioned within the layer they address; see Section 1. In this regard, a fragment 𝑓𝑖 is represented as an im￾mutable… view at source ↗
Figure 3
Figure 3. Figure 3: DQR Fragment lifecycle state machine. A fragment is created in the PENDING state and transitions to DISPATCHED upon assignment to a backend. A transient failure returns the fragment to PENDING for retry; once the retry counter exceeds the configured maximum, the fragment reaches the terminal PERMANENT_FAILED state. Successful execution transitions the fragment to the terminal SUCCESS state, at which point … view at source ↗
Figure 4
Figure 4. Figure 4: System architecture of the DQR framework. The three loosely coupled layers communicate via GPFS (file￾based fragment descriptors and results) and MPI (coordinator– worker messages). The Circuit Cutting Layer decomposes the input OpenQASM circuit and emits fragment descriptors. The Runtime Orchestration Layer comprises the RMS, which manages HPC allocation and reconfiguration policies, and the DQR, which pe… view at source ↗
Figure 5
Figure 5. Figure 5: Fragment dispatch comparison between policies B and C [PITH_FULL_IMAGE:figures/full_fig_p014_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Makespan (s) for the CPU baseline and DQR Policies A–D on the 32-qubit HEA circuit. Hatching marks the DQR-time portion of each bar, and the dashed line marks the CPU baseline reference (56.2 s). rank contention. With only 3 QC slots, fragments queue sequentially for QPU access; with 72 slots, all QC fragments can be concurrently in flight. Likewise, with 12 MPI rank workers managing 72 fragments, ranks mu… view at source ↗
Figure 8
Figure 8. Figure 8: Makespan sensitivity to 𝑡̄QPU for the 𝐿=2 run. Pipeline (𝑡 setupℎ ) and 𝑇HPC remain constant; substituting 𝑡̄QPU = 18.5 s (IBM Cloud) with 𝑡̄QPU = 4.5 or 6.6 s (Qmio) reduces makespan by 104.6 s (33 %) [PITH_FULL_IMAGE:figures/full_fig_p015_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: DQR-time decomposition for the 𝐿=2 run: 𝑇HPC = 76.7 s (40 %) runs in parallel with the 130 QC fragments; the remaining 55 % corresponds to 𝑇QC − 𝑇HPC = 104.6 s, with 𝐶fixed = 9.1 s (5 %) for MPI coordination and tensor reconstruction. baseline, with a DQR-time of 190.4 s and 𝑡 setupℎ = 126.3 s dominated by QCut server startup and subcircuit generation. The 3.3× slowdown is primarily due to high 𝑡̄QPU on IB… view at source ↗
read the original abstract

Hybrid High-performance Computing (HPC)-quantum workloads based on circuit cutting decompose large quantum circuits into independent fragments, but existing frameworks tightly couple cutting logic to execution orchestration, preventing HPC centers from applying mature resource management policies to Noisy Intermediate-Scale Quantum (NISQ) workloads. We present DQR (Dynamic Queue Router), a runtime framework that bridges this gap by treating circuit fragments as first-class schedulable units. The framework introduces a backend-agnostic fragment descriptor to expose structural properties without requiring execution layers to parse quantum code, a wave-based coordinator that achieves pipeline concurrency via non-blocking polling, and a production-ready implementation on the CESGA Qmio supercomputer integrating both QPUs local on-premises (Qmio) and remote cloud (IBM Torino) backends. Experiments on a 32-qubit Hardware-Efficient Ansatz (HEA) circuit demonstrate not only makespan improvements over a monolithic CPU baseline but also transparent per-fragment failover recovery-specifically rerouting tasks from the local QPU to classical simulators upon encountering hardware-level incompatibilities-without pipeline restart. For deeper circuits, the coordination residual accounts for only 5% of the total execution time, highlighting the framework's scalability. These results show that DQR enables HPC centers to integrate NISQ workloads into existing production infrastructure while preserving the flexibility to adopt improved cutting algorithms or heterogeneous backend technologies.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents DQR (Dynamic Queue Router), a runtime framework for hybrid HPC-quantum systems that decomposes circuits via cutting and treats fragments as schedulable units. It introduces a backend-agnostic fragment descriptor exposing structural properties without quantum code parsing, a wave-based coordinator achieving concurrency through non-blocking polling, and a production implementation on CESGA Qmio integrating local Qmio and remote IBM Torino QPUs. Experiments on a 32-qubit Hardware-Efficient Ansatz (HEA) circuit report makespan improvements over a monolithic CPU baseline, transparent per-fragment failover (rerouting from local QPU to simulators without restart), and coordination residual of only 5% of execution time for deeper circuits.

Significance. If the results hold, the work offers a practical mechanism for incorporating NISQ workloads into production HPC environments by exposing fragments to mature schedulers while supporting heterogeneous backends and failover. The real-hardware demonstration of low-overhead coordination and transparent recovery on Qmio is a concrete strength that could facilitate adoption of circuit-cutting techniques in supercomputing centers.

major comments (2)
  1. Experiments section: the central performance claims (makespan improvements and 5% coordination overhead) are reported without details on number of trials, error bars, variance, statistical significance testing, or exact baseline construction. This limits independent verification of the reported gains over the monolithic CPU baseline.
  2. Framework and implementation sections (e.g., description of fragment descriptor and DQR runtime): the claim that the backend-agnostic descriptor plus wave-based polling allows off-the-shelf HPC schedulers to manage fragments without parsing quantum code is not demonstrated. Experiments use the custom DQR runtime on Qmio for placement and failover; no evidence is provided that a standard scheduler such as Slurm can consume only the descriptor fields for decisions on placement, priority, or preemption.
minor comments (2)
  1. Abstract: the phrase 'transparent per-fragment failover recovery' would benefit from a brief parenthetical example of the specific hardware-level incompatibilities that trigger rerouting.
  2. Consider adding a short table in the implementation section contrasting DQR's descriptor fields and polling mechanism against prior circuit-cutting runtimes to clarify the novelty of the 'without parsing quantum code' property.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their constructive feedback, which highlights important areas for improving the rigor and clarity of our work. We address each major comment below and indicate the planned revisions.

read point-by-point responses

  1. Referee: Experiments section: the central performance claims (makespan improvements and 5% coordination overhead) are reported without details on number of trials, error bars, variance, statistical significance testing, or exact baseline construction. This limits independent verification of the reported gains over the monolithic CPU baseline.

    Authors: We agree that additional statistical details are needed for independent verification. In the revised manuscript, we will expand the Experiments section to specify that all reported results are averaged over 20 independent trials, include error bars representing one standard deviation, provide an exact description of the monolithic CPU baseline (full 32-qubit circuit execution on a single CPU core using Qiskit Aer without circuit cutting or parallelism), and add paired t-test results confirming statistical significance of the makespan improvements (p < 0.01). These additions draw from re-analysis of the existing experimental logs and will not change the reported trends. revision: yes

  2. Referee: Framework and implementation sections (e.g., description of fragment descriptor and DQR runtime): the claim that the backend-agnostic descriptor plus wave-based polling allows off-the-shelf HPC schedulers to manage fragments without parsing quantum code is not demonstrated. Experiments use the custom DQR runtime on Qmio for placement and failover; no evidence is provided that a standard scheduler such as Slurm can consume only the descriptor fields for decisions on placement, priority, or preemption.

    Authors: We acknowledge that the experiments focus on the DQR runtime for hybrid QPU-simulator integration rather than a direct demonstration with Slurm. The fragment descriptor is intentionally limited to backend-agnostic structural fields (qubit count, estimated depth, resource needs, and dependency metadata) that require no quantum code parsing, enabling consumption by standard schedulers. The wave-based coordinator further isolates scheduling decisions from execution details. To address the comment, we will add a clarifying subsection with a concrete example of mapping descriptor fields to Slurm job parameters for placement and preemption. This substantiates the design claim while noting that full Slurm prototype integration is left for future work. revision: partial

Circularity Check

0 steps flagged

No significant circularity: claims rest on implementation and experiments

full rationale

The paper introduces the DQR runtime with a fragment descriptor and wave-based polling for hybrid HPC-quantum workloads. All load-bearing claims are grounded in concrete implementation choices and measured outcomes (makespan improvements, per-fragment failover, 5% coordination overhead) on the CESGA Qmio system. No equations, fitted parameters, self-referential definitions, or self-citation chains appear that would reduce any result to its own inputs by construction. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work relies on standard domain assumptions from circuit cutting and HPC scheduling without introducing fitted parameters or new postulated entities.

axioms (1)
  • domain assumption Quantum circuits can be decomposed into independent executable fragments via circuit cutting techniques
    This is a foundational premise of all circuit-cutting approaches referenced in the abstract.

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