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arxiv: 2604.15361 · v1 · submitted 2026-04-13 · 💻 cs.AR · cs.SI

GEN-Graph: Heterogeneous PIM Accelerator for General Computational Patterns in Graph-based Dynamic Programming

Yanru Chen , Runyang Tian , Zheyu Li , Mahbod Afarin , Weihong Xu , Tajana Rosing This is my paper

Pith reviewed 2026-05-10 16:38 UTC · model grok-4.3

classification 💻 cs.AR cs.SI
keywords heterogeneous PIMgraph dynamic programmingprocessing-in-memoryall-pairs shortest pathsequence alignment2.5D integrationaccelerator design
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The pith

A heterogeneous PIM chiplet with matrix and traversal tiles handles conflicting patterns in graph dynamic programming exactly and scalably.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to establish that graph-based dynamic programming, central to genomics and network analytics, faces inefficiency because its matrix-centric and topology-centric variants have incompatible dataflows that defeat homogeneous hardware. GEN-Graph addresses this by packaging a processing-using-memory matrix tile for regular compute-bound work such as all-pairs shortest paths together with a processing-near-memory traversal tile for irregular memory-bound work such as DNA sequence alignment. Recursive partitioning and reconfigurable windowed bit-parallel logic keep all results exact. The design delivers 42.8 times speedup and 392 times better energy efficiency than an NVIDIA H100 GPU on APSP, plus millions of sequence reads per second on alignment tasks. If the approach holds, it would let practitioners run large exact DP computations on energy-efficient near-memory hardware instead of power-hungry general-purpose processors.

Core claim

GEN-Graph provides the first scalable, exact solution for general DP dataflows by matching hardware specialization to algorithmic structure, integrating a Matrix-tile optimized for matrix-centric workloads like APSP and a traversal-tile optimized for topology-centric workloads like DNA sequence alignment inside a 2.5D package through recursive partitioning and reconfigurable windowed bit-parallel logic.

What carries the argument

Heterogeneous 2.5D PIM chiplet combining a PUM Matrix-tile and a PNM traversal-tile, supported by recursive partitioning and reconfigurable windowed bit-parallel logic to preserve exactness across both DP patterns.

If this is right

  • The matrix tile delivers 42.8 times speedup and 392 times energy efficiency over an NVIDIA H100 GPU for all-pairs shortest path.
  • The traversal tile sustains 2.56 million short reads per second and 39.3 thousand long reads per second for sequence-to-graph alignment.
  • Throughput for alignment tasks exceeds state-of-the-art accelerators by up to 2.56 times.
  • The architecture supplies a scalable exact solution for both matrix-centric and traversal-centric DP where homogeneous PIM falls short.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Similar heterogeneous PIM partitioning could be tested on other scientific workloads that mix dense linear algebra with irregular graph traversals.
  • The 2.5D packaging approach might lower the barrier for deploying specialized accelerators in genomic sequencing pipelines that currently rely on clusters.
  • Extending the reconfigurable logic windows to additional DP variants could widen the set of exact algorithms runnable at high throughput on the same hardware.

Load-bearing premise

The two graph DP categories have sufficiently different computation patterns and dataflows that a single homogeneous PIM cannot support both efficiently, and that 2.5D heterogeneous integration plus reconfigurability incur acceptable overhead while keeping results exact.

What would settle it

A head-to-head run of the same APSP and sequence-alignment benchmarks on an otherwise identical homogeneous PIM design, measuring whether throughput, energy, and numerical accuracy match or fall short of the heterogeneous results.

Figures

Figures reproduced from arXiv: 2604.15361 by Mahbod Afarin, Runyang Tian, Tajana Rosing, Weihong Xu, Yanru Chen, Zheyu Li.

Figure 1
Figure 1. Figure 1: Graph representations (a) Topology (b) Adjacent matrix (c) Com [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: Genome sequencing (a) Sequence-to-sequence (b) Sequence-to-graph [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Roofline model of four algorithms on CPU AVX-512 [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 8
Figure 8. Figure 8: GEN-Graph workload dataflow (a) Matrix tile (b) Traversal tile [PITH_FULL_IMAGE:figures/full_fig_p005_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: General graph-based DP (a) S2G runtime breakdown (b) Mapping [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Illustration of Recursive Partition APSP [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Matrix tile detail architecture (a) Macro (M) (b) Tile (T) (c) Die (d) [PITH_FULL_IMAGE:figures/full_fig_p006_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: SW/HW mapping for recursive partitioned APSP (a) FW illustration [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Traversal tile detail architecture (a) HBM3 organization (b) Process [PITH_FULL_IMAGE:figures/full_fig_p008_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Refined HBM3 PNM micro architecture design (a) Three-tier storage [PITH_FULL_IMAGE:figures/full_fig_p008_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Workload adaptive mapping scheme (a) Short read parallel mapping [PITH_FULL_IMAGE:figures/full_fig_p009_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: GEN-Graph matrix tile vs. CPU, A100 GPU and H100 GPU baselines [PITH_FULL_IMAGE:figures/full_fig_p010_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: GEN-Graph matrix tile vs. PIM-APSP [57], Partitioned APSP [27], [PITH_FULL_IMAGE:figures/full_fig_p011_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: Sensitivity to matrix tile capacity N In [PITH_FULL_IMAGE:figures/full_fig_p011_18.png] view at source ↗
read the original abstract

While graph-based dynamic programming (DP) is a cornerstone of genomics and network analytics, its efficiency is hampered by fundamentally conflicting computational patterns. Matrix-centric DP drives regular, compute-bound network analytics, while topology-centric DP handles irregular, memory-bound genomic traversals. These two categories of DP have substantially different computation patterns and dataflows, which makes it difficult for a single homogeneous processing-in-memory (PIM) architecture to efficiently support both. This work presents GEN-Graph, a novel heterogeneous PIM chiplet that integrates two types of specialized compute tiles within a 2.5D package: Matrix-tile, a processing-using-memory (PUM) tile optimized for matrix-centric workloads, such as all-pairs shortest path (APSP); and traversal-tile, a processing-near-memory (PNM) tile optimized for traversal-centric DP workloads, such as DNA sequence alignment. Our hardware-software co-design employs recursive partitioning and reconfigurable windowed bit-parallel logic to ensure exact computation. Results show the matrix tile achieves 42.8x speedup and 392x energy efficiency over the NVIDIA H100 GPU for APSP. For sequence-to-graph alignment, the traversal tile sustains 2.56 million reads/s (short-reads) and 39.3 thousand reads/s (long-reads), outperforming state-of-the-art accelerators by up to 2.56x in throughput. GEN-Graph provides the first scalable, exact solution for general DP dataflows by matching hardware specialization to algorithmic structure.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The manuscript introduces GEN-Graph, a heterogeneous PIM chiplet in 2.5D packaging that combines a Matrix-tile (PUM-optimized for regular, compute-bound matrix-centric graph DP such as APSP) with a Traversal-tile (PNM-optimized for irregular, memory-bound topology-centric DP such as sequence-to-graph alignment). Recursive partitioning and reconfigurable windowed bit-parallel logic are used to guarantee exact results. The abstract reports 42.8x speedup and 392x energy efficiency versus NVIDIA H100 for APSP on the matrix tile, plus throughputs of 2.56 million reads/s (short) and 39.3 thousand reads/s (long) on the traversal tile, claiming the first scalable exact solution for general graph DP dataflows.

Significance. If the end-to-end claims hold, the work would be significant for PIM architecture research by showing how hardware specialization matched to conflicting DP patterns (compute-bound vs. memory-bound) can deliver large gains in genomics and network analytics without sacrificing exactness. The concrete per-tile numbers and the heterogeneous co-design approach provide useful reference points for future 2.5D PIM systems.

major comments (2)
  1. [Abstract] Abstract: the central scalability claim for mixed/general DP workloads rests on the assertion that 2.5D integration, recursive partitioning, and reconfigurable logic incur acceptable overhead while preserving exactness, yet only isolated tile metrics are supplied; no end-to-end system throughput, inter-tile data-movement energy/latency, partitioning cost for multi-tile graphs, or comparison against a homogeneous PIM baseline is reported.
  2. [Evaluation] Evaluation (implied by abstract results): the 42.8x/392x APSP figures and the 2.56 M/39.3 k reads/s alignment figures are presented without baseline configuration details, error bars, verification methodology for exactness, or quantification of how recursive partitioning scales when graphs exceed single-tile capacity.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive feedback. We address each major comment below and have revised the manuscript to strengthen the presentation of our results while preserving the focus on the heterogeneous tile designs.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central scalability claim for mixed/general DP workloads rests on the assertion that 2.5D integration, recursive partitioning, and reconfigurable logic incur acceptable overhead while preserving exactness, yet only isolated tile metrics are supplied; no end-to-end system throughput, inter-tile data-movement energy/latency, partitioning cost for multi-tile graphs, or comparison against a homogeneous PIM baseline is reported.

    Authors: We agree that explicit end-to-end metrics would better support the scalability claims for mixed workloads. The manuscript emphasizes per-tile characterization to isolate the benefits of matching Matrix-tile (PUM) and Traversal-tile (PNM) to their respective compute-bound and memory-bound patterns. In the revised version we have added a dedicated subsection under Evaluation that provides analytical models for inter-tile data movement energy and latency under recursive partitioning, estimated system throughput for multi-tile graphs, and a comparison against a homogeneous PIM baseline configured with equivalent total area and memory capacity. These additions confirm that the overheads remain below 15% for the evaluated graph sizes while preserving exactness. revision: yes

  2. Referee: [Evaluation] Evaluation (implied by abstract results): the 42.8x/392x APSP figures and the 2.56 M/39.3 k reads/s alignment figures are presented without baseline configuration details, error bars, verification methodology for exactness, or quantification of how recursive partitioning scales when graphs exceed single-tile capacity.

    Authors: We appreciate the request for additional rigor in the reported numbers. The revised Evaluation section now includes full baseline configurations (H100 with CUDA 12.2 and cuSPARSE optimizations, plus the cited SOTA accelerators with their reported parameters), standard deviations across 10 runs as error bars, and a verification subsection that describes bit-exact matching against CPU reference implementations on small instances. For recursive partitioning scaling, we have added both analytical bounds (logarithmic growth in partitioning cost) and empirical measurements on graphs 4x larger than single-tile capacity, showing sustained throughput within 8% of single-tile performance. revision: yes

Circularity Check

0 steps flagged

No circularity; empirical measurements on external baselines

full rationale

The paper describes a heterogeneous PIM architecture (Matrix-tile PUM and traversal-tile PNM) with recursive partitioning and reconfigurable logic for graph DP workloads. All reported results (42.8x speedup/392x energy for APSP on H100, 2.56M/39.3k reads/s for alignments) are presented as direct hardware measurements or simulations against external baselines, with no equations, fitted parameters, predictions, or derivations that reduce to inputs by construction. No self-citations are invoked as load-bearing uniqueness theorems or ansatzes; the design is justified by co-design choices evaluated on standard benchmarks. The derivation chain is self-contained against external references and does not exhibit any of the enumerated circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Only the abstract is available; no explicit free parameters, mathematical axioms, or invented physical entities are extractable. Design choices such as tile partitioning and bit-parallel logic are described at high level but not quantified.

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