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arxiv: 2604.20638 · v1 · submitted 2026-04-22 · 💻 cs.AR · cs.ET

Recognition: unknown

Evaluating Computing Platforms for Sustainability: A Comparative Analysis of FPGAs against ASICs, GPUs, and CPUs

Chetan Choppali Sudarshan , Aman Arora , Vidya A Chhabria
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Pith reviewed 2026-05-09 22:54 UTC · model grok-4.3

classification 💻 cs.AR cs.ET
keywords carbon footprintsustainable computingFPGAASICGPUCPUreconfigurabilityembodied emissions
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The pith

FPGAs can be more sustainable than ASICs, GPUs, or CPUs for frequently changing low-volume workloads because reconfigurability amortizes embodied carbon across multiple uses.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper builds a model called GreenFPGA to calculate the complete carbon footprint of FPGAs, folding in emissions from design, manufacture, repeated reprogramming, operation, and end-of-life handling while treating key values as uncertain ranges. It then runs pairwise comparisons against ASICs, GPUs, and CPUs at matched performance levels for varied application types. The central result is that FPGAs produce lower total emissions when the workload set changes often and production volumes remain modest, since one physical device can serve many different tasks without new manufacturing. This matters because semiconductor production and data-center electricity already drive a large share of global emissions, so platform choice directly affects whether computing growth adds to or reduces that burden.

Core claim

GreenFPGA shows that FPGAs can be more sustainable than ASICs, GPUs, and CPUs under iso-performance assumptions whenever workloads are diverse and frequently changing and when application volumes are low; the advantage arises because embodied emissions incurred once during fabrication and design are spread across repeated reconfigurations instead of requiring separate hardware for each task.

What carries the argument

GreenFPGA, a lifetime carbon-footprint estimator that models uncertainties in design, manufacturing, reconfigurability-driven reuse, operation, disposal, testing, and recycling phases and computes total emissions for direct platform comparisons.

If this is right

  • Total carbon footprint depends strongly on application type, device lifetime, daily usage hours, and production volume.
  • Reconfigurability provides a concrete mechanism to reduce embodied emissions when the same hardware serves successive workloads.
  • Platform selection for a given workload set must weigh both operational energy and the full manufacturing-plus-disposal footprint.
  • Low-volume or rapidly evolving deployments favor FPGAs over fixed-function or general-purpose alternatives under the modeled conditions.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware procurement policies for cloud or edge fleets could shift toward reconfigurable devices when task diversity is high and replacement cycles are short.
  • The same amortization logic might apply to other reconfigurable fabrics if their manufacturing emissions are comparable.
  • Extending the model to include software development emissions or supply-chain variability would tighten the uncertainty bounds used in the comparisons.

Load-bearing premise

That performance can be matched exactly across platforms and that the chosen uncertainty ranges for carbon emissions during fabrication and reuse correctly bound real-world variation.

What would settle it

A side-by-side measurement of total carbon emissions for one FPGA reused across ten distinct applications versus ten separate ASICs each running one of those applications, all delivering the same performance, would directly test whether the modeled sustainability edge appears.

Figures

Figures reproduced from arXiv: 2604.20638 by Aman Arora, Chetan Choppali Sudarshan, Vidya A Chhabria.

Figure 1
Figure 1. Figure 1: Lifecycle of a computing platform: Highlighting the detailed embodied and operational CFP from cradle to grave. reconfigurability, allowing developers to tailor hardware to the demands of specific applications precisely. CPUs, while inherently more general-purpose than GPUs, retain a degree of flexibility that enables their deployment across a broader range of tasks. However, the differing levels of flexib… view at source ↗
Figure 2
Figure 2. Figure 2: Comparing the CFP of FPGAs vs. ASICs at iso-performance while sweeping the number of applications using a probabilistic model (box plot data), and a deterministic model [9] (line plot) [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: GreenFPGA framework, showing the required inputs, probabilistic modeling components, embodied and operational carbon models, and the resulting CFP outputs for comparative platform analysis. detailed design-phase CFP model based on industrial reports from design houses, incorporates manufacturing and packaging models from prior work [3, 4, 23], includes memory-related CFP modeling based on [3, 16, 24, 25], … view at source ↗
Figure 5
Figure 5. Figure 5: Variation in total CFP with number of applica￾tions for different 𝜆EOL rates [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: Distributions of 10nm GPA and EPA values: (a) normal GPA distribution and (b) KDE for EPA from [13] [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparing CFP of FPGAs and ASICs with 𝑁app; 𝑁vol, 𝑇i , and 𝑓use are constant [PITH_FULL_IMAGE:figures/full_fig_p013_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Comparing CFP of FPGAs and ASICs with 𝑇i ; 𝑁vol, 𝑁app, and 𝑓use are constant. 5 Evaluation of GreenFPGA 5.1 Comparing CFP of FPGAs and ASICs As noted earlier, the embodied CFP and the deployment CFP of an FPGA are higher than that of an iso-performance ASIC because the FPGA required has a larger area and consumes more power. However, FPGA reconfigurability can help amortize the embodied CFP over the opera… view at source ↗
Figure 11
Figure 11. Figure 11: Comparing CFP of FPGAs and ASICs with 𝑁vol; 𝑁app,𝑇i , and 𝑓use are constant [PITH_FULL_IMAGE:figures/full_fig_p014_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Comparing CFP of FPGAs and ASICs with 𝑓use; 𝑁app, 𝑇i , and 𝑁vol are constant [PITH_FULL_IMAGE:figures/full_fig_p014_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: CFP and its different components for the DNN domain with varying (a) 𝑁app, (b) 𝑇𝑖 , and (c) 𝑁vol. area and power of the FPGA and ASIC implementations are similar. For ImgProc, the A2F crossover is at 6 applications, and for DNN, it is at 3 applications for the CFP. (B) Impact of application lifetime: The results of this experiment where we vary application lifetime (𝑇𝑖 ) from 0.2 to 2.4 years are shown in… view at source ↗
Figure 14
Figure 14. Figure 14: Heatmaps showing the ratio of the CFP of FPGA to ASIC for the DNN application with pairwise sweeps of (a) 𝑁app and 𝑇𝑖 (b), 𝑇𝑖 and 𝑁vol, (c) 𝑁vol and 𝑁app, (d) 𝑁app and 𝑓use while keeping the other two variables constant. (D) Impact of use time fraction: For this experiment, we vary the use time fraction, 𝑓use from 0.1 to 0.9. The results of this experiment are shown in [PITH_FULL_IMAGE:figures/full_fig_p… view at source ↗
Figure 15
Figure 15. Figure 15: Comparing CFP of FPGA and GPU while varying 𝑁app for the (a) high-performance testcase, (b) energy-efficient testcase, (c) LHCb testcase, and (d) G2F crossover point for high-performance and energy-efficient testcase with 𝑁vol, 𝑇i , 𝑓use being constant [PITH_FULL_IMAGE:figures/full_fig_p016_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Comparing CFP of FPGA and GPU while varying𝑇i for (a) high-performance, (b) energy-efficient, (c) LHCb testcase with 𝑁vol, 𝑁app, 𝑓use constant, (d) F2G crossover point with different numbers of applications per GPU for energy-efficient target deployment. (A) Impact of number of applications: We vary 𝑁app between 1 and 32. Depending on the number of applications supported by the GPU, the number of GPUs req… view at source ↗
Figure 17
Figure 17. Figure 17: Comparing CFP of FPGA and GPU while varying 𝑁vol for the (a) high-performance, (b) energy-efficient target deployment, (c) LHCb testcase; 𝑁app, 𝑇i , 𝑓use are constant and (d) shows the F2G crossover point with different number of applications per GPU for high-performance and energy-efficient target deployments. (B) Impact of application lifetime: We sweep, 𝑇𝑖 from 0.2 to 2.4 years per application [PITH_F… view at source ↗
Figure 18
Figure 18. Figure 18: Comparing CFP of FPGA and GPU while varying 𝑓use for the (a) high-performance, (b) energy-efficient target deployment and (c) LHCb testcase; 𝑇i , 𝑁app, 𝑁vol are constant. 𝑁vol increases, while [PITH_FULL_IMAGE:figures/full_fig_p018_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Heatmaps of FPGA-to-GPU CFP ratio while sweeping 𝑁app and 𝑁vol for (a) GPU_2App, (b) GPU_3App, (c) GPU_4App, and (d) GPU_5App. Other variables are held constant [PITH_FULL_IMAGE:figures/full_fig_p019_19.png] view at source ↗
Figure 21
Figure 21. Figure 21: Heatmaps of FPGA-to-GPU CFP ratio while sweeping 𝑇𝑖 and 𝑁app for (a) GPU_2App, (b) GPU_3App, (c) GPU_4App, and (d) GPU_5App. Other variables are held constant [PITH_FULL_IMAGE:figures/full_fig_p019_21.png] view at source ↗
Figure 23
Figure 23. Figure 23: Comparing CFP of FPGAs and CPUs for variations in (a) 𝑁app; 𝑇i , 𝑓use, 𝑁vol are constant (b) 𝑇i ; 𝑁app, 𝑓use, 𝑁vol are constant (c) 𝑁vol; 𝑁app, 𝑓use, 𝑇i are constant (d) 𝑓use; 𝑁app, 𝑇i , 𝑁vol are constant for random number generation testcase [PITH_FULL_IMAGE:figures/full_fig_p020_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: Comparing CFP of FPGAs and CPUs for variations in (a) 𝑁app; 𝑇i , 𝑓use, 𝑁vol are constant (b) 𝑇i ; 𝑁app, 𝑓use, 𝑁vol are constant (c) 𝑁vol; 𝑁app, 𝑓use, 𝑇i are constant (d) 𝑓use; 𝑁app, 𝑇i , 𝑁vol are constant for Llama 2 testcase. (A) Impact of number of applications: We vary 𝑁app from 1 to 8. For the CPU case study, we assume that the FPGA and CPU require the same number of devices under the iso-performance … view at source ↗
Figure 25
Figure 25. Figure 25: Comparing CFP of FPGAs and CPUs for variations in (a) 𝑁app; 𝑇i , 𝑓use, 𝑁vol are constant (b) 𝑇i ; 𝑁app, 𝑓use, 𝑁vol are constant (c) 𝑁vol; 𝑁app, 𝑓use, 𝑇i are constant (d) 𝑓use; 𝑁app, 𝑇i , 𝑁vol are constant for FIR filter testcase [PITH_FULL_IMAGE:figures/full_fig_p021_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: Comparing the CFP of FPGA vs. CPU as a ratio with pairwise sweeps of (a) 𝑇i and 𝑁app, (b) 𝑁vol and 𝑇i , (c) 𝑁app and 𝑁vol, and (d) 𝑓use and 𝑁app while keeping the other two variables constant. and [PITH_FULL_IMAGE:figures/full_fig_p021_26.png] view at source ↗
Figure 27
Figure 27. Figure 27: (a) compares the probabilistic and deterministic models for ASIC vs. FPGA for the DNN application. From the deterministic model, the A2F cross point is at 3 applications, shown at the intersection of the two pink lines, whereas, from the probabilistic model curve shown in the yellow highlighted region, indicates that FPGAs already have a non-zero probability of being more sustainable than ASICs at 2 appli… view at source ↗
Figure 28
Figure 28. Figure 28: CFP for industry testcases (a) ASIC, (b) GPU, (c) CPU, and (d) FPGA. Validating absolute CFP estimates is challenging due to the coarse granularity of publicly available sustainability reports, which often aggregate impacts across entire systems and supply chains rather than isolating chip-level contributions [16]. Additionally, key parameters for accurate CFP estimation, such as design effort, yield, and… view at source ↗
read the original abstract

Climate change concerns emphasize the need for sustainable computing. Modeling the carbon footprint (CFP), including operational and embodied CFP from semiconductor use, manufacture and design, is essential. Field programmable gate arrays (FPGAs) stand out as promising platforms due to their reconfigurability across various applications, enabling the amortization of embodied CFP across multiple applications. This paper introduces GreenFPGA, a tool estimating the total CFP of FPGAs over their lifespan, considering uncertainties in CFP modeling. It accounts for CFP during design, manufacturing, reconfigurability (reuse), operation, disposal, testing, and recycling. GreenFPGA identifies deployment regimes in which FPGAs can be more sustainable than ASICs, GPUs, and CPUs under the modeled iso-performance assumptions. Experimental results highlight the importance of analyzing applications across different computing platforms to assess their CFP while varying parameters such as application type, lifetime, usage time, and volume impact their total CFP. Across the evaluated pairwise iso-performance case studies with ASICs, GPUs, and CPUs, FPGAs can be more sustainable under specific deployment regimes involving frequently changing, diverse workloads and low-volume applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces GreenFPGA, a tool for estimating the total carbon footprint (CFP) of FPGAs over their lifespan, accounting for uncertainties in design, manufacturing, reconfigurability, operation, disposal, testing, and recycling. It performs pairwise iso-performance comparisons with ASICs, GPUs, and CPUs and concludes that FPGAs can be more sustainable in regimes with frequently changing, diverse workloads and low-volume applications.

Significance. If the underlying models and assumptions prove accurate, this work could significantly influence sustainable computing practices by providing a framework to evaluate when reconfigurable platforms like FPGAs offer carbon advantages over specialized or general-purpose alternatives. The emphasis on varying parameters such as lifetime, usage time, and volume adds nuance to hardware selection for climate-conscious deployments.

major comments (2)
  1. [Abstract] Abstract: The sustainability conclusions rest on unvalidated iso-performance assumptions for the pairwise comparisons and on specific chosen uncertainty ranges for embodied CFP in design, manufacturing, reuse, and disposal phases; without shown equations, external calibration, or sensitivity bounds, the identified regimes (low-volume, frequently-changing workloads) are load-bearing on these internal parameter selections and could shift if FPGA resource overhead inflates operational CFP.
  2. [Experimental results] Experimental results section: The paper states that FPGAs can be more sustainable across the evaluated case studies but provides no validation data, real-world deployment metrics, or sensitivity analysis on how equivalent performance (throughput/latency) is maintained across platforms; this undermines the cross-platform claims if architectural differences are not fully accounted for in the CFP modeling.
minor comments (2)
  1. [Abstract] Abstract: A brief mention of the data sources or literature values used for baseline CFP estimates would improve transparency and allow readers to assess the modeling inputs.
  2. [Discussion] The manuscript would benefit from a dedicated subsection on limitations of the iso-performance assumption and how violations would quantitatively affect the sustainability thresholds.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their constructive comments. We address each major comment point-by-point below and indicate where revisions will be made.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The sustainability conclusions rest on unvalidated iso-performance assumptions for the pairwise comparisons and on specific chosen uncertainty ranges for embodied CFP in design, manufacturing, reuse, and disposal phases; without shown equations, external calibration, or sensitivity bounds, the identified regimes (low-volume, frequently-changing workloads) are load-bearing on these internal parameter selections and could shift if FPGA resource overhead inflates operational CFP.

    Authors: The iso-performance assumptions are explicitly modeled and stated as such, drawing on published benchmark data for throughput and latency equivalence across platforms. Uncertainty ranges for embodied CFP components are taken from semiconductor industry reports and prior studies, with sources cited in the methods. The GreenFPGA equations appear in Section 3 but will be made more prominent. In revision we will add the core equations to the abstract/introduction, include calibration references, and insert a sensitivity analysis subsection showing how parameter variations (including FPGA overhead effects on operational CFP) bound the low-volume and frequently-changing workload regimes. revision: yes

  2. Referee: [Experimental results] Experimental results section: The paper states that FPGAs can be more sustainable across the evaluated case studies but provides no validation data, real-world deployment metrics, or sensitivity analysis on how equivalent performance (throughput/latency) is maintained across platforms; this undermines the cross-platform claims if architectural differences are not fully accounted for in the CFP modeling.

    Authors: This is a modeling framework paper; real-world deployment metrics and new empirical validation therefore lie outside its scope. Architectural differences are accounted for through the iso-performance modeling that normalizes using established benchmark metrics. We will add a sensitivity analysis to the experimental results section that varies the performance-equivalence parameters and quantifies their effect on total CFP, thereby addressing the concern that unaccounted differences could alter the conclusions. revision: partial

standing simulated objections not resolved
  • Real-world deployment metrics or direct empirical validation data, as the manuscript is a modeling study and no new hardware experiments or deployments were performed.

Circularity Check

0 steps flagged

No circularity: sustainability regimes derived from independent CFP modeling and explicit iso-performance assumptions

full rationale

The paper introduces GreenFPGA as a new estimation tool that aggregates CFP across design, manufacturing, reuse, operation, and disposal phases while propagating stated uncertainty ranges. The central claim identifies FPGA-favorable regimes only after applying pairwise iso-performance constraints and varying external parameters (lifetime, volume, workload diversity). No equations reduce the final sustainability comparison to a fitted parameter or self-citation by construction; the iso-performance equivalence is declared as an input assumption rather than derived from the model itself. Because the derivation chain remains self-contained against external benchmarks and does not rename or smuggle prior author results as forced conclusions, the analysis exhibits no load-bearing circular steps.

Axiom & Free-Parameter Ledger

1 free parameters · 0 axioms · 0 invented entities

Abstract references uncertainties in CFP modeling and iso-performance assumptions but provides no explicit list of fitted parameters or background axioms; full paper would be needed to enumerate them.

free parameters (1)
  • CFP uncertainty parameters
    Mentioned as accounted for in the tool but no specific values or fitting process described in abstract.

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discussion (0)

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