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arxiv: 2604.23880 · v1 · submitted 2026-04-26 · 📡 eess.SP

Coordinated Multipoint Anti-jamming Beam Pattern Synthesis: From AI Accelerated Algorithm to Hardware Implementation

Zilong Wang , Cheng Zhang , Zhilei Zhang , Yaxuan Hu , Wen Wang , Yongming Huang This is my paper

Pith reviewed 2026-05-08 05:24 UTC · model grok-4.3

classification 📡 eess.SP
keywords beamforminganti-jammingcoordinated multipointdeep unfoldingneural networkhardware implementationcell-free networksFPGA
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The pith

Access points independently form anti-jamming analog beams from local angles using a deep-unfolded neural network, while the center adds digital coordination with one interaction per point.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper develops a coordinated multipoint beam pattern synthesis method that allows each access point to compute its analog beamformer locally based on angle information alone. A deep unfolding technique converts an iterative optimization step into a learnable parameter inside a complex-valued neural network, which is trained offline and run quickly online. The central processor then combines these with digital beamforming using only one round of communication per access point. Simulations demonstrate linear scaling in complexity, a 67 percent reduction in per-access-point runtime, and better jamming suppression than pure machine learning alternatives. Real hardware tests on an ARM-FPGA system and anechoic chamber measurements show the approach maintains performance despite practical imperfections.

Core claim

The paper claims that by having access points independently determine analog beamforming weights using only local angle data and a deep-unfolded neural network for fast parameter selection, while the central unit performs digital beamforming cooperatively with minimal fronthaul use, the overall system achieves linear complexity growth with the number of access points, significantly faster execution, and effective anti-jamming performance that holds up in hardware implementations.

What carries the argument

The deep unfolding-supported coordinated multipoint beam pattern synthesis (DUCoMP-BPS) scheme, where a complex-valued neural network replaces costly step-size searches in analog beamforming optimization.

If this is right

  • The computational complexity increases only linearly as more access points are added.
  • Each access point's analog beamforming computation runs about 67% faster than traditional methods.
  • Nulling of jamming signals outperforms approaches that rely entirely on data-driven neural networks.
  • Fronthaul requirements drop because only one interaction between each access point and the central unit is needed.
  • The design works on real hardware platforms like ARM-FPGA with measured beam patterns confirming robustness.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Extending this local-decision model might help in other distributed wireless systems facing similar jamming threats.
  • The hardware co-verification process could serve as a template for deploying other unfolded algorithms on embedded platforms.
  • If angle information becomes less reliable in mobile scenarios, additional sensing or adaptation layers may be needed to maintain performance.

Load-bearing premise

Local angle information available at each access point must be sufficiently accurate to support independent analog beamforming decisions that align well with the global anti-jamming goal, and the offline-trained neural network must generalize to online hardware operation without substantial loss of effectiveness.

What would settle it

Running the hardware implementation with deliberately perturbed angle estimates (for example, adding Gaussian noise of 5 degrees standard deviation) and checking whether the measured null depths in the jamming directions remain within acceptable limits compared to simulations.

Figures

Figures reproduced from arXiv: 2604.23880 by Cheng Zhang, Wen Wang, Yaxuan Hu, Yongming Huang, Zhilei Zhang, Zilong Wang.

Figure 1
Figure 1. Figure 1: Illustration of the considered CoMP CF system. view at source ↗
Figure 2
Figure 2. Figure 2: Architecture of deep unfolding RGD with hyperparameter network view at source ↗
Figure 3
Figure 3. Figure 3: The analog beam pattern of single AP (one target and one jammer). view at source ↗
Figure 4
Figure 4. Figure 4: Analog beam communication performance under jamming. view at source ↗
Figure 6
Figure 6. Figure 6: The CoMP beam pattern (one target and one jammer). view at source ↗
Figure 5
Figure 5. Figure 5: The analog beam pattern of single AP (one target and two jammers). view at source ↗
Figure 8
Figure 8. Figure 8: The CoMP beam pattern (two target and one jammer). view at source ↗
Figure 10
Figure 10. Figure 10: The complexity of proposed scheme. of neural network inference for real-time operation. These hardware-level enhancements serve as a bridge between al￾gorithmic simulation and practical field validation, thereby ensuring that the proposed scheme is both computationally efficient and ready for real-world deployment. A. Top-level Design of Hardware Platform for AI Acceleration view at source ↗
Figure 9
Figure 9. Figure 9: Anti-jamming communication performance of DUCoMP-BPS. view at source ↗
Figure 11
Figure 11. Figure 11: System-level design and hardware build. The top-level architecture of the AI acceleration platform designed in this paper is shown in view at source ↗
Figure 13
Figure 13. Figure 13: However, a divergence emerges in terms of the view at source ↗
Figure 12
Figure 12. Figure 12: Hardware mapping and acceleration design for neural network view at source ↗
Figure 13
Figure 13. Figure 13: Analog beam patterns of 5 and 3 complex linear layers. view at source ↗
Figure 14
Figure 14. Figure 14: Analog beam patterns of ARM and ARM+FPGA. view at source ↗
Figure 15
Figure 15. Figure 15: The illustration of the measurement environment. view at source ↗
Figure 17
Figure 17. Figure 17: The illustration of non-linear mapping of multi-channel phase shift. view at source ↗
Figure 18
Figure 18. Figure 18: The illustration of measured beam pattern and ideal one. view at source ↗
Figure 16
Figure 16. Figure 16: (a) The non-consistency error of antenna channel gain. (b) The non view at source ↗
read the original abstract

This paper presents a deep unfolding-supported coordinated multipoint beam pattern synthesis (DUCoMP-BPS) scheme to overcome the high complexity, poor adaptability, and limited scalability of traditional cell-free anti-jamming beamforming. In the proposed design, access points (APs) independently determine analog beamforming using local angle information, while the central processing unit (CPU) performs cooperative digital beamforming with only a single AP-CPU interaction, significantly reducing fronthaul overhead. To further improve efficiency, a deep unfolding strategy transforms the costly step size search in analog beamforming into a trainable parameter, where an offline-trained complex-valued neural network enables fast and adaptive online inference. Simulation results show that the complexity of DUCoMP-BPS scales linearly with the number of APs, reduces single-AP analog beamforming runtime by about 67% compared to conventional optimization, and achieves superior nulling performance over purely data-driven approaches. Hardware feasibility is validated on an Advanced RISC Machine-Field Programmable Gate Array (ARM-FPGA) heterogeneous platform, where algorithm-hardware co-verification and hardware-software decoupling enable efficient parallelism and low-latency execution. Finally, anechoic chamber measurements under practical hardware imperfections confirm robust beamforming performance, demonstrating the strong potential of DUCoMP-BPS for real-world deployment.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The paper proposes DUCoMP-BPS, a deep-unfolding scheme for coordinated multipoint anti-jamming beam pattern synthesis in cell-free networks. Access points independently compute analog beamforming from local angle information while the CPU performs cooperative digital beamforming with a single AP-CPU exchange. A complex-valued neural network is trained offline to replace iterative step-size search with a single learned parameter, enabling fast online inference. Simulations claim linear complexity scaling with the number of APs, a 67% reduction in single-AP analog beamforming runtime versus conventional optimization, and superior nulling over purely data-driven methods. Hardware feasibility is demonstrated on an ARM-FPGA platform with algorithm-hardware co-verification, followed by anechoic chamber measurements under practical imperfections.

Significance. If the generalization and hardware claims hold, the work offers a practical bridge between optimization-based and learning-based beamforming for anti-jamming scenarios, with the deep-unfolding step-size parameterization providing a clear complexity advantage and the ARM-FPGA plus chamber validation addressing a common gap in wireless AI papers. The linear scaling and reduced fronthaul are potentially impactful for scalable cell-free deployments.

major comments (3)
  1. [Abstract / Simulation Results] Abstract and simulation results section: the headline claims of 67% runtime reduction, linear scaling, and superior nulling are presented without error bars, training/validation dataset details, out-of-distribution test cases (angles, jammer powers), or quantitative baseline tables, making it impossible to assess whether the learned step-size parameter actually delivers the reported gains or merely reproduces the conventional optimizer.
  2. [Deep Unfolding / Hardware Implementation] Deep unfolding and hardware validation sections: the manuscript provides no information on the training distribution, validation on distribution shift, or measured simulation-to-hardware degradation for the offline-trained complex-valued network, yet the entire complexity-reduction and online-inference narrative rests on this network generalizing reliably to real-time inference and the ARM-FPGA platform.
  3. [System Model / Algorithm] System model and algorithm description: the design assumes local angle information at each AP is accurate and sufficient for fully independent analog decisions, but no sensitivity analysis or robustness test against angle estimation errors or imperfect local CSI is reported, which directly affects the claimed scalability and nulling performance.
minor comments (1)
  1. [Abstract] Abstract: the phrase 'strong potential for real-world deployment' is stated without qualifying the range of imperfections or operating conditions under which the anechoic-chamber results remain valid.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the thorough and constructive review. We have addressed each major comment below and will incorporate the suggested additions and analyses into the revised manuscript to improve clarity, reproducibility, and robustness.

read point-by-point responses

  1. Referee: [Abstract / Simulation Results] Abstract and simulation results section: the headline claims of 67% runtime reduction, linear scaling, and superior nulling are presented without error bars, training/validation dataset details, out-of-distribution test cases (angles, jammer powers), or quantitative baseline tables, making it impossible to assess whether the learned step-size parameter actually delivers the reported gains or merely reproduces the conventional optimizer.

    Authors: We agree that additional statistical and comparative details are required to substantiate the performance claims. In the revised manuscript, we will include error bars on all simulation figures, specify the training/validation dataset sizes, generation procedures, and split ratios, add out-of-distribution evaluations across varied angles and jammer powers, and provide quantitative tables comparing DUCoMP-BPS against the conventional optimizer and other baselines. These changes will allow readers to directly verify the reported runtime reduction and nulling improvements. revision: yes

  2. Referee: [Deep Unfolding / Hardware Implementation] Deep unfolding and hardware validation sections: the manuscript provides no information on the training distribution, validation on distribution shift, or measured simulation-to-hardware degradation for the offline-trained complex-valued network, yet the entire complexity-reduction and online-inference narrative rests on this network generalizing reliably to real-time inference and the ARM-FPGA platform.

    Authors: We acknowledge the need for explicit generalization analysis. The revised version will detail the training distribution (including ranges for angles, powers, and AP counts), present validation results under distribution shifts such as increased AP numbers or unseen jammer scenarios, and report quantitative simulation-to-hardware degradation metrics (e.g., beam pattern error and runtime differences) measured on the ARM-FPGA platform. This will support the claims of reliable online inference. revision: yes

  3. Referee: [System Model / Algorithm] System model and algorithm description: the design assumes local angle information at each AP is accurate and sufficient for fully independent analog decisions, but no sensitivity analysis or robustness test against angle estimation errors or imperfect local CSI is reported, which directly affects the claimed scalability and nulling performance.

    Authors: We agree that robustness to imperfect local information is essential for practical cell-free deployments. We will add a dedicated sensitivity analysis subsection that quantifies performance degradation under angle estimation errors (with varying error variances) and imperfect local CSI, including impacts on null depth and overall scalability. Simulations will demonstrate that DUCoMP-BPS maintains acceptable performance within realistic error bounds. revision: yes

Circularity Check

0 steps flagged

No significant circularity detected in the derivation chain.

full rationale

The paper derives DUCoMP-BPS by applying deep unfolding to convert iterative step-size search in analog beamforming into a single trainable parameter inside an offline-trained complex-valued neural network, then uses the resulting fast inference for independent per-AP analog decisions and cooperative digital beamforming. This structure is self-contained: the complexity scaling, runtime reduction, and nulling claims follow directly from the unfolded architecture and hardware co-design rather than any equation or parameter being defined in terms of its own output. No self-definitional mappings, fitted inputs relabeled as predictions, load-bearing self-citations, or ansatz smuggling appear in the abstract or described method; the approach retains independent content from standard optimization principles and empirical validation.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

Relies on domain assumptions about angle information availability and standard wireless channel models; introduces trainable neural network parameters via deep unfolding but no new physical entities.

free parameters (1)
  • trainable step-size parameter in unfolded network
    Deep unfolding converts the costly step size search in analog beamforming into a trainable parameter for the complex-valued neural network.
axioms (1)
  • domain assumption Local angle information at each AP is accurate and sufficient for independent analog beamforming
    Explicitly stated as the basis for APs determining analog beamforming locally with only one AP-CPU interaction for digital part.

pith-pipeline@v0.9.0 · 5549 in / 1329 out tokens · 66505 ms · 2026-05-08T05:24:35.579046+00:00 · methodology

discussion (0)

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