Recognition: unknown
A real-time demonstrator of track reconstruction with FPGAs at LHCb
Pith reviewed 2026-05-08 02:15 UTC · model grok-4.3
The pith
An FPGA prototype has processed live LHCb data for real-time track reconstruction in the VELO detector.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
The authors have built and operated a demonstrator for 30 MHz real-time tracking in the LHCb VELO detector on state-of-the-art PCIe-hosted FPGA cards connected by fast optical links. The system processes live LHCb data opportunistically during physics data taking via a dedicated TestBed facility supplied by the experiment monitoring system. It incorporates optimized high-speed data distribution across components and maintains synchronization with the most recent alignment constants needed for accurate track reconstruction.
What carries the argument
The TestBed facility that distributes live data at high speed to interconnected FPGA cards while synchronizing reconstruction with updated alignment constants.
If this is right
- Real-time tracking at the full 30 MHz rate becomes feasible with current FPGA hardware when data distribution and alignment sync are handled as described.
- The TestBed approach allows opportunistic testing on live data without interfering with standard physics data taking.
- High-speed optical links and PCIe hosting can support the data flow required for VELO reconstruction at current rates.
- Synchronization with alignment constants can be maintained in a live environment, enabling accurate reconstruction during operations.
Where Pith is reading between the lines
- Successful scaling would let LHCb move more selection decisions into the real-time stage, reducing the volume of data written to storage.
- The same architecture could be adapted to other detectors or experiments facing similar rate challenges.
- Long-term operation of the TestBed could reveal maintenance issues with firmware updates and hardware reliability under continuous load.
Load-bearing premise
The prototype's performance and alignment synchronization will continue to work when data rates and luminosity rise to the levels expected in Upgrade II.
What would settle it
Running the same system on data taken at the Upgrade II target luminosity and checking whether track-finding efficiency, latency, and alignment accuracy remain within acceptable limits.
Figures
read the original abstract
The upgraded LHCb detector has started its Run 3 of data taking in 2022, with a completely overhauled DAQ system, reading out and processing the full detector data at every LHC bunch crossing (30 MHz average rate). At the same time, an intense R&D activity is taking place, with the aim of further improving the real-time data processing performance of LHCb, in view of "Upgrade II", where luminosity will be increased. In this work, we describe the experience gained with a prototype device for a 30 MHz real-time tracking in the LHCb VELO detector, implemented in state-of-art PCIe-hosted FPGA cards interconnected by fast optical links. The system has been processing live LHCb data opportunistically during physics data taking, thanks to a dedicated TestBed facility fed by the experiment monitoring system. We describe, amongst other things, the system used to organise and optimise the high-speed distribution of data to the components, and the synchronisation with the most updated alignment constants to be used in track reconstruction.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript describes the implementation and deployment of a prototype system using interconnected PCIe-hosted FPGA cards for real-time track reconstruction in the LHCb VELO detector at the full 30 MHz bunch-crossing rate. The system has been integrated into a dedicated TestBed facility that receives data from the LHCb monitoring system and has processed live experimental data opportunistically during Run 3 physics data taking. The paper details the high-speed data distribution architecture and the mechanism for synchronizing track reconstruction with the latest alignment constants.
Significance. If the reported operation is confirmed, the work constitutes a valuable hardware demonstrator that validates FPGA-based real-time tracking under actual LHCb conditions. This provides concrete experience and architectural insights relevant to the higher data rates expected in the LHCb Upgrade II, strengthening the case for hardware acceleration in future real-time processing pipelines.
major comments (2)
- The central claim of successful live-data processing would be strengthened by quantitative metrics on tracking performance (efficiency, fake rate, latency) and any observed synchronization errors; these appear to be absent from the results or performance sections, leaving the robustness of the prototype difficult to assess independently.
- § on data distribution: the description of the high-speed optical-link distribution and buffering strategy is high-level; without explicit discussion of packet-loss rates or back-pressure handling under sustained 30 MHz input, it is hard to evaluate whether the architecture is load-bearing for the claimed real-time operation.
minor comments (2)
- The abstract and introduction would benefit from a brief statement of the total integrated luminosity or number of events processed during the opportunistic runs to give readers a sense of scale.
- Figure captions (e.g., the TestBed schematic) should explicitly label data-flow directions and clock domains to improve clarity for readers unfamiliar with the LHCb DAQ.
Simulated Author's Rebuttal
We thank the referee for the positive assessment of our work as a valuable hardware demonstrator and for the constructive comments. We address each major point below and will revise the manuscript to incorporate additional details where feasible.
read point-by-point responses
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Referee: The central claim of successful live-data processing would be strengthened by quantitative metrics on tracking performance (efficiency, fake rate, latency) and any observed synchronization errors; these appear to be absent from the results or performance sections, leaving the robustness of the prototype difficult to assess independently.
Authors: We agree that quantitative performance metrics would allow readers to better evaluate the prototype. The manuscript is structured as a system demonstrator paper whose primary focus is the successful integration and real-time operation at 30 MHz with live LHCb data rather than a full physics performance study. Detailed efficiency and fake-rate figures would require a dedicated offline comparison campaign that was outside the scope of this work. We did, however, record latency measurements for the track reconstruction pipeline and confirmed the absence of synchronization errors across all opportunistic runs. We will add a concise new subsection in the results section that reports the measured latency, notes the lack of observed synchronization issues, and describes how alignment constants are updated in real time. revision: partial
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Referee: § on data distribution: the description of the high-speed optical-link distribution and buffering strategy is high-level; without explicit discussion of packet-loss rates or back-pressure handling under sustained 30 MHz input, it is hard to evaluate whether the architecture is load-bearing for the claimed real-time operation.
Authors: We accept that the data-distribution section would benefit from greater technical detail. We will expand the relevant paragraphs to describe the buffering strategy implemented on the PCIe-hosted FPGAs, the flow-control mechanisms that manage back-pressure across the optical links, and the observed behavior under sustained 30 MHz input. In particular, we will state that no packet losses occurred during the live-data runs and that the architecture maintained continuous operation without back-pressure-induced stalls. revision: yes
Circularity Check
No significant circularity in experimental hardware demonstration
full rationale
The paper reports an implemented PCIe-hosted FPGA prototype for 30 MHz VELO tracking that processed live LHCb data via a dedicated TestBed. No derivation chain, fitted parameters, or predictions exist; the central claims rest on direct description of hardware architecture, data distribution, alignment synchronization, and opportunistic operation during physics runs. All load-bearing statements are observational or architectural rather than self-referential reductions, so the report is self-contained against external benchmarks with no circularity.
Axiom & Free-Parameter Ledger
Reference graph
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discussion (0)
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