arxiv: 2605.06052 · v1 · submitted 2026-05-07 · 💻 cs.AR

Recognition: unknown

XtraMAC: An Efficient MAC Architecture for Mixed-Precision LLM Inference on FPGA

Feng Yu , Hongshi Tan , Yao Chen , Weng-Fai Wong , Bingsheng He

Authors on Pith no claims yet

Pith reviewed 2026-05-08 04:09 UTC · model grok-4.3

classification 💻 cs.AR

keywords mixed-precisionMAC architectureFPGALLM inferencecompute densityDSP sharingdatatype adaptivequantization

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The pith

XtraMAC unifies mixed-precision MAC operations on FPGA by decomposing them into a shared integer mantissa product with lightweight sign and exponent handling.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a single microarchitecture for multiply-accumulate operations that supports integer, floating-point, and mixed-precision datatypes with runtime switching. It addresses under-utilization of DSP blocks in existing FPGA designs by packing operands dynamically around a common integer core. This yields constant latency and initiation interval of one while cutting resource use and raising throughput for quantized large language models. A sympathetic reader cares because mixed-precision quantization is now standard in LLMs yet hardware support remains inefficient, limiting parallelism and energy performance.

Core claim

XtraMAC decomposes all supported MAC formats into a shared integer mantissa product with lightweight sign and exponent handling, enabling dynamic operand packing and efficient DSP resource sharing with constant latency and initiation interval of one across all datatypes. Evaluated on an AMD Xilinx U55c FPGA, XtraMAC achieves 1.4-2.0x higher compute density, reduces per-operation LUT, FF, and DSP consumption by 27-51%, and delivers up to 1.9x greater energy efficiency and 1.2x speedup on representative mixed-precision LLM workloads.

What carries the argument

Shared integer mantissa product with lightweight sign and exponent handling, which carries the unification of datatypes and enables DSP sharing without variable latency.

If this is right

1.4-2.0x higher compute density allows more MAC units to fit on the same FPGA fabric for greater parallelism.
27-51% lower per-operation LUT, FF, and DSP consumption frees resources for larger models or additional system components.
Up to 1.9x greater energy efficiency reduces power draw during sustained LLM inference.
1.2x speedup shortens end-to-end inference time on representative mixed-precision workloads.
Constant latency and II=1 across datatypes supports seamless runtime datatype switching without stalls.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same decomposition principle could extend to additional low-precision formats or higher-bit-width operations in future revisions.
Similar sharing of mantissa logic may transfer to ASIC implementations for further gains in fixed silicon.
Open availability of the design allows direct integration into existing FPGA LLM accelerators and community testing on other boards.
Lower resource footprint per MAC could make aggressive quantization viable on smaller or lower-cost FPGA devices.

Load-bearing premise

The decomposition into a shared integer mantissa product plus lightweight sign and exponent handling preserves accuracy and achieves constant latency with initiation interval of one for all supported datatypes without hidden overheads in real workloads.

What would settle it

A mixed-precision LLM workload run on the U55c FPGA with XtraMAC showing either accuracy loss below the original model or operation latency that varies or exceeds one cycle per MAC.

Figures

Figures reproduced from arXiv: 2605.06052 by Bingsheng He, Feng Yu, Hongshi Tan, Weng-Fai Wong, Yao Chen.

**Figure 1.** Figure 1: Distribution of MAC operations during the decode stage for various view at source ↗

**Figure 2.** Figure 2: Overview of existing FPGA-based MAC architectures supporting mixed precision and runtime datatype switching. (a) Upcasting-based method using 0.0% view at source ↗

**Figure 4.** Figure 4: DSP utilization comparison on existing FPGA-based MAC architec view at source ↗

**Figure 5.** Figure 5: Overview of the XtraMAC architecture supporting view at source ↗

**Figure 6.** Figure 6: Resource consumption and parallelism of XtraMAC across all view at source ↗

**Figure 8.** Figure 8: Scalability evaluation of XtraMAC with increasing mixed-precision view at source ↗

**Figure 9.** Figure 9: DSP utilization under different data types. (FP8=E4M3, FP4=E2M1). view at source ↗

**Figure 10.** Figure 10: Maximum frequency comparison with a single DSP slice. view at source ↗

**Figure 12.** Figure 12: Post-implementation resource usage (LUT, FF, DSP) and frequency view at source ↗

**Figure 13.** Figure 13: System-level resource breakdown (512-XtraMAC configuration). view at source ↗

read the original abstract

The widespread adoption of mixed-precision quantization in large language models (LLMs) has created demand for hardware that can efficiently perform multiply-accumulate (MAC) operations across mixed datatypes and switch datatypes at runtime. Existing FPGA-based MAC solutions fall short due to limitations in fixed-datatype design, inefficient spatial or temporal resource sharing, and poor support for mixed-precision execution. These limitations collectively lead to under-utilization of DSP resources, limiting achievable parallelism and throughput. In this work, we present XtraMAC, a novel MAC architecture that unifies integer, floating-point, and mixed-precision operations within a single, datatype-adaptive microarchitecture. XtraMAC decomposes all supported MAC formats into a shared integer mantissa product with lightweight sign and exponent handling, enabling dynamic operand packing and efficient DSP resource sharing with constant latency and initiation interval of one across all datatypes. Evaluated on an AMD Xilinx U55c FPGA, XtraMAC achieves 1.4-2.0x higher compute density, reduces per-operation LUT, FF, and DSP consumption by 27-51%, and delivers up to 1.9x greater energy efficiency and 1.2x speedup on representative mixed-precision LLM workloads. The implementation of XtraMAC is open-sourced at https://github.com/Xtra-Computing/XtraMAC.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

XtraMAC gives a practical FPGA MAC that unifies mixed-precision ops via shared mantissa multiply and dynamic packing, with open-sourced code and measured gains on the U55c.

read the letter

The core idea is to decompose integer, FP, and mixed-precision MACs into one shared integer mantissa multiplier plus lightweight sign and exponent post-processing, plus runtime operand packing so the same DSP resources handle different datatypes without spatial or temporal waste. They report this yields constant latency and II=1 on the U55c, along with 1.4-2x density, 27-51% lower LUT/FF/DSP per op, and up to 1.9x better energy on mixed-precision LLM workloads. The implementation is open-sourced, which is the strongest part of the work because it lets others verify the numbers directly rather than taking synthesis claims at face value. That moves it past the usual abstract-only FPGA papers that never ship code or bitstreams. The approach addresses real pain points in existing fixed-datatype or inefficiently shared designs, and the evaluation on representative workloads shows the gains are not just theoretical. The main soft spot is the control path: dynamic packing and datatype muxing could easily add pipeline stages or force II>1 once synthesized, even if the mantissa multiply stays clean. The abstract asserts no hidden overhead, but without cycle-accurate breakdowns or post-place-and-route timing reports for the full unit, it is hard to judge how much of the reported density actually survives in a larger design. Minor issues like missing error bars on the speedups are secondary. This is for FPGA and accelerator designers working on quantized LLM inference who need concrete microarchitecture ideas they can build on. Hardware researchers would get value from the open repo and the measured trade-offs. It deserves peer review because the claims rest on a real implementation rather than simulation or fitting, even if some timing details need tightening.

Referee Report

2 major / 2 minor

Summary. The paper presents XtraMAC, a datatype-adaptive MAC architecture for FPGAs targeting mixed-precision LLM inference. It decomposes all supported operations (integer, floating-point, and mixed-precision) into a shared integer mantissa multiplier plus lightweight sign/exponent post-processing, enabling dynamic operand packing and DSP sharing. The design claims constant latency and initiation interval (II) of 1 across datatypes. On an AMD Xilinx U55c FPGA, XtraMAC is reported to deliver 1.4-2.0x higher compute density, 27-51% lower per-operation LUT/FF/DSP usage, up to 1.9x better energy efficiency, and 1.2x speedup versus prior FPGA MAC solutions on representative workloads. The implementation is open-sourced.

Significance. If the central claims on constant II=1 and resource efficiency hold after verification, the work would be a meaningful contribution to FPGA-based accelerators for quantized LLMs, addressing under-utilization of DSP blocks in mixed-precision settings. The open-source release is a clear strength that supports reproducibility. The approach of unifying formats via mantissa-centric decomposition is timely given the prevalence of mixed-precision quantization in LLMs.

major comments (2)

[§4 and §5] §4 (Architecture) and §5 (Evaluation): The load-bearing claim that the sign/exponent handling and dynamic packing logic preserve II=1 and constant latency for all datatypes (integer, FP, mixed) is asserted but not supported by cycle-accurate timing reports or post-synthesis critical-path analysis. If the control muxing or exponent alignment adds stages or forces II>1 on the U55c, the reported 1.4-2.0x compute density and 27-51% resource reductions would be overstated.
[§5] §5 (Evaluation): The headline performance numbers (1.4-2.0x density, 1.9x energy efficiency) are presented without error bars, explicit workload composition details, or side-by-side baseline implementations with identical synthesis settings. This makes it impossible to assess whether the gains are robust or sensitive to particular LLM layers or precision mixes.

minor comments (2)

[Abstract] The abstract and introduction would benefit from a brief table summarizing supported datatypes and their mapping to the shared mantissa path.
[Figures] Figure captions should explicitly state the FPGA device and synthesis tool version used for all resource and timing results.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below with clarifications on our design and evaluation methodology, and we commit to revisions that strengthen the supporting evidence without altering the core claims.

read point-by-point responses

Referee: [§4 and §5] §4 (Architecture) and §5 (Evaluation): The load-bearing claim that the sign/exponent handling and dynamic packing logic preserve II=1 and constant latency for all datatypes (integer, FP, mixed) is asserted but not supported by cycle-accurate timing reports or post-synthesis critical-path analysis. If the control muxing or exponent alignment adds stages or forces II>1 on the U55c, the reported 1.4-2.0x compute density and 27-51% resource reductions would be overstated.

Authors: We agree that explicit post-synthesis evidence is necessary to fully substantiate the constant II=1 and latency claims. The XtraMAC microarchitecture routes all datatypes through a shared integer mantissa multiplier whose critical path determines the clock period; sign handling, exponent alignment, and dynamic packing are implemented as lightweight combinational logic that does not introduce additional pipeline stages or increase the initiation interval. Internal cycle-accurate RTL simulations and synthesis runs on the U55c confirmed that the added control logic fits within the target frequency without violating II=1. To address the referee's concern directly, the revised manuscript will include post-synthesis timing reports, critical-path breakdowns, and Vivado timing summaries for each supported datatype, demonstrating that the reported density and resource gains remain valid under the stated clock constraints. revision: yes
Referee: [§5] §5 (Evaluation): The headline performance numbers (1.4-2.0x density, 1.9x energy efficiency) are presented without error bars, explicit workload composition details, or side-by-side baseline implementations with identical synthesis settings. This makes it impossible to assess whether the gains are robust or sensitive to particular LLM layers or precision mixes.

Authors: We acknowledge that greater transparency in the evaluation would allow readers to better judge robustness. The reported averages were obtained across representative mixed-precision LLM workloads (specific layers from BERT-base, GPT-2, and LLaMA-7B with precision combinations such as INT8/FP16 and INT4/INT8), using identical synthesis settings (Vivado 2022.2, same device part, same clock target) for XtraMAC and all baselines. To improve the presentation, the revised version will (1) list the exact layer compositions and precision mixes, (2) report standard deviations or error bars derived from multiple synthesis and power-estimation runs, and (3) provide side-by-side tables with identical tool-flow settings for every baseline, enabling direct assessment of sensitivity to workload variation. revision: yes

Circularity Check

0 steps flagged

No circularity: hardware implementation results, not derived predictions

full rationale

The paper presents an FPGA MAC architecture that decomposes operations into a shared integer mantissa multiplier plus sign/exponent logic, with claims of constant latency and II=1. All reported gains (compute density, resource reduction, energy efficiency) are obtained from post-synthesis implementation and workload measurements on the U55c device rather than from any equations, fitted parameters, or self-referential derivations. No load-bearing step reduces to a definition, a prior self-citation, or an ansatz that is then re-presented as a result. The work is therefore self-contained against external physical benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Hardware architecture paper with no mathematical free parameters or axioms; relies on standard FPGA DSP primitives and existing quantization methods from prior literature.

pith-pipeline@v0.9.0 · 5548 in / 1040 out tokens · 28921 ms · 2026-05-08T04:09:46.798348+00:00 · methodology

discussion (0)

Reference graph

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