Integrity report for Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation

A machine-verified record of the checks Pith has run against this paper: detector runs, findings, signed bundle events, and canonical identifiers.

arXiv:2605.08725

0Critical

0Advisory

4Detectors run

2026-05-20Last checked

Paper page arXiv integrity.json

Detector runs

claim_evidence completed v1.0.0 · findings 0 · 2026-05-20 09:02:01.950013+00:00

ai_meta_artifact completed v1.0.0 · findings 0 · 2026-05-19 22:35:41.689873+00:00

doi_title_agreement completed v1.0.0 · findings 0 · 2026-05-19 14:31:17.622069+00:00

doi_compliance completed v1.0.0 · findings 0 · 2026-05-19 10:50:52.799502+00:00

Findings

No public integrity findings for this paper.

Signed record

The machine-readable record for this paper lives at /pith/2605.08725/integrity.json. Pith Number bundles also include signed pith.integrity.v1 events where a Pith Number exists.