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arxiv: 2605.18515 · v1 · pith:JEWWJRSZnew · submitted 2026-05-18 · 💻 cs.DC

CB-SpMV:A Data Aggregating and Balance Algorithm for Cache-Friendly Block-Based SpMV on GPUs

Xing Cong , Fukai Sun , Yifan Chen , Chenhao Xie* , Yi Liu , Depei Qian This is my paper

Pith reviewed 2026-05-20 08:15 UTC · model grok-4.3

classification 💻 cs.DC
keywords sparse matrix-vector multiplicationGPU optimizationcache localityload balancing2D blockingdata aggregationperformance acceleration
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The pith

A 2D blocking structure with virtual pointer aggregation and load balancing raises cache hit rates and delivers up to 3.95x speedup for SpMV on GPUs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents CB-SpMV as a way to reorganize sparse matrices for better performance during matrix-vector multiplication on graphics processors. It splits the matrix into independent sub-blocks, then uses virtual pointers to collect related data inside each block so that fast cache memory holds it longer. Block-aware column grouping and format choices adapt the computation to different sparsity patterns, while a separate balancing step spreads work evenly across thread blocks. If these steps work as described, many repeated SpMV calls in science and machine learning would finish in less time on current NVIDIA hardware without changes to the underlying matrix data.

Core claim

The paper claims that dividing the input matrix into independent sub-blocks, aggregating intra-block data of different types through virtual pointers to raise cache-level locality, applying block-aware column aggregation together with per-sub-block format selection to improve hardware use, and adding an inter-block load-balancing algorithm produces markedly higher cache hit rates and average speedups reaching 3.95 times over existing libraries when measured across 2,843 matrices from the SuiteSparse Collection on A100 and RTX 4090 GPUs.

What carries the argument

An adaptable 2D blocking structure that supports virtual pointer aggregation of intra-block data and enables block-aware column aggregation plus inter-block load balancing.

If this is right

  • Higher cache hit rates directly shorten the time spent fetching matrix and vector entries from slower memory levels.
  • Per-block format selection lets the same code handle both very sparse and denser local regions without manual retuning.
  • Even distribution of work across thread blocks reduces idle time on the GPU during each multiplication.
  • The resulting faster SpMV kernels accelerate any larger computation that repeatedly calls matrix-vector multiplication.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same aggregation and balancing ideas could be tested on other memory-intensive GPU routines such as sparse matrix-matrix multiplication.
  • Library developers might adopt similar virtual-pointer layouts as a default storage option for sparse data on GPUs.
  • Gains are likely largest for matrices from graph or finite-element applications whose local structure matches the block assumptions.
  • The open code release makes it straightforward to measure whether the speedups hold on future GPU generations with different cache sizes.

Load-bearing premise

The 2D blocking, virtual pointer aggregation, column strategies, and balancing steps will improve cache use and hardware efficiency for most sparse matrix patterns without adding offsetting overheads that erase the gains.

What would settle it

Running CB-SpMV on a fresh collection of matrices whose sparsity patterns differ markedly from the SuiteSparse set and recording no rise in cache hit rate or no net reduction in runtime compared with current libraries.

Figures

Figures reproduced from arXiv: 2605.18515 by Chenhao Xie*, Depei Qian, Fukai Sun, Xing Cong, Yifan Chen, Yi Liu.

Figure 1
Figure 1. Figure 1: (a) illustrates a 16×16 example matrix divided into 4×4 sub-blocks, with 13 non-zero sub-blocks highlighted. (b) depicts the data layout of the matrix in GPU global memory across four sparse storage formats (CSR, COO, BSR, TileSpMV), along with the memory access patterns for retrieving the third non-zero element located at (0,4) in the example matrix. case of highly sparse sub-blocks. For instance, when a … view at source ↗
Figure 2
Figure 2. Figure 2: An example of an SpMV that multiplies a 6-by-6 sparse matrix 𝐴 by a vector 𝑥 to get a vector 𝑦. 2 Background, Motivation and Challenge 2.1 Sparse Matrix Storage Format Sparse matrices, characterized by a few non-zero elements per row, require specialized storage formats to improve access efficiency. The COO format is widely used for its simplicity and compatibility with data storage, stores non-zero elemen… view at source ↗
Figure 4
Figure 4. Figure 4: Standard deviation and distribution of non-zero elements per thread block: (a) Standard deviation across 2000 matrices; (b) Distribution for a specific matrix (TSC_OPF_1047.mtx). that 59.36% of sub-blocks have a warp-level thread utilization below 75%, while 20.35% falls below 50%, leading to significant efficiency losses. Although TileSpMV[39] partially addresses this by consoli￾dating sparse sub-blocks a… view at source ↗
Figure 6
Figure 6. Figure 6: The storage format and memory organization of CB-SpMV. (a) illustrates a 16-by-16 example matrix, where different colors indicate that sub-blocks adopt distinct storage formats. (b) depicts the matrix after column aggregation. (c) shows the 2D metadata of CB-SpMV. In comparison, CB-SpMV aggregates different types of data within the sub-block for better data locality. As shown in Fig.5, the overview flow ch… view at source ↗
Figure 7
Figure 7. Figure 7: Sub-block Data Transfer and GPU Memory Access: (a) Packaging of sub-block data on the CPU, transfer to GPU global memory, and access via L1, L2 caches, and shared memory; (b) Mem￾ory alignment issue and its resolution. specify the storage format of each sub-block. The low-level struc￾ture defaults to the COO format for rapid conversion from the input data to the CB-SpMV structure. To treat the different ty… view at source ↗
Figure 8
Figure 8. Figure 8: Block level load balancing policy and high-level structure after balancing 3.3.2 Dense Sub-blocks. For excessively dense sub-blocks, CB￾SpMV employs a format selection strategy, storing sub-blocks in one of three formats: COO for low-density blocks(the number of non-zero elements in a block is less than 𝑡ℎ1), Dense for high￾density blocks(the number of non-zero elements in a block is more than 𝑡ℎ2), and CS… view at source ↗
Figure 9
Figure 9. Figure 9: Performance comparison between CB-SpMV and the SOTA SpMV algorithm on RTX4090 and A100 GPUs [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Performance comparison of 15 typical sparse matrices on RTX 4090 GPU and L1 & L2 Cache hit ratio lts__t_request_hit_rate for L2 Cache hit rate. These metrics were used to evaluate the Gflops and average L1 and L2 cache hit rates for the three methods mentioned earlier when applied to these 15 matrices. As shown in Fig.10, CB-SpMV achieves L1 cache hit rates 14.4× and 1.93× higher than BSR and TileSpMV, re… view at source ↗
Figure 11
Figure 11. Figure 11: Performance comparison of 15 typical sparse matrices using different optimization measures using CB-SpMV on RTX 4090 GPUs [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Comparison of memory usage and preprocessing time across different SpMV storage formats. This demonstrates that CB-SpMV effectively balances storage effi￾ciency and computational adaptability. 4.4.2 preprocessing time overhead. The preprocessing time re￾quired to convert COO matrices into the formats used by various algorithms is shown in Fig.12(b). CB-SpMV consistently outper￾forms TileSpMV and cuSPARSE-… view at source ↗
read the original abstract

Sparse matrix-vector multiplication (SpMV) is crucial in computational science, engineering, and machine learning. Despite substantial efforts to improve SpMV performance on GPUs through various techniques, issues related to data locality, hardware utilization, and load balancing persist, leaving room for further optimization. This paper presents CB-SpMV, a cache-friendly SpMV optimization algorithm, using a novel data convergent and adaptable 2D blocking structure. The matrix in CB-SpMV is divided into independent sub-blocks, with virtual pointers aggregating different types of intra-block data for better cache-level data locality. To enhance hardware utilization, a block-aware column aggregation strategy and the selection of sub-block formats are proposed to accelerate computation and adapt to varying sparse matrices. Finally, an inter-block load-balancing algorithm is designed to ensure efficient workload distribution across thread blocks. Experimental evaluations on 2,843 matrices from the SuiteSparse Collection show that CB-SpMV significantly improves cache hit rates and achieves average speedups of up to 3.95x over state-of-the-art methods like cuSPARSE-BSR, TileSpMV, and DASP on NVIDIA A100 and RTX 4090 GPUs. The implementation is available at: \url{https://github.com/xing-cong/CB-Sparse}.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents CB-SpMV, a GPU SpMV algorithm that partitions the matrix into independent sub-blocks using a novel 2D blocking structure, aggregates intra-block data via virtual pointers to improve cache locality, applies block-aware column aggregation and sub-block format selection to boost hardware utilization, and incorporates an inter-block load-balancing algorithm. Experiments on 2,843 SuiteSparse matrices report improved cache hit rates and average speedups of up to 3.95× over cuSPARSE-BSR, TileSpMV, and DASP on NVIDIA A100 and RTX 4090 GPUs, with the implementation released on GitHub.

Significance. If the performance claims are substantiated, the work would represent a useful incremental advance in cache- and load-aware SpMV kernels for GPUs, a core primitive in scientific computing and machine learning. The open-source release supports reproducibility and follow-on work. The significance hinges on demonstrating that the proposed aggregation and blocking mechanisms deliver net gains without material offsetting costs across diverse sparsity patterns.

major comments (2)
  1. [Experimental Evaluation] Experimental Evaluation section: The reported speedups on 2,843 SuiteSparse matrices lack any description of selection criteria, post-hoc exclusions, variance or error-bar computation, or confirmation that baseline libraries (cuSPARSE-BSR, TileSpMV, DASP) were compiled and preprocessed under identical conditions. These omissions make it impossible to assess whether the 3.95× average speedup is robust or sensitive to matrix subset choice.
  2. [Experimental Evaluation] Experimental Evaluation section: No ablation studies or micro-benchmarks isolate the incremental cache-hit and runtime contributions (or overheads) of virtual-pointer aggregation, block-aware column aggregation, and sub-block format selection versus a plain blocked baseline or the inter-block load balancer alone. Without such isolation, the central claim that the cache-friendly 2D structures are the primary driver of the observed gains cannot be verified and may be confounded by the load balancer.
minor comments (2)
  1. [Abstract] Abstract: The phrasing 'average speedups of up to 3.95x' is ambiguous; clarify whether this is the mean of per-matrix speedups or the maximum observed average across baselines.
  2. [Algorithm Description] Notation throughout: Define the precise meaning of 'virtual pointer' and 'sub-block format selection' on first use, and ensure consistent terminology between the algorithmic description and the experimental figures.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and have revised the Experimental Evaluation section to improve transparency and strengthen the supporting evidence for our claims.

read point-by-point responses

  1. Referee: Experimental Evaluation section: The reported speedups on 2,843 SuiteSparse matrices lack any description of selection criteria, post-hoc exclusions, variance or error-bar computation, or confirmation that baseline libraries (cuSPARSE-BSR, TileSpMV, DASP) were compiled and preprocessed under identical conditions. These omissions make it impossible to assess whether the 3.95× average speedup is robust or sensitive to matrix subset choice.

    Authors: We appreciate the referee's emphasis on rigorous experimental reporting. The 2,843 matrices comprise the full subset of SuiteSparse matrices with at least 1,000 non-zeros that fit in GPU memory on the evaluated platforms; no post-hoc exclusions were applied. All timing results are deterministic for a given matrix, hardware, and kernel launch configuration, which is why per-matrix variance was not originally reported. We confirm that cuSPARSE-BSR, TileSpMV, and DASP were compiled with identical CUDA toolchains, optimization flags, and preprocessing pipelines. In the revised manuscript we have added an explicit subsection describing the selection criteria, the use of geometric means for aggregation, and per-category standard deviations to allow readers to assess robustness across sparsity patterns. revision: yes

  2. Referee: Experimental Evaluation section: No ablation studies or micro-benchmarks isolate the incremental cache-hit and runtime contributions (or overheads) of virtual-pointer aggregation, block-aware column aggregation, and sub-block format selection versus a plain blocked baseline or the inter-block load balancer alone. Without such isolation, the central claim that the cache-friendly 2D structures are the primary driver of the observed gains cannot be verified and may be confounded by the load balancer.

    Authors: The referee correctly notes that component-wise isolation would further substantiate our central claim. While the original results already link the observed cache-hit-rate improvements directly to the 2D blocking and aggregation mechanisms, we agree that explicit ablations reduce the possibility of confounding. We have therefore added a new set of micro-benchmark experiments in the revised manuscript. These compare (i) a plain blocked baseline, (ii) the inter-block load balancer alone, and (iii) incremental addition of virtual-pointer aggregation, block-aware column aggregation, and sub-block format selection. The new data show that the cache-friendly 2D structures account for the majority of the performance and locality gains, with the load balancer providing complementary but smaller additional benefits. revision: yes

Circularity Check

0 steps flagged

No circularity: algorithmic construction with independent empirical benchmarks

full rationale

The paper introduces a 2D blocking structure, virtual pointer aggregation, block-aware column aggregation, sub-block format selection, and inter-block load balancing as explicit algorithmic design choices for cache-friendly SpMV. These mechanisms are described directly in the manuscript without reference to fitted parameters, self-citations that bear the central claim, or uniqueness theorems imported from prior author work. Performance results are reported as measured speedups and cache-hit improvements on 2,843 SuiteSparse matrices against external baselines (cuSPARSE-BSR, TileSpMV, DASP), with no equations equating outputs to quantities defined by the authors' own inputs. The derivation chain consists of engineering decisions followed by external validation and is therefore self-contained.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The paper introduces no new physical constants or mathematical axioms; it relies on standard GPU memory hierarchy assumptions and the existence of the SuiteSparse matrix collection. No free parameters are explicitly fitted in the abstract description.

axioms (1)
  • domain assumption GPU cache behavior and thread-block scheduling follow the documented NVIDIA architecture rules for the A100 and RTX 4090.
    Invoked implicitly when claiming improved cache hit rates and load balance.

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Reference graph

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