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arxiv: 2605.25522 · v1 · pith:GVYTPYMInew · submitted 2026-05-25 · 💻 cs.AR

Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory

Sitian Chen , Yusen Li , Yao Chen , Minwen Deng , Jintao Meng , Amelie Chi Zhou This is my paper

Pith reviewed 2026-06-29 19:48 UTC · model grok-4.3

classification 💻 cs.AR
keywords approximate nearest neighbor searchprocessing-in-memorygraph-based indexingbillion-scale datasetsalgorithm-architecture co-designhigh-recall searchmemory-bound workloads
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The pith

Co-design of compacted index layout, pipelined scheduler, and multiplication-free kernel enables efficient graph-based ANNS on PIM at billion scale.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tries to establish that graph-based approximate nearest neighbor search, a memory-bound workload central to AI systems, can be adapted to processing-in-memory hardware by addressing its architectural mismatches. It does this via a compacted index that shrinks the memory footprint by 14.5x, an asynchronous pipelined scheduler that saturates the interconnect, and a multiplication-free distance kernel that holds recall loss below 0.08 percent. If these hold, the design delivers substantially higher throughput than CPUs, GPUs, or earlier PIM approaches while scaling to multi-node setups. A sympathetic reader would care because current hardware hits bandwidth walls on billion-scale indexes, and PIM offers internal bandwidth that could change what large-scale search is practical.

Core claim

The central claim is that the three-component co-design overcomes PIM limitations of small local memories, costly inter-unit communication, host coordination overhead, and weak in-memory compute units. The compacted index layout shrinks the PIM-resident footprint by 14.5x. The asynchronous pipelined scheduler keeps the host-to-PIM interconnect saturated. The multiplication-free distance kernel loses under 0.08 percent recall. On three billion-scale benchmarks this yields up to 20x and 17.1x higher throughput than CPU and GPU baselines, 129x over prior PIM accelerators in the high-recall regime, and graceful scaling across multi-node deployments and emerging PIM architectures.

What carries the argument

The algorithm-architecture co-design of compacted index layout, asynchronous pipelined scheduler, and multiplication-free distance kernel.

If this is right

  • Achieves up to 20x higher throughput than CPU baselines on billion-scale benchmarks.
  • Delivers up to 17.1x higher throughput than GPU baselines.
  • Outperforms prior PIM accelerators by 129x in the high-recall regime.
  • Scales gracefully across multi-node deployments and emerging PIM architectures.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The multiplication-free kernel may reduce energy use in other memory-bound similarity tasks beyond ANNS.
  • Future PIM hardware could add native support for irregular graph traversals based on the mismatches identified here.
  • The compacted layout technique might extend to other graph algorithms that suffer from high memory footprint on PIM.

Load-bearing premise

The three components overcome PIM architectural mismatches of small local memory, costly communication, host overhead, and weak compute units without introducing new performance or accuracy bottlenecks.

What would settle it

Running the full design on physical PIM hardware for the three billion-scale benchmarks and measuring whether throughput reaches the reported multiples over CPU, GPU, and prior PIM baselines while recall loss stays below 0.08 percent.

Figures

Figures reproduced from arXiv: 2605.25522 by Amelie Chi Zhou, Jintao Meng, Minwen Deng, Sitian Chen, Yao Chen, Yusen Li.

Figure 1
Figure 1. Figure 1: Roofline Analysis of graph-based ANNS on SIFT. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Query processing with greedy beam search. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Commodity PIM architecture. on optimizing the query execution path, as it dominates end￾to-end ANNS performance, while treating index construction as an offline preprocessing step. By aggressively reducing the cost of distance computation, modern graph-based ANNS algorithms shift their performance bottleneck toward memory access and graph traversal, as confirmed by the roofline analysis in [PITH_FULL_IMAG… view at source ↗
Figure 4
Figure 4. Figure 4: Overview of PIMCQG local memory capacity (C1) forces aggressive graph par￾titioning, which in turn amplifies inter-PU communication during traversal (C2). High communication overhead exacer￾bates coordination costs and load imbalance across PUs (C3), while restricted PU compute capability (C4) further constrains the choice of distance computation and pruning strategies that could otherwise mitigate these e… view at source ↗
Figure 5
Figure 5. Figure 5: Index structure of SymphonyQG and PIMCQG [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 8
Figure 8. Figure 8: Comparison of Host-PU collaboration strategy. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: Comparison of different scheduling strategies. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Recall of PIMCQG using node-specific cos(θ) or fixed α on SIFT. value has a convenient binary representation, 1.012, which translates directly into efficient bitwise operations: x · 1.25 ≈ x+(x >> 2). When a specific dataset or cluster deviates from this default, α is calibrated during index construction to the nearest hardware-friendly binary-shift equivalent. As a result, the expensive floating-point sca… view at source ↗
Figure 10
Figure 10. Figure 10: QPS vs. recall@10 of compared baselines. Each point is obtained by varying the search-cluster count and [PITH_FULL_IMAGE:figures/full_fig_p008_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Energy efficiency (QPS/W) vs. recall@10 for the compared baselines across three datasets. [PITH_FULL_IMAGE:figures/full_fig_p008_11.png] view at source ↗
Figure 14
Figure 14. Figure 14: Performance breakdown. The overall execution time [PITH_FULL_IMAGE:figures/full_fig_p009_14.png] view at source ↗
Figure 16
Figure 16. Figure 16: Throughput compar￾ison of different scheduling strategies SIFT1B SPACEV1B SSN1B 0.00 0.05 0.10 0.15 Time (s) -60.4% -60.8% -49.6% w/o MF w/ MF [PITH_FULL_IMAGE:figures/full_fig_p010_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: Multi-node scalability of PIMCQG on SIFT1B. UPMEM PIM-HBM AiM 10 0 10 1 10 2 Speedup vs CPU vs GPU [PITH_FULL_IMAGE:figures/full_fig_p010_18.png] view at source ↗
read the original abstract

Approximate Nearest Neighbor Search (ANNS) is a core primitive in modern AI systems, and graph-based methods currently offer the best accuracy-efficiency trade-off at scale. The workload is fundamentally memory-bound: graph traversal produces frequent, irregular memory accesses that cap CPU throughput at main-memory bandwidth, while GPUs lack the high-bandwidth memory capacity to host billion-scale indexes. Processing-in-Memory (PIM) is a natural candidate, as placing computation next to data unlocks the abundant internal bandwidth that such bandwidth-starved workloads demand. Porting graph-based ANNS to PIM, however, exposes several architectural mismatches: each processing unit has only a small local memory, inter-unit communication is costly, host coordination adds overhead, and in-memory compute units are relatively weak -- limitations that have forced prior PIM-based ANNS designs to fall back on cluster-based indexing, whose recall ceiling is far below that of graph methods. This paper presents an algorithm-architecture co-design that overcomes these obstacles through three components: a compacted index layout that shrinks the PIM-resident memory footprint by 14.5x; an asynchronous pipelined scheduler that keeps the host-to-PIM interconnect saturated; and a multiplication-free distance kernel that loses under 0.08% recall. Across three billion-scale benchmarks, the proposed design achieves up to 20x and 17.1x higher throughput than CPU and GPU baselines, respectively, outperforms prior PIM accelerators by 129x in the high-recall regime, and scales gracefully across multi-node deployments and emerging PIM architecture.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 1 minor

Summary. The manuscript presents a co-design for graph-based ANNS on PIM at billion scale. It proposes three components to address PIM architectural mismatches: a compacted index layout that reduces the memory footprint by 14.5x, an asynchronous pipelined scheduler to keep the host-to-PIM interconnect saturated, and a multiplication-free distance kernel that incurs less than 0.08% recall loss. The design is evaluated on three billion-scale benchmarks, claiming up to 20x higher throughput than CPU baselines, 17.1x over GPU, and 129x over prior PIM accelerators in the high-recall regime, with graceful scaling in multi-node and emerging PIM setups.

Significance. If the empirical results are robust, this work is significant as it demonstrates how to adapt high-accuracy graph ANNS to PIM hardware, overcoming limitations that previously forced lower-recall cluster-based methods. The throughput gains are substantial for a memory-bound workload, and the co-design approach could influence future PIM software-hardware co-optimization for irregular access patterns in AI systems. The paper provides concrete numbers and addresses scaling, which strengthens the contribution.

minor comments (1)
  1. [Abstract] Abstract: The abstract states specific quantitative claims (20x, 17.1x, 129x throughput; 14.5x footprint; 0.08% recall) without referencing the corresponding evaluation sections, figures, or tables. The manuscript should cross-reference these claims to the experimental results to facilitate verification.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the positive assessment of our work on co-designing graph-based ANNS for PIM at billion scale, including recognition of the 14.5x compacted index, asynchronous scheduler, and multiplication-free kernel, as well as the throughput gains and scaling results. The recommendation for minor revision is noted, and we will address any editorial or minor issues in the revised manuscript.

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper presents an empirical hardware-software co-design for graph-based ANNS on PIM hardware. It reports measured throughput and recall numbers from three billion-scale benchmarks without any equations, derivations, fitted parameters renamed as predictions, or self-citation chains that reduce the central claims to inputs by construction. The three components (compacted index, pipelined scheduler, multiplication-free kernel) are described as engineering solutions whose performance is validated externally against CPU/GPU baselines and prior PIM designs; none of the load-bearing results are shown to be tautological or self-referential. This is the expected outcome for a systems paper whose contributions are implementation and measurement rather than mathematical derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on domain assumptions about PIM hardware properties and graph ANNS workload characteristics; no free parameters or invented entities are identifiable from the abstract.

axioms (1)
  • domain assumption PIM units have only small local memory, costly inter-unit communication, weak compute, and host coordination overhead that prior designs could not overcome with graph methods.
    Explicitly listed in the abstract as the architectural mismatches that forced prior PIM ANNS designs to use lower-recall cluster indexing.

pith-pipeline@v0.9.1-grok · 5824 in / 1353 out tokens · 46205 ms · 2026-06-29T19:48:57.216162+00:00 · methodology

discussion (0)

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