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arxiv: 2605.26555 · v1 · pith:HDOIJHMOnew · submitted 2026-05-26 · ⚛️ physics.app-ph

Chips in the Flatland : 2D Semiconductors for Future Computing Electronic

Narin Trakarnvanich , Mitra Sanchali , Tong Su , Haiyu Meng , Jing Lu , Kah-Wee Ang , Lain-Jong Li , Chit Siong Lau
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Yee Sin Ang
This is my paper

Pith reviewed 2026-06-29 14:57 UTC · model grok-4.3

classification ⚛️ physics.app-ph
keywords 2D semiconductorsfield-effect transistorscompact modelingintegrated circuitsRISC-Vmonolithic CMOSAngstrom era computingelectronic design automation
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The pith

Multiscale compact modeling is the required bridge to turn 2D semiconductor transistors into functional integrated circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper reviews the development of 2D semiconductor field-effect transistors from basic Boolean logic to complex chip architectures such as RISC-V and monolithic CMOS microprocessors. It argues that device-level performance has advanced but circuit-level integration has not, leaving a gap that prevents proof-of-concept devices from becoming working chips. The central position is that multiscale compact modeling, covering semiclassical, quantum-hybrid, and data-driven methods, supplies the missing connection to electronic design automation tools. This matters because it directly addresses how to move 2D materials into scalable manufacturing for Angstrom-era computing. The review also maps current bottlenecks in both fabrication and design flows to guide that translation.

Core claim

The review tracks the evolution of 2D semiconductor FETs from basic logic families and standard cells to complex chip architectures including recent RISC-V and monolithic CMOS microprocessors, while establishing multiscale compact modeling as the indispensable link between device physics and electronic design automation workflows for scalable chip development, and summarizing breakthroughs alongside fab and fabless bottlenecks.

What carries the argument

Multiscale compact modeling (semiclassical, quantum-hybrid, and data-driven approaches) that links device physics to electronic design automation workflows.

If this is right

  • Milestones demonstrate that 2D materials can support complex processor architectures beyond single transistors.
  • Compact modeling enables the use of standard EDA tools for 2D-based chip design.
  • Mapping fab and fabless bottlenecks identifies concrete next steps for scaling.
  • The overall path supports 2D semiconductors as candidates for Angstrom-era computing.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If compact models reach sufficient accuracy, they could shorten the timeline from material discovery to tape-out of small circuits.
  • The same modeling strategy might extend to hybrid 2D-silicon stacks or other emerging channel materials.
  • A practical test would be to extract parameters from a specific 2D FET and simulate a small logic block to check agreement with measured behavior.

Load-bearing premise

The cited milestones in RISC-V and monolithic CMOS processors using 2D materials are representative enough to guide general translation strategies, and the main barriers are fab and fabless issues rather than unresolved material or integration physics.

What would settle it

A working 2D-material microprocessor fabricated and verified without multiscale compact modeling, or a clear failure to reach functional integration even after deploying such models due to unaccounted physical effects.

Figures

Figures reproduced from arXiv: 2605.26555 by Chit Siong Lau, Haiyu Meng, Jing Lu, Kah-Wee Ang, Lain-Jong Li, Mitra Sanchali, Narin Trakarnvanich, Tong Su, Yee Sin Ang.

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read the original abstract

As transistor scaling approaches its fundamental physical limits in the Angstrom era, two-dimensional (2D) semiconductors have emerged as the promising channel material candidates for future computing. While the device physics of 2D semiconductors have been rigorously explored, translating these nanodevices into fully functional integrated circuits remains a largely uncharted frontier. This review bridges the gap between material- and device-centric breakthroughs and circuit-level chip design in 2D semiconductors, a valley of death that has so far prevented translation of high-performance individual transistors into functional chips. We track the evolution of 2D semi-conductor field-effect transistors from basic Boolean logic families and standard cells to complex chip architectures, including recent milestones in RISC-V and monolithic CMOS microprocessors. Critically, we highlight the indispensable role of multiscale compact modeling, spanning semiclassical, quantum-hybrid and data-driven approaches, as the necessary link between device physics and the electronic design automation workflows for scalable chip development. By summarizing recent breakthroughs and identifying the bottlenecks in both fab and fabless trajectories of 2D semiconductors, this review shall provide insights that motivates the translation of proof-of-concept 2D transistors into fully functional computing chips, paving a way towards future Angstrom era computing technology empowered by 2D semiconductors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. This review paper tracks the development of 2D semiconductor FETs from basic Boolean logic and standard cells through to complex chip architectures, citing recent RISC-V and monolithic CMOS microprocessor milestones. It positions multiscale compact modeling (semiclassical, quantum-hybrid, and data-driven) as the indispensable bridge between device physics and EDA workflows, while identifying fab and fabless bottlenecks as the primary barriers preventing translation of high-performance transistors into functional chips.

Significance. If the cited milestones are representative and the modeling emphasis is substantiated, the review could usefully organize the literature on scaling 2D devices to circuits and motivate targeted research on compact models. However, its value as a bridge document is limited by the absence of quantitative case studies linking specific modeling advances to the cited chip-level demonstrations.

major comments (2)
  1. [Abstract] Abstract: The central claim that multiscale compact modeling constitutes the 'necessary link' and 'indispensable role' for scalable chip development rests on the cited RISC-V and monolithic CMOS milestones as evidence of translation progress. No section in the provided abstract or structure demonstrates that these milestones have reached a stage where modeling (rather than contact resistance, dielectric integration, or variability) is the rate-limiting step, weakening the bottleneck diagnosis.
  2. [Abstract] Abstract: The review asserts that 'translating these nanodevices into fully functional integrated circuits remains a largely uncharted frontier' and that fab/fabless trajectories are the primary barriers. This framing is load-bearing for the call to action, yet the abstract provides no explicit comparison showing that the cited milestones are limited by modeling gaps versus fundamental material or integration physics issues outside the review's scope.
minor comments (2)
  1. [Title] Title: 'Future Computing Electronic' appears incomplete or typographically inconsistent with standard phrasing ('Electronics').
  2. [Abstract] Abstract: 'semi-conductor' uses an inconsistent hyphenation compared to the standard 'semiconductor' used elsewhere in the abstract.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our review manuscript. We address the two major comments on the abstract point by point below and agree that targeted revisions to the abstract will better substantiate the positioning of multiscale compact modeling.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that multiscale compact modeling constitutes the 'necessary link' and 'indispensable role' for scalable chip development rests on the cited RISC-V and monolithic CMOS milestones as evidence of translation progress. No section in the provided abstract or structure demonstrates that these milestones have reached a stage where modeling (rather than contact resistance, dielectric integration, or variability) is the rate-limiting step, weakening the bottleneck diagnosis.

    Authors: We acknowledge that the abstract, as currently worded, does not explicitly demonstrate through comparison that modeling has become the rate-limiting step versus other integration challenges. The manuscript reviews the cited milestones to illustrate progress from devices to circuits and argues, based on the surveyed literature, that compact modeling is required to bridge to EDA workflows. To address the concern, we will revise the abstract to include a concise statement noting that the review identifies modeling gaps as a key translational barrier in the context of the milestones, while recognizing that material and integration issues also remain active areas of research. revision: yes

  2. Referee: [Abstract] Abstract: The review asserts that 'translating these nanodevices into fully functional integrated circuits remains a largely uncharted frontier' and that fab/fabless trajectories are the primary barriers. This framing is load-bearing for the call to action, yet the abstract provides no explicit comparison showing that the cited milestones are limited by modeling gaps versus fundamental material or integration physics issues outside the review's scope.

    Authors: We agree that the abstract would benefit from an explicit qualifier on the relative role of modeling versus other physics issues. The full manuscript surveys both device-level challenges and the fab/fabless bottlenecks, using the milestones to highlight the current state of translation. We will revise the abstract to add a brief clause clarifying that, while material and integration challenges persist, the review focuses on multiscale modeling as the critical link for scalable circuit design based on the reviewed works. revision: yes

Circularity Check

0 steps flagged

Review paper with no derivations or predictions; no circularity present

full rationale

The manuscript is a literature review that summarizes device physics, milestones in RISC-V and monolithic CMOS using 2D materials, and the role of multiscale compact modeling. It contains no original equations, first-principles derivations, fitted parameters presented as predictions, or self-referential claims. The central narrative relies on external citations for milestones and bottlenecks rather than any chain that reduces by construction to its own inputs. No load-bearing step matches any of the enumerated circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a review paper; it introduces no new free parameters, axioms, or invented entities. All content rests on cited prior literature.

pith-pipeline@v0.9.1-grok · 5787 in / 1050 out tokens · 20695 ms · 2026-06-29T14:57:56.509952+00:00 · methodology

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Reference graph

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