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arxiv: 2605.27745 · v1 · pith:3QTA4JHKnew · submitted 2026-05-26 · 💻 cs.AR

CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST

Kaustav Goswami , Maryam Babaie , Hoa Nguyen , Venkatesh Akella , Jason Lowe-Power This is my paper

Pith reviewed 2026-06-29 14:49 UTC · model grok-4.3

classification 💻 cs.AR
keywords CXLdisaggregated memorysimulationgem5SSTmemory poolingcomputer architecturefull-system simulation
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The pith

CXL-ClusterSim combines gem5 and SST to simulate CXL disaggregated memory clusters at scale.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents CXL-ClusterSim as a new simulation framework for modeling systems with disaggregated memory using the CXL protocol. It integrates the gem5 simulator, which provides detailed system modeling, with the Structural Simulation Toolkit for handling larger parallel simulations. This approach aims to help explore design choices in memory pooling and sharing without the need for physical hardware prototypes. Architects can use it to study performance tradeoffs in large AI and cloud computing setups where DRAM is often underutilized.

Core claim

CXL-ClusterSim is a full-system simulation framework that merges gem5 for high-fidelity modeling of individual nodes with SST for scalable parallel execution across clusters, enabling evaluation of CXL-based memory disaggregation for improved resource utilization.

What carries the argument

The CXL-ClusterSim framework integrates gem5 and SST to model CXL protocol behavior in disaggregated memory clusters.

Load-bearing premise

The integration of gem5 and SST can preserve modeling fidelity for CXL behavior and cluster interactions without major accuracy loss or slowdown.

What would settle it

Running the same workload on both CXL-ClusterSim and a real CXL-enabled hardware cluster and finding large discrepancies in measured latency or throughput.

Figures

Figures reproduced from arXiv: 2605.27745 by Hoa Nguyen, Jason Lowe-Power, Kaustav Goswami, Maryam Babaie, Venkatesh Akella.

Figure 1
Figure 1. Figure 1: Overview of the simulation infrastructure. [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: System-level view of the remote memory ranges. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Ideal simulation timeline. ( [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The simulation timeline for CXL-ClusterSim. We [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Statistics used to validate the correctness of CXL [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: The total bandwidth was measured at each of the memory controllers. There were 8 system nodes in the cluster [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: The bandwidth reported by each of the STREAM [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Bandwidth reported by the two system nodes and [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 8
Figure 8. Figure 8: Reported host system statistics when the number [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: NPB workloads’ relative IPC of NUMA-Local [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Share of retired memory instructions served by [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Reported IPC of GAPBS kernels in CXL￾ClusterSim, when the same unweighted synthetic graph was shared across all the kernels. We compare the IPC of CXL-ClusterSim’s experiments with a single system running one kernel without additional latencies. pressure and switch modeling, which likely understates tail￾latency growth and interference under heavy co-tenancy; we leave detailed switch/fabric and credit-bas… view at source ↗
read the original abstract

Large-scale AI training and inference require hundreds of gigabytes to terabytes of DRAM with high peak to average utilization ratios, resulting in overprovisioning. In cloud computing, DRAM constitutes a significant share of the cost. Yet, as shown by recent articles, DRAM is heavily under utilized. Memory disaggregation is a solution to both these problems. With the advent of the CXL protocol, there is renewed interest in designing and optimizing computing systems with disaggregated memory. However, at present, there are limited simulation tools available for exploring the design space and evaluating the performance tradeoffs in computer systems with disaggregated memory. In this paper, we propose CXL-ClusterSim, a full-system modeling and simulation framework by combining the gem5 simulator for fidelity, with the Structural Simulation Toolkit (SST) for parallel simulation. We outline the challenges in creating this simulation infrastructure and present a design that is scalable, flexible, and reasonably fast to help computer architects to explore the design space of CXL-based disaggregated memory and identify new opportunities for hardware/software codesign and performance optimization.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The manuscript proposes CXL-ClusterSim, a full-system simulation framework that integrates the gem5 simulator (for modeling fidelity) with the Structural Simulation Toolkit (SST) (for parallel execution) to enable exploration of CXL-based disaggregated memory clusters for pooling and sharing. It outlines integration challenges and claims the resulting design is scalable, flexible, and reasonably fast for computer architects studying hardware/software co-design opportunities in memory disaggregation.

Significance. A validated implementation of this framework could address the current scarcity of simulation tools for CXL disaggregated memory systems and support design-space exploration at cluster scale. However, the manuscript supplies no validation data, performance measurements, fidelity comparisons to standalone gem5, or evidence that the gem5-SST coupling preserves CXL link, coherence, and memory-pool semantics, so the practical significance cannot yet be assessed.

major comments (2)
  1. [Abstract / §1] Abstract and §1 (Introduction): The central claim that the framework is 'scalable, flexible, and reasonably fast' while preserving 'sufficient modeling fidelity for CXL protocol behavior and cluster-scale interactions' is unsupported; the text contains no simulation speed results, accuracy metrics versus a pure-gem5 baseline, or timing-accuracy data for CXL transactions.
  2. [Design / Integration description] The integration layer between gem5 and SST is identified as the least-secured point for preserving transaction ordering, latency distributions, and bandwidth contention, yet no section demonstrates that the chosen synchronization or abstraction mechanisms maintain these properties at cluster scale.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive feedback on our manuscript describing CXL-ClusterSim. The work focuses on the design of a gem5-SST integration framework for CXL disaggregated memory, including integration challenges. We acknowledge that the manuscript does not include quantitative validation, speed results, or fidelity metrics, as it is primarily a design and architecture paper rather than an evaluation study. We will revise the text to ensure claims are appropriately qualified.

read point-by-point responses

  1. Referee: [Abstract / §1] Abstract and §1 (Introduction): The central claim that the framework is 'scalable, flexible, and reasonably fast' while preserving 'sufficient modeling fidelity for CXL protocol behavior and cluster-scale interactions' is unsupported; the text contains no simulation speed results, accuracy metrics versus a pure-gem5 baseline, or timing-accuracy data for CXL transactions.

    Authors: We agree that these claims lack supporting quantitative data in the manuscript. The paper's scope is the proposal of the framework architecture and discussion of integration challenges, not empirical evaluation. We will revise the abstract and §1 to remove or qualify the unsupported claims (e.g., stating design goals rather than demonstrated properties) and add a note that performance and fidelity evaluations are planned future work. revision: yes

  2. Referee: [Design / Integration description] The integration layer between gem5 and SST is identified as the least-secured point for preserving transaction ordering, latency distributions, and bandwidth contention, yet no section demonstrates that the chosen synchronization or abstraction mechanisms maintain these properties at cluster scale.

    Authors: The manuscript describes the integration mechanisms chosen to address ordering, latency, and contention. However, we acknowledge the absence of any demonstration or empirical evidence that these mechanisms preserve the required properties at cluster scale. We will expand the relevant design section with additional detail on the synchronization approach and its rationale, while explicitly noting the lack of validation and the assumptions involved. Full demonstration would require new experiments. revision: partial

standing simulated objections not resolved
  • Providing empirical validation data, speed measurements, accuracy metrics, or cluster-scale demonstrations of semantic preservation, as no such experiments or results exist in the current work.

Circularity Check

0 steps flagged

No circularity: tool-construction paper with no derivations or predictions

full rationale

The paper is a description of a proposed simulation framework (CXL-ClusterSim) that integrates two established external simulators (gem5 and SST). No equations, fitted parameters, predictions, or derivation chains exist in the text. The central claim is a design proposal for scalability and flexibility, not a result derived from inputs by construction. All load-bearing elements are engineering choices justified by reference to the capabilities of the base tools rather than self-referential reduction. This matches the default expectation of no circularity for non-derivational work.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The work rests on the established capabilities of two pre-existing simulators rather than new fitted parameters or invented entities.

axioms (2)
  • domain assumption gem5 provides high-fidelity modeling of individual CPU and memory systems
    Abstract relies on gem5's known properties for the fidelity component of the hybrid framework.
  • domain assumption SST supports scalable parallel simulation of large systems
    Abstract relies on SST's known properties for the parallel and scalability component.

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discussion (0)

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