pith. sign in

arxiv: 2606.23532 · v1 · pith:5F3H22XYnew · submitted 2026-06-22 · 💻 cs.ET · cs.AR· cs.NE

An Open-Source LFSR-Based Stochastic Leaky Integrate-and-Fire Neuron in SkyWater 130 nm: Design, Stochastic Characterisation, and Rate Coding

Poornima Kumaresan , Santhosh Sivasubramani This is my paper

Pith reviewed 2026-06-26 05:34 UTC · model grok-4.3

classification 💻 cs.ET cs.ARcs.NE
keywords stochastic neuronLFSRleaky integrate-and-fireSkyWater 130 nmrate codingBernoulli firingneuromorphic hardwareopen-source design
0
0 comments X

The pith

A 16-bit configurable LFSR and eight-entry table set Bernoulli firing probabilities in a leaky integrate-and-fire neuron on SkyWater 130 nm CMOS.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a fully digital stochastic neuron built from standard cells that uses a linear-feedback shift register to drive a small programmable table and thereby produce controlled random spikes. A saturating 16-bit leaky integrator accumulates weighted inputs, compares against a threshold, and respects a short refractory period, with all parameters loaded through a serial register file. Simulation confirms that the maximal-length LFSR produces a 65535-state period, that firing probability matches the table entry divided by 256, and that output rate rises monotonically with input weight while the refractory period caps the maximum rate. A reader would care because the design replaces analog randomness with reproducible digital pseudo-randomness, lowering area and allowing the circuit to tolerate noisy inputs on an open-source process flow.

Core claim

A 16-bit configurable-polynomial LFSR drives an eight-entry programmable activation table that sets a Bernoulli firing probability, while a saturating 16-bit leaky integrator with programmable threshold and zero-to-seven-cycle refractory period produces the spike train; the bit-exact model matches the register-transfer code, the period reaches 65535 states for a maximal polynomial, the eight-bit comparison value is uniform over the period, firing probability equals the table value divided by 256, and rate-coding sweeps confirm monotonic control of output rate by input weight and threshold.

What carries the argument

16-bit configurable-polynomial LFSR driving an eight-entry programmable activation table to decide Bernoulli firing

If this is right

  • Firing probability equals the eight-bit table entry divided by 256 for every entry.
  • Output spike rate rises monotonically as input weight increases or threshold decreases.
  • The refractory period limits the maximum firing rate to one spike every refractory-plus-one cycles.
  • Comparator output exhibits serial correlation at short lags that disappears when decisions are taken every sixteen cycles.
  • The neuron occupies roughly 10600 square micrometres at 70 percent utilisation and meets 50 MHz timing.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same LFSR-plus-table block could be replicated across an array to build larger stochastic neuromorphic processors without analog components.
  • System-level simulators of spiking networks should incorporate the observed short-lag correlation unless the model subsamples the neuron output.
  • Because the design uses only standard cells and an open flow, the same netlist can be retargeted to other open-source process nodes for direct comparison.
  • Runtime writes to the activation table enable on-chip adaptation of firing statistics without changing the surrounding digital fabric.

Load-bearing premise

Pre-silicon RTL, gate-level, and cocotb simulation results will match the electrical behavior of fabricated silicon on SkyWater 130 nm.

What would settle it

Fabricated silicon measurements showing that measured firing probability deviates from the programmed table value divided by 256 or that the LFSR sequence length differs from the simulated 65535 states.

Figures

Figures reproduced from arXiv: 2606.23532 by Poornima Kumaresan, Santhosh Sivasubramani.

Figure 1
Figure 1. Figure 1: Datapath of the stochastic leaky integrate-and-fire neuron. The configurable linear-feedback shift register supplies pseudorandom bits each cycle. The top three bits select one of eight activation-table entries, and the low eight bits form the comparison value; a stochastic event is asserted when the comparison value is less than the selected activation. The leaky integrate￾and-fire core adds the input cur… view at source ↗
Figure 2
Figure 2. Figure 2: Serial register interface. (a) The sixteen single-byte registers that configure the neuron, grouped by function: control and refractory, feedback polynomial, seed, threshold, decay, status, and the eight activation-table entries. (b) The sixteen-bit serial frame, with one read-or-write bit, seven address bits sent most significant first, and eight data bits. 3.3. Leaky integrate-and-fire core The membrane … view at source ↗
Figure 3
Figure 3. Figure 3: Configurable linear-feedback shift register. (a) Structure of the 16-bit Fibonacci register: the feedback bit is the exclusive-or reduction of the bitwise conjunction of the state and the programmable polynomial, and the next state is the state shifted left with the feedback inserted in the least significant bit. (b) Measured period as a function of the feedback polynomial. The shipped default 0x002D produ… view at source ↗
Figure 4
Figure 4. Figure 4: Statistics of the random source over the full maximal-length period (polynomial 0xB400). (a) Histogram of the eight￾bit comparison value; each value occurs the same number of times to the resolution of the count, so the comparison value is uniform. (b) Autocorrelation of the stochastic-event signal as a function of lag. The signal is serially correlated, about 0.32 at lag one with a secondary negative lobe… view at source ↗
Figure 5
Figure 5. Figure 5: Activation table and firing probability. (a) The default activation table: the eight programmed entries, addressed by the top three shift-register bits, rise in eight-bit steps and approximate a sigmoid. (b) Measured per-entry firing probability against the activation value. The points are the fraction of cycles on which a stochastic event is asserted, counted over the full maximal-length period; the line … view at source ↗
Figure 6
Figure 6. Figure 6: Rate-coding and refractory behaviour. The output spike rate increases monotonically with the input weight and decreases monotonically with the threshold. The refractory period caps the maximum output rate; the measured maximum-rate points lie on the law 1/(r +1) spikes per cycle, where r is the programmed refractory value in the range zero to seven. The weight sweep uses host mode with threshold 0x80 and d… view at source ↗
Figure 7
Figure 7. Figure 7: Routed layout of the stochastic neuron on a single Tiny Tapeout 1x1 tile on the SkyWater 130 nm process. The image is a render from the open place-and-route flow and is not measured silicon [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
read the original abstract

Stochastic spiking neurons trade exact arithmetic for controlled randomness, lowering area and tolerating input noise, which suits event-driven edge hardware. We present a compact, configurable stochastic leaky integrate-and-fire neuron in standard-cell CMOS on the SkyWater 130 nm process, released openly. A 16-bit configurable-polynomial linear-feedback shift register drives an eight-entry programmable activation table that sets a Bernoulli firing probability, and a saturating 16-bit leaky integrator with a programmable threshold and a refractory period of zero to seven cycles produces the spike train. All parameters are set through a sixteen-register serial interface, and the neuron runs from parallel inputs or entirely from the register file. From a model checked bit-exact against the register-transfer code, the period is 65535 states for a maximal-length polynomial and 63 for the shipped default, the eight-bit comparison value is uniform over the full period, and the per-entry firing probability equals the table value divided by 256. We also characterise a property a system-level model would not expose: the comparator output is serially correlated at short lags, with a negative lobe near lag eight, because the compared byte shifts by one bit each cycle; subsampling every sixteen cycles restores whiteness. Rate-coding sweeps show monotonic control of the output rate by the input weight and the threshold, and the refractory period caps the rate at one spike per refractory-plus-one cycles. The neuron occupies about 10,600 square micrometres at 70 per cent utilisation on a single Tiny Tapeout tile, meets 50 MHz timing with positive margin, and passes eighteen directed cocotb tests at register-transfer and gate level. All results are pre-silicon, from simulation and the open flow. The neuron is an openly released companion to a four-block neuromorphic suite reported separately.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The manuscript presents the design of an open-source stochastic leaky integrate-and-fire neuron in SkyWater 130 nm CMOS. A 16-bit configurable-polynomial LFSR drives an eight-entry activation table for Bernoulli firing probability in a saturating 16-bit leaky integrator with programmable threshold and refractory period. It reports a bit-exact model matching the RTL, LFSR periods of 65535 (maximal) and 63 (default), claims that the eight-bit comparison value is uniform over the period and firing probability equals table value / 256, characterizes serial correlations in the comparator output, shows monotonic rate coding, and gives pre-silicon area (~10,600 µm²), timing (50 MHz), and cocotb test results from simulation and the open flow.

Significance. If the central claims hold, the work supplies a compact, configurable stochastic neuron with an openly released RTL and flow, suitable for neuromorphic edge hardware. The bit-exact model verification against RTL and the 18 directed tests are strengths that establish internal consistency within simulation; the pre-silicon limitation is clearly stated.

major comments (1)
  1. [Abstract] Abstract (and the stochastic characterisation section): the claim that 'the eight-bit comparison value is uniform over the full period' and 'the per-entry firing probability equals the table value divided by 256' is incorrect. A maximal-length 16-bit LFSR has period 65535, which is not divisible by 256; the 256 possible 8-bit patterns therefore occur with frequencies 255 and 256 (one pattern 255 times, the rest 256 times). The same non-uniformity applies to the default period of 63. This falsifies the exact-equality claim for firing probability even inside the bit-exact model and RTL simulation.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the careful review and for identifying an imprecision in our description of the LFSR output distribution. We address the point below and will revise the manuscript to correct the claim.

read point-by-point responses

  1. Referee: [Abstract] Abstract (and the stochastic characterisation section): the claim that 'the eight-bit comparison value is uniform over the full period' and 'the per-entry firing probability equals the table value divided by 256' is incorrect. A maximal-length 16-bit LFSR has period 65535, which is not divisible by 256; the 256 possible 8-bit patterns therefore occur with frequencies 255 and 256 (one pattern 255 times, the rest 256 times). The same non-uniformity applies to the default period of 63. This falsifies the exact-equality claim for firing probability even inside the bit-exact model and RTL simulation.

    Authors: The referee is correct. A period of 65535 yields 8-bit values with frequencies of 255 or 256, so the distribution is not perfectly uniform and the firing probability equals table_value/256 only up to a maximum deviation of order 1/65535. The same holds for period 63. We will revise the abstract and the stochastic characterisation section to state the exact frequencies and to describe the probability as approximately table_value/256 with this bounded error. The bit-exact model and all simulation results remain unchanged, as they match the RTL exactly; the correction affects only the wording of the uniformity claim. revision: yes

Circularity Check

0 steps flagged

No circularity; direct hardware description with bit-exact mapping

full rationale

The paper is a pre-silicon engineering design description of an LFSR-driven stochastic LIF neuron. All load-bearing claims (period 65535/63, table-driven Bernoulli probability, monotonic rate coding, serial correlation) are presented as direct observations from a model stated to be bit-exact against the RTL implementation and verified via cocotb tests. No equations, fitted parameters, ansatzes, or uniqueness theorems appear; there are no derivations that reduce outputs to inputs by construction, no self-citation chains, and no renaming of known results. The design is self-contained against its own RTL and simulation artifacts.

Axiom & Free-Parameter Ledger

3 free parameters · 2 axioms · 0 invented entities

Relies on standard properties of maximal-length LFSRs and programmable hardware parameters; no new physical entities postulated.

free parameters (3)
  • LFSR polynomial
    Configurable choice for period length; default yields period 63.
  • activation table values
    Eight programmable entries that directly set per-cycle firing probability.
  • threshold and refractory period
    Programmable parameters controlling integrator and spike timing.
axioms (2)
  • standard math Maximal-length LFSR produces uniform distribution over its period
    Invoked to claim eight-bit comparison value is uniform.
  • domain assumption Firing probability equals table entry divided by 256
    Direct mapping from table to Bernoulli trial probability.

pith-pipeline@v0.9.1-grok · 5885 in / 1297 out tokens · 27115 ms · 2026-06-26T05:34:39.630802+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

29 extracted references · 25 canonical work pages · 1 internal anchor

  1. [1]

    Design and development of a neuromorphic silicon suite: PVT sensing, stochastic LIF inference, on-chip STDP learning, and crossbar programming, 2026

    Poornima Kumaresan and Santhosh Sivasubramani. Design and development of a neuromorphic silicon suite: PVT sensing, stochastic LIF inference, on-chip STDP learning, and crossbar programming, 2026. arXiv preprint, arXiv:XXXX.XXXXX (to be updated with assigned identifier)

    2026

  2. [2]

    Loihi: A neuromorphic manycore processor with on-chip learning.IEEE Micro, 38:82-99, 2018

    Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham Chinya, Yongqiang Cao, Sri Harsha Choday, Andreas Wild, and Hong Wang. Loihi: A neuromorphic manycore processor with on-chip learning.IEEE Micro, 38:82-99, 2018. doi: 10.1109/mm.2018.112130359

    work page doi:10.1109/mm.2018.112130359 2018

  3. [3]

    Merolla, John V

    Paul A. Merolla, John V . Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernard Brezzo, Ivan V o, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra S. Modha. A million spiking-neuron inte...

    work page doi:10.1126/science.1254642 2014

  4. [4]

    Cassidy, Paul Merolla, John V

    Andrew S. Cassidy, Paul Merolla, John V . Arthur, Steve K. Esser, Bryan Jackson, Rodrigo Alvarez-Icaza, Pallab Datta, Jun Sawada, Theodore M. Wong, Vitaly Feldman, Arnon Amir, Daniel Ben-Dayan Rubin, Filipp Akopyan, Emmett McQuinn, William P. Risk, and Dharmendra S. Modha. Cognitive computing building block: A versatile and efficient digital neuron model ...

    work page doi:10.1109/ijcnn.2013.6707077 2013

  5. [5]

    Armin Alaghi and John P. Hayes. Survey of stochastic computing.ACM Transactions on Embedded Computing Systems, 12:1-19, 2013. doi: 10.1145/2465787.2465794

    work page doi:10.1145/2465787.2465794 2013

  6. [6]

    Design of an efficient parallel random number generator using a single lfsr for stochastic computing

    Donghui Lee, Hyoju Seo, and Yongtae Kim. Design of an efficient parallel random number generator using a single lfsr for stochastic computing. In2024 International Conference on Artificial Intelligence in Information and Communication (ICAIIC), pages 775-777, 2024. doi: 10.1109/icaiic60209.2024.10463230

    work page doi:10.1109/icaiic60209.2024.10463230 2024

  7. [7]

    Sutton, and Supriyo Datta

    Kerem Yunus Camsari, Rafatul Faria, Brian M. Sutton, and Supriyo Datta. Stochastic p-bits for invertible logic.Physical Review X, 7: 031014, 2017. doi: 10.1103/physrevx.7.031014

    work page doi:10.1103/physrevx.7.031014 2017

  8. [8]

    Wang, Tara J

    Chetan Singh Thakur, Saeed Afshar, Runchun M. Wang, Tara J. Hamilton, Jonathan Tapson, and Andre van Schaik. Bayesian estimation and inference using stochastic electronics.Frontiers in Neuroscience, 10:104, 2016. doi: 10.3389/fnins.2016.00104

    work page doi:10.3389/fnins.2016.00104 2016

  9. [9]

    Neuromorphic silicon neuron circuits.Frontiers in Neuroscience, 5:73, 2011

    Giacomo Indiveri, Bernabe Linares-Barranco, Tara Julia Hamilton, Andre van Schaik, Ralph Etienne-Cummings, Tobi Delbruck, Shih-Chii Liu, Piotr Dudek, Philipp Hafliger, Sylvie Renaud, Johannes Schemmel, Gert Cauwenberghs, John Arthur, Kai Hynna, Fopefolu Folowosele, Sylvain Saighi, Teresa Serrano-Gotarredona, Jayawan Wijekoon, Yingxue Wang, and Kwabena Boa...

    work page doi:10.3389/fnins.2011.00073 2011

  10. [10]

    Venkateswara Reddy and N

    K. Venkateswara Reddy and N. Balaji. Efficient hardware implementation of spiking neural networks using nonstandard finite difference scheme for leaky integrate and fire neuron model.Journal of Circuits, Systems and Computers, 34, 2024. doi: 10.1142/s0218126625500380

    work page doi:10.1142/s0218126625500380 2024

  11. [11]

    Exploring neuronal leakage for spiking neural networks on event-driven hardware

    Jann Krausse, Sven Nitzsche, Brian Pachideh, Carmen Weigelt, Klaus Knobloch, and Juergen Becker. Exploring neuronal leakage for spiking neural networks on event-driven hardware. In2024 International Conference on Neuromorphic Systems (ICONS), pages 140-147, 2024. doi: 10.1109/icons62911.2024.00028

    work page doi:10.1109/icons62911.2024.00028 2024

  12. [12]

    Bifurcation phenomena observed from two-variable spiking neuron integrated circuit

    Takemori Orima, Yoshihiko Horio, Satoshi Moriya, and Shigeo Sato. Bifurcation phenomena observed from two-variable spiking neuron integrated circuit. In2024 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1-5, 2024. doi: 10.1109/iscas58744.202 4.10558075

    work page doi:10.1109/iscas58744.202 2024

  13. [13]

    Donghui Lee and Yongtae Kim. Hardware-efficient quantized stochastic computing with reduced precision stochastic number generator and lfsr-based counter.International Journal of Circuit Theory and Applications, 53:7281-7294, 2025. doi: 10.1002/cta.70041

    work page doi:10.1002/cta.70041 2025

  14. [14]

    Shrivastava

    Murchana Saikia and Bhawna P. Shrivastava. Adaptive reconfigurable lfsr: Dynamic tapping and reseeding for enhanced pseudo random number generation. In2024 IEEE International Students Conference on Electrical, Electronics and Computer Science (SCEECS), pages 1-6,

  15. [15]

    doi: 10.1109/sceecs61402.2024.10482241

    work page internal anchor Pith review Pith/arXiv arXiv doi:10.1109/sceecs61402.2024.10482241 2024

  16. [16]

    High-entropy lfsr-based random number generator (rng) for hardware security

    Sonia Akter, Shelby Williams, Prosen Kirtonia, Kasem Khalil, and Magdy Bayoumi. High-entropy lfsr-based random number generator (rng) for hardware security. In2025 IEEE 38th International System-on-Chip Conference (SOCC), pages 1-6, 2025. doi: 10.1109/socc6612 6.2025.11235484

    work page doi:10.1109/socc6612 2025

  17. [17]

    Random number generation from image data and lfsr.IEEJ Transactions on Industry Applications, 145:192-199, 2025

    Shuichi Ichikawa. Random number generation from image data and lfsr.IEEJ Transactions on Industry Applications, 145:192-199, 2025. doi: 10.1541/ieejias.145.192

    work page doi:10.1541/ieejias.145.192 2025

  18. [18]

    A comparison for probabilistic spiking neuron model and spiking integrate-and-fire neuron model

    Xiuqing Wang, Zeng-Guang Hou, Hui Zeng, Min Tan, and Yongji Wang. A comparison for probabilistic spiking neuron model and spiking integrate-and-fire neuron model. InProceedings of the 33rd Chinese Control Conference (CCC), pages 5059-5064, 2014. doi: 10.1109/chic c.2014.6895800

    work page doi:10.1109/chic 2014

  19. [19]

    Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength, and postsynaptic cell type.The Journal of Neuroscience, 18:10464-10472, 1998

    Guo-qiang Bi and Mu-ming Poo. Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength, and postsynaptic cell type.The Journal of Neuroscience, 18:10464-10472, 1998. doi: 10.1523/jneurosci.18-24-10464.1998

    work page doi:10.1523/jneurosci.18-24-10464.1998 1998

  20. [20]

    A hybrid analog/digital spike-timing dependent plasticity learn- ing circuit for neuromorphic vlsi multi-neuron architectures

    Hesham Mostafa, Federico Corradi, Fabio Stefanini, and Giacomo Indiveri. A hybrid analog/digital spike-timing dependent plasticity learn- ing circuit for neuromorphic vlsi multi-neuron architectures. In2014 IEEE International Symposium on Circuits and Systems (ISCAS), pages 854-857, 2014. doi: 10.1109/iscas.2014.6865270

    work page doi:10.1109/iscas.2014.6865270 2014

  21. [21]

    Building openlane: A 130nm openroad-based tapeout-proven flow

    Mohamed Shalan and Tim Edwards. Building openlane: A 130nm openroad-based tapeout-proven flow. InProceedings of the 39th Interna- tional Conference on Computer-Aided Design (ICCAD), pages 1-6, 2020. doi: 10.1145/3400302.3415735

    work page doi:10.1145/3400302.3415735 2020

  22. [22]

    Design and implementation of integrated circuits using open source tools and sky130 free pdk

    Krzysztof Herman, Mauricio Montanares, and Jorge Marin. Design and implementation of integrated circuits using open source tools and sky130 free pdk. In2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), pages 105-110,

  23. [23]

    doi: 10.23919/mixdes58562.2023.10203216

    work page doi:10.23919/mixdes58562.2023.10203216 2023

  24. [24]

    Eshraghian

    Farhad Modaresi, Matthew Guthaus, and Jason K. Eshraghian. Openspike: An openram snn accelerator. In2023 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1-5, 2023. doi: 10.1109/iscas46773.2023.10182182

    work page doi:10.1109/iscas46773.2023.10182182 2023

  25. [25]

    Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, and David Bol. A 0.086-mm2 12.7-pj/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28nm cmos.IEEE Transactions on Biomedical Circuits and Systems, 13:145-158, 2019. doi: 10.1109/tbcas.2018.2880425

    work page doi:10.1109/tbcas.2018.2880425 2019

  26. [26]

    Reckon: A 28nm sub-mm2 task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales

    Charlotte Frenkel and Giacomo Indiveri. Reckon: A 28nm sub-mm2 task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales. In2022 IEEE International Solid-State Circuits Conference (ISSCC), pages 1-3, 2022. doi: 10.1109/isscc42614.2022.9731734

    work page doi:10.1109/isscc42614.2022.9731734 2022

  27. [27]

    Neurocorex: An open-source fpga-based spiking neural network emulator with on-chip learning, 2025

    Ashish Gautam, Prasanna Date, Shruti Kulkarni, Robert Patton, and Thomas Potok. Neurocorex: An open-source fpga-based spiking neural network emulator with on-chip learning, 2025. arXiv:2506.14138

    arXiv 2025

  28. [28]

    Hardware-efficient stochastic computing-based neural networks with snn-isomorphic lif activa- tion.Electronics, 15:768, 2026

    Jiho Kim, Kaeun Lim, and Youngmin Kim. Hardware-efficient stochastic computing-based neural networks with snn-isomorphic lif activa- tion.Electronics, 15:768, 2026. doi: 10.3390/electronics15040768

    work page doi:10.3390/electronics15040768 2026

  29. [29]

    Anderson, Yuko Hara-Azumi, and Shigeru Yamashita

    Jason H. Anderson, Yuko Hara-Azumi, and Shigeru Yamashita. Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. In2016 Design, Automation and Test in Europe Conference and Exhibition (DATE), pages 1550-1555, 2016. doi: 10.3850/9783981537079_0162. 12

    work page doi:10.3850/9783981537079_0162 2016