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REVIEW 3 major objections 5 minor 60 references

FPGA-Based Mini X-Ray Detector Front-End

T0 review · 3 major / 5 minor · reviewed 2026-07-15 · grok-4.5

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Pith's one-line read A small FPGA pipeline can receive, store, detect, correct, and return synthetic X-ray-style pixel errors in real time.

desk verdict Solid course-project demo of a modular UART/BRAM/FSM image-correction pipeline; educational value is real, research novelty is not. read the letter →

arxiv 2607.12126 v1 pith:N5SAGJOB submitted 2026-07-13 cs.AR

Kris Paetow , D.G. Perera This is my paper · ORCID
classification cs.AR
keywords FPGAmedicalimagingfront-endoffsetcorrectiongainBRAMUARTX-raydetectorsimulationArtix-7
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This project shows that a classroom-scale FPGA can act as a mini detector front-end: it takes a 16×16 grayscale test image from a PC, holds it in on-chip memory, finds offset or gain pixel defects, fixes them, and sends the cleaned image back while reporting error counts and locations on board LEDs and an LCD. The work is deliberately simplified—no real X-ray sensor—but it walks through the same digital steps a real imaging front-end needs: transfer, frame buffering, analysis, correction, and feedback. A sympathetic reader cares because medical imagers need predictable, low-latency hardware between the sensor and the display, and FPGAs are a practical way to prototype that path without fabricating a custom chip. The design stays modular so each block can be built and checked alone before the whole pipeline is stitched together.

What carries the argument

A top-level control FSM that arbitrates single-port BRAM ownership among the UART receive controller, image-processing core, UART transmit controller, and LCD logic so only one module drives memory at a time while the image core scans row-major, thresholds pixels, packs error coordinates, and writes corrected baselines.

What would settle it

Run the same dark and light test images through the board and check whether every deliberately injected error pixel is both counted on the LEDs, listed at the correct (x,y) on the LCD, and restored to the exact baseline value (10 or 180) in the returned image with no residual column shift or missed detections.

Watch

Extended reading notes

Core claim

The completed FPGA design successfully receives a 16×16 grayscale image over UART, stores it in BRAM, detects offset or gain-related pixel errors according to a selected mode, corrects those pixels, returns the corrected image to the host, shows the error count on LEDs, and lists stored error locations on an LCD, thereby proving a working proof-of-concept of the major detector-front-end pipeline steps.

Load-bearing premise

The claim rests on treating a few hand-placed defects in a tiny synthetic grayscale image, fixed numeric thresholds, and constant baseline replacement as enough to stand in for real detector offset and gain nonuniformity.

Editorial extensions

If this is right

  • A modular UART–BRAM–FSM pipeline can demonstrate detector-style offset and gain correction without a physical X-ray sensor.
  • Low resource use (under 0.5 % LUTs/FFs, half a BRAM block) leaves headroom for larger frames or extra defect types on the same Artix-7 board.
  • Separate RX/TX controllers and a single clock domain keep serial transfer and image logic independently debuggable.
  • Fixed-threshold correction plus LED/LCD feedback is enough for a controlled classroom proof-of-concept of front-end data flow.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same arbitration pattern could be reused for streaming larger frames if multi-ported or dual-buffer memory replaced the single-port BRAM.
  • Replacing constant baselines with a short calibration-pass average would move the design closer to real flat-field correction without changing the outer FSM.
  • The residual one-column shift points to a general lesson: synchronous BRAM latency must be pipeline-matched in any write-back image path.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The manuscript presents a class-scale FPGA proof-of-concept for a simplified X-ray detector front-end on an Artix-7 AC701 board. A host Python script generates 16×16 grayscale test images with deliberately injected offset or gain defects, sends them over UART, and receives a corrected image. On the FPGA, a modular pipeline stores the frame in BRAM, uses a DIP-switch-selected mode to flag pixels against fixed dark/gain thresholds, replaces flagged pixels with constant baselines (10 or 180), stores error coordinates, returns the corrected frame, reports the error count on LEDs, and displays error locations on an LCD under button control. Implementation results report very low utilization, timing closure at 10 MHz, and successful detection of the injected defects in dark and light demos, with an acknowledged residual one-column shift in the returned light image attributed to BRAM latency.

Significance. As an educational demonstration of modular FPGA design for a medical-imaging-inspired pipeline (UART, BRAM arbitration, image-processing FSM, LCD feedback), the work is useful and the hardware demos (Figures 8–9, Tables 2–3) and resource/timing numbers are concrete. It does not claim a new detector-correction algorithm or transfer to real flat-field calibration; the contribution is a working, documented student-scale system that separates communication, memory ownership, and correction. That limited claim is supported by the reported demos. The long closing citation block to the same research group does not add technical novelty to the pipeline itself.

major comments (3)
  1. The manuscript is written as a course final-project report (motivation from lab experience, class LCD notes [5], “bonus” LCD, residual bugs left for future work) rather than a research article. For a serious cs.AR journal, the central claim is only a working 16×16 synthetic demo; there is no comparison to prior FPGA front-ends beyond brief citations, no quantitative latency/throughput analysis of the pipeline, and no evaluation against real detector data or standard flat-field methods. Without a clear research question and baseline comparison, the work does not meet typical archival standards even if the demo is correct.
  2. Section 3.1.3 and 4.1.2–4.1.3: correction is fixed-threshold flagging plus replacement by constant baselines (dark=10, light=180). Exact threshold values are never stated, and no calibration-frame or per-pixel gain-map path is implemented. The authors acknowledge this as a simplification (Sections 1.2, 2.1, 4.2), but the abstract and introduction still frame the work as a mini X-ray detector front-end. Either the claim language must be narrowed strictly to “synthetic threshold demo” or a more representative correction path (or at least explicit thresholds and sensitivity analysis) is needed for the medical-imaging framing to hold.
  3. Section 4.1.3 reports a residual one-column shift in the returned light image, attributed to BRAM read latency / FSM alignment, and Section 3.3 notes remaining latency issues. Because the strongest claim (Section 4.3) includes returning a correctly ordered corrected image, this is a load-bearing functional defect for the output path. A fix (explicit address/data pipelining or corrected write-back/TX sequencing) or a clear demonstration that the shift is eliminated should be required before acceptance of the pipeline claim.
minor comments (5)
  1. Abstract and Section 1.1 largely repeat the same medical-imaging motivation paragraph; tighten and state the concrete 16×16 UART–BRAM–correct–return scope up front.
  2. Figures 1–9 are referenced but not available as high-resolution captions with signal names; ensure waveforms (Figures 3–6) label key signals (process_start, bram_we, error_count, etc.) so the simulations are reproducible from the text alone.
  3. References [6]–[59] are almost entirely from one research group and are used mainly to assert that FPGAs are generally suitable; prune to works that directly inform detector front-ends, flat-field correction, or the specific architecture choices.
  4. Table 1 and peripheral description are clear; add the exact dark/high-gain/low-gain threshold constants and BRAM address map (image 0–255, error list from 256) in a small table for reproducibility.
  5. Minor typos and formatting: “frontend”/“front-end” inconsistency, “image process core” vs “image-processing,” and incomplete DOI/URL punctuation in the reference list.

Circularity Check

1 steps flagged · score 1.0 of 10

No derivation circularity: the demo is a self-contained synthetic pipeline; only a non-load-bearing self-citation block frames FPGAs as 'best option'.

  1. self citation load bearing [Section 4.3 closing paragraphs; refs [6]–[59]]
    "This work is inspired by the digital design research group at UCCS. This group has done extensive work in FPGA-based architectures, techniques, and associated models. Their analyses [6],[7] show that FPGA-based embedded systems are currently the best option to support applications and techniques, such as the ones presented in this report. Also, their previous work on FPGA-based embedded accelerators... demonstrated that FPGA-based embedded systems are the best avenue to support and accelerate complex algorithms and techniques."

    The claim that FPGAs are 'the best option/avenue' for this class of system is justified almost entirely by a long chain of self-group citations rather than by independent external benchmarks or by the demo itself. The demo result (working synthetic pipeline) does not depend on that ranking, so the circularity is framing-only and not load-bearing for the paper's strongest claim.

full rationale

This is an educational FPGA proof-of-concept, not a first-principles derivation paper. The strongest claim (Section 4.3) is that a modular design received a 16×16 grayscale image over UART, stored it in BRAM, detected offset/gain errors via fixed thresholds, corrected pixels to constant baselines (10 or 180), returned the image, and displayed error count/locations on LEDs/LCD. Those steps are verified by construction against deliberately injected defects (Tables 2–3, Figures 8–9) and by simulation/implementation results; they do not reduce to a fitted parameter renamed as prediction, nor to a uniqueness theorem. The authors explicitly scope the work as a simplified class demo (Sections 1.2, 2.1), not a commercial detector. The only mild circularity-adjacent pattern is the closing block (end of Section 4.3 and refs [6]–[59]), almost all from the same group, used to assert that FPGA-based embedded systems are 'the best option' and to list future optimization directions. That framing is not load-bearing for the reported pipeline result, so the score remains 1 rather than 0.

Assumptions & free parameters 5 free parameters · 3 assumptions · 0 invented entities

The central demonstration rests on a handful of hand-chosen constants (baselines, thresholds, image size, baud/clock) and domain assumptions that synthetic threshold violations stand in for real detector nonuniformity. No new physical entities are postulated; the free parameters and modeling choices fully determine the reported “success.”

free parameters (5)
  • dark baseline correction value = 10
    Defective dark-frame pixels are overwritten with the constant 10 grayscale counts (Section 3.1.3).
  • light baseline correction value = 180
    Defective light-frame pixels are overwritten with the constant 180 grayscale counts (Section 3.1.3).
  • dark / high-gain / low-gain thresholds = unspecified
    Error detection is pure threshold comparison; exact numeric cut-offs are never stated in the text, yet they decide every flagged pixel.
  • image size and BRAM layout = 16×16 / 256-pixel image region
    16×16 pixels occupy addresses 0–255; error list begins at 256; 9-bit addressing chosen by hand for the demo.
  • system clock and UART baud = 10 MHz / 9600 baud
    Single 10 MHz clock domain and 9600 baud are design choices that set all timing margins.
assumptions (3)
  • domain assumption Offset and gain nonuniformity in a real X-ray detector can be adequately represented by a few pixels that simply exceed or fall below fixed grayscale thresholds on a synthetic dark or light frame.
    Stated in Sections 1.2 and 2.1 as the justification for the entire simplified pipeline.
  • domain assumption A single-port BRAM can be safely time-multiplexed among RX, image processor, TX, and LCD by a top-level FSM without data corruption provided only one master is enabled per state.
    Section 3.1.5; residual column-shift bug shows the assumption is only partially realized.
  • ad hoc to paper Replacing a flagged pixel by a constant baseline is a valid stand-in for offset subtraction and flat-field gain correction used in commercial detectors.
    Section 3.1.3 and future-work discussion; authors themselves note real systems use calibration frames and scaling.

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Cite this review

Pith. "Pith review of FPGA-Based Mini X-Ray Detector Front-End." pith.science (2026). https://pith.science/paper/N5SAGJOB

@misc{pith2026260712126,
  author       = {Pith},
  title        = {Pith review of: FPGA-Based Mini X-Ray Detector Front-End},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/N5SAGJOB}},
  note         = {Machine review of arXiv:2607.12126}
}
read the original abstract

Medical imaging systems require reliable front-end electronics that can acquire sensor data, process image information, identify errors, and communicate results to other parts of the system. In applications such as X-ray imaging, CT, PET, ultrasound, and other diagnostic imaging systems, the electronics must often handle large amounts of data while maintaining predictable timing and low-latency operation. Because of these requirements, FPGAs (Field Programmable Gate Arrays) are commonly useful for medical imaging and signal-processing applications. In this project, the medical imaging concept is simplified into a small FPGA-based frontend demonstration.

Figures

Figures reproduced from arXiv: 2607.12126 by the authors.

Figure 1
Figure 1. shows the high level system diagram of the design. The concept of the design is straightforward: send a grayscale image created through Python from the PC to the FPGA, analyze and correct any ”defective” pixels on the FPGA, then return the corrected image to the PC. The FPGA will also show the number of errors found on the LEDs, and the LCD will display the locations. The image is stored on the BRAM of the FPGA so t… view at source ↗
Figure 2
Figure 2. shows the top-level system flow of the design. A clock wizard drives each module with a 10 MHz signal. At the center of the design is the BRAM where the image data is stored. Each module interacts with the BRAM and only one module is interacting at a time to avoid errors. First an image with errors is sent from the host PC to the FPGA through the UART Rx. The UART Rx includes a controller that handles where each rec… view at source ↗
Figure 3
Figure 3. Image Process Core simulation The zoomed-out waveform shows the error-detection and correction behavior during the dark-image test. When a pixel value exceeds the dark threshold, the module identifies it as an offset error. At each detected error, error count increments, bram we pulses, and bram din is driven with the correction value or stored error-location data, depending on the current FSM state. The waveform sh… view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Image Process Core Simulation Expanded 3.1.4 UART Receive and Transmit The UART RX and TX are implemented as separate modules, as well as the controllers for each. These modules don’t know what an image is, they only send and receive bytes. The controllers are what def…
Figure 5
Figure 5. Figure 5: UART TX/RX loopback simulation [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: RX and TX controller simulation 3.1.5 Top-Level Control FSM and BRAM Arbitration Since the design uses a single-port BRAM, only one subsystem can access the memory interface during a given clock cycle. The UART receive controller, image processing core, UART transmit c…
Figure 7
Figure 7. Figure 7: Implementation details The implementation results show that the final design remains relatively lightweight even though it is more complex than the previous lab projects. The system includes UART receive and transmit modules, BRAM-based image storage, an image-processi…
Figure 8
Figure 8. Figure 8: shows the dark image sent to the FPGA on the left and the corrected image returned to the PC on the right. The deliberately added high-offset pixels are removed in the returned image, showing that the threshold detection and correction path operated as intended for the…
Figure 9
Figure 9. Figure 9: shows the light image sent to the FPGA on the left and the corrected image returned to the PC on the right. The deliberately added high-gain and low-gain pixels are removed in the returned image, showing that the threshold detection and correction path operated as inte…

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Reference graph

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    M.A. Mohsin, S.N. Shahrouzi, and D.G. Perera, “Composing Efficient Computational Models for Real -Time Processing on Next-Generation Edge-Computing Platforms” IEEE ACCESS, (Open Access Journal in IEEE), 30- page manuscript, 13th February 2024

    2024

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    High-Level Synthesis-Based FPGA Hardware Architecture for PCA+SVM for Real-Time Processing on Edge Computing Platforms

    Mokhles A. Mohsin, and Darshika G. Perera, “High-Level Synthesis-Based FPGA Hardware Architecture for PCA+SVM for Real-Time Processing on Edge Computing Platforms” IEEE ACCESS, (Open Access Journal in IEEE), 24-page manuscript, 18th December 2025. DOI: 10.1109/ACCESS.2025.364576

    2025 doi

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    FPGA -Based Hardware Architecture for Sequence Alignment by Genetic Algorithm

    Laura H. Garcia, Arkan Alkamil, Mokhles A. Mohsin, Johannes Menzel and Darshika G. Perera, “FPGA -Based Hardware Architecture for Sequence Alignment by Genetic Algorithm”, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’25), 5-page manuscript,...

    2025

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    An FPGA-Based Hardware Accelerator for Sequence Alignment by Genetic Algorithm

    L. H. Garcia, "An FPGA-Based Hardware Accelerator for Sequence Alignment by Genetic Algorithm", MSc Thesis, Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, December 2019

    2019

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    Neuromorphic Sentiment Analysis Using Spiking Neural Networks

    R.K. Chunduri and D.G. Perera, “Neuromorphic Sentiment Analysis Using Spiking Neural Networks”, Sensors, MDPI open access journal, Sensing and Imaging Section, 24-page manuscript, vol. 23, no. 7701, 6th September 2023

    2023

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    Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker

    S. Sharma and D. G. Perera, “Analysis of Generalized Hebbian Learning Algorithm for Neuromorphic Hardware Using Spinnaker” 8-page manuscript, https://doi.org/10.48550/arXiv.2411.11575

    doi arXiv

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    High-Level Synthesis-Based FPGA Hardware Accelerator for Generalized Hebbian Learning Algorithm for Neuromorphic Computing

    S. Sharma, and D.G. Perera, “High-Level Synthesis-Based FPGA Hardware Accelerator for Generalized Hebbian Learning Algorithm for Neuromorphic Computing” Electronics, MDPI open access journal, 21 -page manuscript, vol. 15, no. 8: 1725. 18th April 2026; https://doi.org/10.3390/e...

    2026 doi

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    A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis

    R. Raghavan and D.G. Perera, “A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1 ...

    2017

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    Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,

    D.G. Perera and Kin F. Li, “Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,” in Proceedings of 22nd IEEE International Conference on Advanced Information Networking and Applications, (AINA’08), pp. 955-962, Okinawa, Japan, March 2008

    2008

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    A Fast and Scalable Hardware Architecture for K-Means Clustering for Big Data Analysis

    R. Raghavan, "A Fast and Scalable Hardware Architecture for K-Means Clustering for Big Data Analysis", MSc Thesis, (Supervisor Dr. Darshika G. Perera), Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, May 2016

    2016

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    A Design Methodology for Mobile and Embedded Applications on FPGA -Based Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “A Design Methodology for Mobile and Embedded Applications on FPGA -Based Dynamic Reconfigurable Hardware”, International Journal of Embedded Systems, (IJES), Inderscience publishers, 23-page manuscript, vol. 11, no. 5, Sept. 2019

    2019

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    Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications

    D.G. Perera, “Analysis of FPGA-Based Reconfiguration Methods for Mobile and Embedded Applications”, in Proceedings of 12th ACM FPGAWorld International Conference, (FPGAWorld’15), pp. 15 -20, Stockholm, Sweden, September 2015

    2015

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    Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6 -page manuscript, Victoria, BC, Canada, August 2024

    2024

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    FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

    D.G. Perera and Kin F. Li, “FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications”, in Proc. of 6th IEEE Int. Conf. on P2P, Parallel, Grid, Cloud, and Internet Computing, (3PGCIC’11), pp. 100-108, Barcelona, Spain, October 2011

    2011

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    Similarity Computation Using Reconfigurable Embedded Hardware,

    D.G. Perera and Kin F. Li, “Similarity Computation Using Reconfigurable Embedded Hardware,” in Proceedings of 8th IEEE International Conference on Dependable, Autonomic, and Secure Computing (DASC’09), pp. 323 -329, Chengdu, China, December 2009

    2009

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    Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices”, EURASIP Journal on Embedded Systems, SpringerOpen , vol. 2017, article no. 25, 18-page manuscript, 21st February 2017

    2017

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    HDL Code Optimization: Impact on Hardware Implementations and CAD Tools

    S.N Shahrouzi and D.G. Perera, “HDL Code Optimization: Impact on Hardware Implementations and CAD Tools”, in Proc. of IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’19), 9 -page manuscript, Victoria, BC, Canada, August 2019. 20

    2019

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    HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools

    I.D. Atwell and D.G. Perera, “HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6 -page manuscript, Victoria, BC, Canada, August 2024

    2024

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    Towards Composing Optimized Bi -Directional Multi-Ported Memories for Next-Generation FPGAs

    S.N. Shahrouzi, A. Alkamil, and D.G. Perera, “Towards Composing Optimized Bi -Directional Multi-Ported Memories for Next-Generation FPGAs”, IEEE Access, Open Access Journal in IEEE, vol. 8, no. 1, pp. 91531 -91545, 14th May 2020

    2020

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    An Efficient Embedded Multi-Ported Memory Architecture for Next-Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “An Efficient Embedded Multi-Ported Memory Architecture for Next-Generation FPGAs”, in Proceedings of 28th Annual IEEE International Conferences on Application -Specific Systems, Architectures, and Processors, (ASAP’17), pp. 83-90, Seattle, WA, ...

    2017

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    Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs”, in Proceedings of the 31st IEEE International Systems-On-Chip Conference, (SOCC’18), pp. 106-111, Arlington, VA, Sep. 2018

    2018

Pith tools

Reviewed July 15, 2026 · model on record in the stance chip above.