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REVIEW 4 major objections 5 minor 44 references

ADEPT: Architecture-Driven Energy-Efficient CNN Fine-Tuning on PIM Accelerators

T0 review · 4 major / 5 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read ADEPT shows CNN fine-tuning on processing-in-memory accelerators can achieve up to 8.1x lower energy-delay product than full-parameter training with comparable accuracy, by ranking blocks by sensitivity-to-hardware-cost and adapting channel

desk verdict Good hardware-aware fine-tuning idea, but the 8.1x EDP claim compares to AutoRGN, not full-parameter training. read the letter →

arxiv 2607.17371 v1 pith:3SSHBCCA submitted 2026-07-19 cs.AR cs.ET

Pratyush Dhingra , Vibhanshu Sharma , Janardhan Rao Doppa , Partha Pratim Pande This is my paper · ORCID
classification cs.ARcs.ET
keywords processing-in-memoryCNNfine-tuningenergy-delayproductlow-rankadaptationhardware-awareneuralnetworktraininglayerselectioncontinuallearningedgeaccelerators
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that the energy cost of fine-tuning a pre-trained CNN on a processing-in-memory (PIM) accelerator can be cut by nearly an order of magnitude without losing accuracy, if the choice of which blocks to train is driven by the actual hardware cost of training each block rather than by gradient sensitivity alone. The framework, ADEPT, ranks each block by a Sensitivity-EDP Ratio (SER)—the block's relative gradient norm divided by its per-block energy-delay product on the target architecture—and then uses a nested stochastic schedule in which a block's update frequency is proportional to its rank. It pairs this with a channel-wise low-rank adaptation (DCLoRA) that shrinks gradient traffic selectively in channel-dense later layers, while leaving early layers alone because their cost is dominated by stored activations. On four CNN models and multiple datasets, the paper reports up to 8.1x lower energy-delay product than full-parameter fine-tuning, with accuracy within roughly a point of full retraining, and shows the same mechanism extends to continual learning via an on-chip sensitivity refresh.

What carries the argument

Sensitivity-EDP Ratio (SER): a per-block score SER_b = (S_b)^n / (T_b)^m, where S_b = ||g_b||_2 / ||theta_b||_2 (relative gradient norm) and T_b is the block's aggregated energy-delay product from a PIM-specific latency/energy model (Eqs. 4-7, including off-chip DRAM traffic). Nested block-wise training: the ranked blocks form subsets V_k = {B_1,...,B_k}; each mini-batch samples one V_k, so block B_i trains with probability (z-i+1)/z, making update frequency exactly track SER rank. Dynamic Channel-wise LoRA (DCLoRA): low-rank factors A_l (k x k x C_in x r) and B_l (r x C_out x 1 x 1) are added along channels rather than spatial filters, with rank sampled per mini-batch from {8,...,64}; adapt

What would settle it

Run ADEPT on a PIM simulator but replace the pre-computed SER ranking with a ranking recomputed every epoch (or every few mini-batches) from the same sensitivity formula; if the fully-refreshed version beats ADEPT's static ranking by more than a small margin in accuracy at equal EDP, the one-time calibration assumption is falsified. Equivalently, compare the top-k SER block sets between the first epoch and the last epoch under a distribution shift like CIFAR10-c: if they overlap by less than half the blocks, the ranking was not stable.

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Extended reading notes

Core claim

This paper claims that hardware-aware fine-tuning can largely neutralize the off-chip memory bottleneck that dominates CNN fine-tuning on PIM accelerators. Its central object is the SER ranking: each block receives a score S_b^n / T_b^m, where sensitivity S_b is the ratio of gradient norm to parameter norm and training overhead T_b is the block's EDP computed from a memory-system model that includes on-chip communication and off-chip DRAM accesses. Blocks are sorted by SER and arranged into nested subsets; each mini-batch samples one subset, so more-sensitive, cheaper blocks are updated more often and frozen blocks generate no activation or gradient traffic. On the rank side, DCLoRA applies

Load-bearing premise

Everything hinges on a one-time estimate: the framework measures each block's importance from a few initial mini-batches and a static hardware-cost model, and then freezes or trains blocks for the whole run according to that fixed ranking — if those early estimates mislead, the whole accuracy-versus-energy trade-off breaks.

Editorial extensions

If this is right

  • If the results transfer, on-device fine-tuning for federated and continual-learning deployments becomes materially cheaper, since those workloads fine-tune repeatedly rather than once.
  • Layer selection becomes architecture-dependent by construction: the same model will fine-tune different blocks on a memory-centric PIM than on a compute-centric accelerator, because off-chip weight fetches change each block's effective cost.
  • DCLoRA should not be applied uniformly: the paper's per-block EDP analysis shows little benefit in early layers where activations dominate, implying that hardware-aware gating is essential for LoRA-like methods on CNNs.
  • The on-chip controller that implements stochastic freeze/unfreeze and rank sampling adds under 0.5% tile area/power, so the EDP savings are achievable without a host CPU in the loop.
  • The continual-learning variant tracks a full-training baseline within 0.3% accuracy across sequential corruption stages at under 2% extra EDP, suggesting the hardware-aware ranking can be maintained under distribution drift.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: the SER idea is not tied to CNNs or LoRA; any block-structured PEFT method (adapter, pruning mask, or even prompt) could be gated by the same sensitivity-to-hardware-cost ratio, though the paper only demonstrates it for CNN blocks with channel-wise LoRA.
  • Editorial extension: because update probability is a pure function of SER rank, ADEPT's training schedule is effectively 'stochastic depth with hardware-informed survival rates'; this suggests a clean ablation—hold EDP fixed and shuffle the ranking—to isolate how much of the accuracy win comes from the hardware-aware ordering versus from stochastic depth itself.
  • Editorial extension: the calibration assumption could be stress-tested cheaply by recomputing S_b from later epochs and comparing the top-k block sets; if the ranking flips frequently on a drifting distribution, the static version of ADEPT will eventually underperform, which is exactly the scenario the EMA extension addresses.
  • Editorial extension: the reported 8.1x EDP gain is relative to full fine-tuning on the same platform; a deployment would also need to amortize one-time costs (loading the pretrained weights and the calibration pass) across many fine-tuning rounds before the gain materializes.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This paper introduces ADEPT, a hardware-aware framework for fine-tuning CNNs on PIM accelerators. The central idea is a Sensitivity-EDP Ratio (SER) that ranks each CNN block by the ratio of its gradient-based sensitivity to its per-block Energy-Delay Product (EDP) cost. A stochastic nested training scheme then samples blocks for each mini-batch with probability proportional to their SER rank, and a dynamic channel-wise LoRA (DCLoRA) is applied selectively to channel-dense blocks to reduce gradient-memory traffic. The paper claims up to 8.1x lower EDP compared to full-parameter fine-tuning while maintaining comparable accuracy, and also presents a continual-learning extension that refreshes the sensitivity component via on-chip EMA updates. Experiments are carried out across four CNN models, four datasets, and three PIM platforms (PUMA, CIMAT, HuNT) using NeuroSim-based modeling.

Significance. If the central claims are supported, ADEPT is a useful contribution to efficient on-device fine-tuning for PIM architectures. The SER metric is a principled way to make layer selection architecture-aware, and the DCLoRA construction addresses a real mismatch between standard LoRA and CNN weight tensors. The paper is transparent about the hardware models and provides extensive evaluations across models, datasets, and accelerators. The continual-learning extension with EMA-based sensitivity refresh is a thoughtful, low-overhead addition. However, the headline comparison to full-parameter training is not directly measured, and the reported accuracy numbers are inflated by test-set-based rank selection. These issues are load-bearing for the stated contributions, so the empirical support is currently incomplete.

major comments (4)
  1. [§V.E, Fig. 10] The headline claim in the abstract and Key Contribution 3 is that ADEPT achieves up to 8.1x lower EDP than full-parameter fine-tuning (FpT), but no FpT baseline is measured. The EDP comparisons in Fig. 10 are normalized to ADEPT and show AutoRGN, L2F, ADEPT(S), and a uniform DCLoRA baseline; AutoRGN is described as updating all layers 'similar to' FpT, but it also computes per-layer learning rates from gradient/parameter norms, which adds overhead absent from plain FpT. Table VII likewise omits FpT accuracy. The 8.1x figure is therefore only a comparison to AutoRGN, not to FpT. Please add actual FpT measurements (accuracy and EDP on the same platforms) or revise the claim to state the comparison is against AutoRGN.
  2. [§IV.C] The final LoRA rank is selected using test accuracy: 'After fine-tuning, we employ the rank with highest test accuracy in R for inference.' This is a form of test-set leakage. The reported ADEPT accuracies in Table VII are optimistic and do not reflect a deployment scenario where the test set is unavailable. The 'comparable accuracy' claim is therefore not supported for a realistic protocol. The rank should be chosen on a validation split, or the paper should report accuracy for a fixed rank (e.g., the largest rank) and show that the test-selected rank does not materially change the conclusions.
  3. [§V.A, Table VII, Figs. 9-11] All accuracy and EDP results are point estimates with no repeated-seed variance, confidence intervals, or significance tests. In Table VII, ADEPT and AutoRGN differ by only 0.1-0.5 percentage points in several configurations; without a variance estimate, the claimed 'comparable accuracy' could be noise. Likewise, the EDP ratios in Figs. 9-11 come from single runs of the calibration pass, and the sensitivity estimates in Eq. (3) are computed from a small number of mini-batches, so the resulting SER ranking could vary across initializations. At minimum, report three to five seeds for a representative subset (e.g., ResNet-18 on CIFAR10, CIFAR10-c, and Entity-30) and show the ranges for Table VII and the EDP figures.
  4. [§IV.A, Algorithm 1, Table IX] The SER priority map is computed once during a short calibration pass and never updated during static fine-tuning. The continual-learning experiments in Table IX demonstrate that the sensitivity profile drifts across corruption stages, which raises the concern that it may also drift within a single fine-tuning task. If the initial gradient-norm ratios are unrepresentative of later iterations, the stochastic freezing pattern is misdirected and the claimed accuracy/EDP trade-off weakens. Please provide an ablation in which the SER map is recomputed mid-training (or compare the static SER against an oracle that re-ranks periodically) to show that the one-time calibration is sufficient.
minor comments (5)
  1. [Eq. (11)] The parameter-reduction ratio expression is hard to parse: the parentheses and the 'r/(k)^2' term need clarification. State more explicitly that C_in = C_out = C and rewrite the ratio with unambiguous parentheses.
  2. [Fig. 6] The y-axis is normalized independently per architecture, so the reader cannot compare absolute EDP between PUMA and TPU. Add an explicit statement in the caption that each architecture is normalized to its own Ip.conv EDP.
  3. [Table VII] The table is dense and the row/column structure is difficult to follow. Consider splitting into separate tables per model or adding boldface/color to distinguish metrics and baselines.
  4. [§V.E] The caption for Fig. 10 says 'Normalized EDP of ADEPT and baseline fine-tuning techniques' but the legend includes ADEPT(S) and a uniform DCLoRA baseline; make the normalization reference explicit to avoid confusion.
  5. [§IV.E, Eq. (12)] The EMA update in Eq. (12) is written as S_b ← S_b + (1-λ)(x_b - S_b). This is algebraically correct, but the subsequent sentence says 'with S_b initialized during the one-time calibration step' while also using λ; the notation λ and k should be defined immediately before first use in the equation.

Circularity Check

0 steps flagged · score 2.0 of 10

No circularity in the SER/EDP derivation chain; the main caveats are a missing FpT baseline and test-set rank selection, which are external-validity issues rather than circular reductions.

full rationale

ADEPT's central derivation is not circular. SER (Eq. 1) is defined as S_b^n / T_b^m, where sensitivity S_b is a gradient-norm ratio (Eq. 3) and training overhead T_b is an independently modeled EDP cost (Eqs. 4-7). The block priority map is computed from these quantities, and the resulting fine-tuned accuracy and EDP are measured after training against external baseline methods (AutoRGN, L2F, GF, ADEPT(S), uniform-DCLoRA) using NeuroSim-based cost characterization and standard accuracy benchmarks. Accuracy is not algebraically derivable from the SER definition; it is an empirical outcome. The fact that the selection objective includes EDP and the evaluation metric is also EDP is a design objective, not a tautology, because the non-trivial claim is that comparable accuracy is retained. The main weaknesses are correctness/validity concerns, not circularity: the headline '8.1x lower EDP compared to full-parameter fine-tuning' is actually supported by measurements against AutoRGN in Section V.E / Figs. 10-11, with FpT absent from Table VII; and Section IV.C selects the deployed LoRA rank using test accuracy, which biases the reported accuracy comparison. These affect interpretation of the evidence but do not make the derivation equivalent to its inputs. Two self-citations ([32], [44]) appear only in supporting architectural statements and are corroborated by external references ([13], [31]); no load-bearing self-citation chain or imported uniqueness theorem is invoked.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claims rest on the accuracy of the EDP model, the representativeness of one-time gradient sensitivity estimates, and the low-rank assumption for convolutional weight updates. None of these are proven; they are domain assumptions inherited from prior work or introduced by the framework. No new physical entities are postulated.

free parameters (5)
  • SER exponents n,m = n=m=1
    User-tunable exponents in Eq. 1; balanced default chosen after the hyperparameter sweep in Section V.D (Table VI, Fig. 8).
  • DCLoRA gating threshold T_r = 2x EDP reduction
    User-specified threshold for selectively applying DCLoRA; set conservatively to 2x in Section V.A.
  • LoRA rank range R = {8,16,32,64}
    User-specified dynamic rank range; final inference rank is chosen by the highest test accuracy (Section IV.C, V.A).
  • EMA smoothing factor lambda = 0.5 (k=1)
    Power-of-two smoothing for the continual-learning sensitivity update; chosen for multiplier-free implementation (Section IV.E, V.F).
  • Learning rates per model/dataset = [0.05,0.01,0.001,0.005], best reported
    Learning rates swept per dataset and best accuracy reported (Table I), adding a target-data-dependent selection.
assumptions (5)
  • domain assumption Gradient-norm ratio S_b = ||g_b||_2 / ||theta_b||_2 identifies blocks that need adaptation for a given distribution shift.
    Eq. 3; inherited from AutoRGN / surgical fine-tuning literature; no proof that ranking by this metric optimizes fine-tuning accuracy.
  • domain assumption The EDP model T_b (Eqs. 4-7) accurately captures per-block training cost on the target PIM architecture, including the architecture-specific constants alpha and beta.
    Section IV.B; alpha/beta are said to account for utilization, tiling, and mapping overheads, but their values are not reported; relies on NeuroSim calibration.
  • domain assumption One-time calibration sensitivities remain valid throughout fine-tuning and are representative of the full training distribution.
    Algorithm 1 Lines 1-7; no empirical check that early sensitivity ranking tracks later shifts in the standard fine-tuning setting.
  • domain assumption Channel-wise low-rank decomposition of convolutional weights (DCLoRA) can represent the needed weight updates with small rank.
    Section IV.C; standard LoRA assumption applied to the channel dimension; no rank-accuracy bound is given.
  • domain assumption Stochastically freezing blocks via uniform sampling over the nested set V preserves convergence comparable to full training because update frequencies are SER-proportional.
    Section IV.A; analogous to stochastic depth [34], but no convergence guarantee is provided for this EDP-weighted sampling.

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Cite this review

Pith. "Pith review of ADEPT: Architecture-Driven Energy-Efficient CNN Fine-Tuning on PIM Accelerators." pith.science (2026). https://pith.science/paper/3SSHBCCA

@misc{pith2026260717371,
  author       = {Pith},
  title        = {Pith review of: ADEPT: Architecture-Driven Energy-Efficient CNN Fine-Tuning on PIM Accelerators},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3SSHBCCA}},
  note         = {Machine review of arXiv:2607.17371}
}
read the original abstract

Processing-in-memory-based (PIM) architectures have emerged as a promising solution for accelerating Convolutional Neural Network (CNN) workloads at the edge. Fine-tuning pre-trained CNNs is a common requirement to enhance the model predictive accuracy after deployment. However, the fine-tuning process is computational and memory-intensive, generating a significant amount of intermediate activations. This leads to frequent off-chip memory access, affecting the overall efficiency of the PIM accelerator. Existing fine-tuning strategies are agnostic to the underlying hardware, as they treat all layers equally. In this paper, we propose a hardware-aware framework called ADEPT to accelerate CNN fine-tuning on PIM architectures. Unlike prior fine-tuning methods, ADEPT adaptively trains the model considering both the training overhead and layer sensitivity. Specifically, ADEPT introduces a novel metric that quantifies the trade-off between a block's gradient-based sensitivity and its hardware architecture-specific Energy-Delay Product (EDP), producing platform-dependent fine-tuning configurations. Overall, ADEPT helps reduce the total trainable parameters and the off-chip data access during fine-tuning, while incurring minimal loss in predictive accuracy compared to full-parameter fine-tuning.

Figures

Figures reproduced from arXiv: 2607.17371 by the authors.

Figure 1
Figure 1. The intermediate size of output activations and weights for input conv (Ip.conv), each conv block and the FC layer in ResNet-18. 0.001 0.01 0.1 1 10 100 Ip.Conv Block-1 Block-2 Block-3 Block-4 FC Normalized Data Size Activations Weights [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. A conceptual illustration of the PIM processing element (PE) and memory hierarchy. PIM PEs can be homogeneous or heterogeneous based on the architecture. Input Circuitry Output Circuitry Core Core Core Core Buffers Tile Tile Tile Tile Cache Act. Unit Off-chip Memory (DRAM/HBM) Control Logic Peripherals Register File I/O Misc. units Core Tile PE [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. High-level illustration of the fine-tuning pipeline employing ADEPT for a mini-batch. The back-propagation computation generates gradients only for the trainable parameters uniformly sampled from 𝑉. In this illustration, these include the LoRA parameters (𝐴 3 and 𝐵 3 ) for the last conv block and the weights (𝑊4 ) for the FC layer. Frozen Layers Trainable Layers Input Forward Phase Backward Phase DCLoRA weights Conv… view at source ↗

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Reference graph

Works this paper leans on

44 extracted references · 1 canonical work pages

  1. [1]

    A Survey of Convolutional Neural Networks: Analysis, Applications, and Prospects,

    Z. Li et al. , “A Survey of Convolutional Neural Networks: Analysis, Applications, and Prospects,” IEEE Trans. Neural Netw. Learn. Syst., vol. 33, no. 12, Dec. 2022

    2022

  2. [2]

    Review of deep learning: concepts, CNN architectures, challenges, applications, future directions,

    L. Alzubaidi et al. , “Review of deep learning: concepts, CNN architectures, challenges, applications, future directions,” J. Big Data , vol. 8, no. 1, Mar. 2021

    2021

  3. [3]

    Are vision transformers more data hungry than newborn visual systems?,

    L. Pandey, S. Wood, J. Wood, “Are vision transformers more data hungry than newborn visual systems?,” Adv. Neural Inf. Process. Syst. , vol. 36, 2023

    2023

  4. [4]

    Edge Intelligence: Empowering Intelligence to the Edge of Network,

    D. Xu et al., “Edge Intelligence: Empowering Intelligence to the Edge of Network,” Proc. IEEE, vol. 109, no. 11, Nov. 2021

    2021

  5. [5]

    Parameter-efficient fine-tuning of large-scale pre-trained language models,

    N. Ding et al., “Parameter-efficient fine-tuning of large-scale pre-trained language models,” Nat. Mach. Intell., vol. 5, no. 3, Mar. 2023

    2023

  6. [6]

    Survey: federated learning data security and privacy-preserving in edge-Internet of Things,

    H. Li, L. Ge, L. Tian, “Survey: federated learning data security and privacy-preserving in edge-Internet of Things,” Artif. Intell. Rev., vol. 57, no. 5, 2024

    2024

  7. [7]

    Communication-efficient learning of deep networks from decentralized data,

    B. McMahan et al., “Communication-efficient learning of deep networks from decentralized data,” in Artificial intelligence and statistics , Pmlr, 2017

    2017

  8. [8]

    A Comprehensive Survey of Continual Learning: Theory, Method and Application,

    L. Wang et al., “A Comprehensive Survey of Continual Learning: Theory, Method and Application,” IEEE Trans. Pattern Anal. Mach. Intell. , vol. 46, no. 8, Aug. 2024

    2024

Show all 44 references
  1. [9]

    PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy -Efficient ReRAM,

    A. Ankit et al., “PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy -Efficient ReRAM,” IEEE Trans. Comput., vol. 69, no. 8, Aug. 2020

    2020

  2. [10]

    Compute -in-Memory Chips for Deep Learning: Recent Trends and Prospects,

    S. Yu et al. , “Compute -in-Memory Chips for Deep Learning: Recent Trends and Prospects,” IEEE Circuits Syst. Mag., vol. 21, no. 3, 2021

    2021

  3. [11]

    Architectures and Circuits for Analog -memory-based Hardware Accelerators for Deep Neural Networks (Invited),

    H. Tsai et al. , “Architectures and Circuits for Analog -memory-based Hardware Accelerators for Deep Neural Networks (Invited),” in 2023 IEEE International Symposium on Circuits and Systems (ISCAS) , IEEE, May 2023

    2023

  4. [12]

    MobileNetV2: Inverted Residuals and Linear Bottlenecks,

    M. Sandler et al. , “MobileNetV2: Inverted Residuals and Linear Bottlenecks,” in 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, IEEE, June 2018

    2018

  5. [13]

    DNN+NeuroSim V2.0: An End -to-End Benchmarking Framework for Compute -in-Memory Accelerators for On -Chip Training,

    X. Peng et al., “DNN+NeuroSim V2.0: An End -to-End Benchmarking Framework for Compute -in-Memory Accelerators for On -Chip Training,” IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. , vol. 40, no. 11, Nov. 2021

    2021

  6. [14]

    Efficient On -Device Training via Gradient Filtering,

    Y. Yang, G. Li, R. Marculescu, “Efficient On -Device Training via Gradient Filtering,” in 2023 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), IEEE, June 2023

    2023

  7. [15]

    Universal language model fine -tuning for text classification,

    J. Howard, S. Ruder, “Universal language model fine -tuning for text classification,” in Proceedings of the 56th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers) , 2018

    2018

  8. [16]

    Distilling BERT into Simple Neural Networks with Unlabeled Transfer Data,

    S. Mukherjee, A. H. Awadallah, “Distilling BERT into Simple Neural Networks with Unlabeled Transfer Data,” July 23, 2020, arXiv: arXiv:1910.01769. doi: 10.48550/arXiv.1910.01769

    2020 doi arXiv

  9. [17]

    What is being transferred in transfer learning?,

    B. Neyshabur, H. Sedghi, C. Zhang, “What is being transferred in transfer learning?,” Adv. Neural Inf. Process. Syst., vol. 33, 2020

    2020

  10. [18]

    Deep Residual Learning for Image Recognition,

    K. He et al., “Deep Residual Learning for Image Recognition,” in 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), IEEE, June 2016

    2016

  11. [19]

    In -Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview,

    K. Roy et al. , “In -Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview,” in 2020 57th ACM/IEEE Design Automation Conference (DAC), IEEE, July 2020

    2020

  12. [20]

    ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars,

    A. Shafiee et al., “ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars,” in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) , IEEE, June 2016

    2016

  13. [21]

    HuNT: Exploiting Heterogeneous PIM Devices to Design a 3 -D Manycore Architecture for DNN Training,

    C. Ogbogu et al. , “HuNT: Exploiting Heterogeneous PIM Devices to Design a 3 -D Manycore Architecture for DNN Training,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 43, no. 11, Nov. 2024

    2024

  14. [22]

    Hybrid RRAM/SRAM in -Memory Computing for Robust DNN Acceleration,

    G. Krishnan et al., “Hybrid RRAM/SRAM in -Memory Computing for Robust DNN Acceleration,” IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst., vol. 41, no. 11, Nov. 2022

    2022

  15. [23]

    Surgical fine -tuning improves adaptation to distribution shifts,

    Y. Lee et al., “Surgical fine -tuning improves adaptation to distribution shifts,” ArXiv Prepr. ArXiv221011466, 2022

    2022

  16. [24]

    Deep residual learning for image recognition: A survey,

    M. Shafiq, Z. Gu, “Deep residual learning for image recognition: A survey,” Appl. Sci., vol. 12, no. 18, 2022

    2022

  17. [25]

    SpotTune: Transfer Learning Through Adaptive Fine - Tuning,

    Y. Guo et al. , “SpotTune: Transfer Learning Through Adaptive Fine - Tuning,” in 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), IEEE, June 2019

    2019

  18. [26]

    Automatic layer selection for transfer learning and quantitative evaluation of layer effectiveness,

    S. Nagae et al. , “Automatic layer selection for transfer learning and quantitative evaluation of layer effectiveness,” Neurocomputing, vol. 469, 2022

    2022

  19. [27]

    Lora: Low-rank adaptation of large language models.,

    E. J. Hu et al., “Lora: Low-rank adaptation of large language models.,” Iclr, vol. 1, no. 2, 2022

    2022

  20. [28]

    Few -shot parameter -efficient fine -tuning is better and cheaper than in-context learning,

    H. Liu et al. , “Few -shot parameter -efficient fine -tuning is better and cheaper than in-context learning,” Adv. Neural Inf. Process. Syst., vol. 35, 2022

    2022

  21. [29]

    Language models are few -shot learners,

    T. Brown et al., “Language models are few -shot learners,” Adv. Neural Inf. Process. Syst., vol. 33, 2020

    2020

  22. [30]

    Lora-c: Parameter-efficient fine-tuning of robust cnn for iot devices,

    C. Ding et al., “Lora-c: Parameter-efficient fine-tuning of robust cnn for iot devices,” ArXiv Prepr. ArXiv241016954, 2024

    2024

  23. [31]

    PipeLayer: A Pipelined ReRAM -Based Accelerator for Deep Learning,

    L. Song et al., “PipeLayer: A Pipelined ReRAM -Based Accelerator for Deep Learning,” in 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), IEEE, Feb. 2017

    2017

  24. [32]

    FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators,

    P. Dhingra et al., “FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, Mar. 2024

    2024

  25. [33]

    Improving neural networks by preventing co - adaptation of feature detectors,

    G. E. Hinton et al. , “Improving neural networks by preventing co - adaptation of feature detectors,” ArXiv Prepr. ArXiv12070580, 2012

    2012

  26. [34]

    Deep networks with stochastic depth,

    G. Huang et al. , “Deep networks with stochastic depth,” in European conference on computer vision, Springer, 2016

    2016

  27. [35]

    DyLoRA: Parameter-efficient tuning of pre -trained models using dynamic search-free low-rank adaptation,

    M. Valipour et al., “DyLoRA: Parameter-efficient tuning of pre -trained models using dynamic search-free low-rank adaptation,” in Proceedings of the 17th Conference of the European Chapter of the Association for Computational Linguistics, 2023

    2023

  28. [36]

    Learning ordered representations with nested dropout,

    O. Rippel, M. Gelbart, R. Adams, “Learning ordered representations with nested dropout,” in International Conference on Machine Learning , PMLR, 2014

    2014

  29. [37]

    CIMAT: A Compute -In-Memory Architecture for On - chip Training Based on Transpose SRAM Arrays,

    H. Jiang et al., “CIMAT: A Compute -In-Memory Architecture for On - chip Training Based on Transpose SRAM Arrays,” IEEE Trans. Comput., 2020

    2020

  30. [38]

    PUMA: A Programmable Ultra -efficient Memristor - based Accelerator for Machine Learning Inference,

    A. Ankit et al. , “PUMA: A Programmable Ultra -efficient Memristor - based Accelerator for Machine Learning Inference,” in Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, Apr. 2019

    2019

  31. [39]

    ShuffleNet: An Extremely Efficient Convolutional Neural Network for Mobile Devices,

    X. Zhang et al. , “ShuffleNet: An Extremely Efficient Convolutional Neural Network for Mobile Devices,” in 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition, IEEE, June 2018

    2018

  32. [40]

    ImageNet: A large-scale hierarchical image database,

    J. Deng et al., “ImageNet: A large-scale hierarchical image database,” in 2009 IEEE Conference on Computer Vision and Pattern Recognition , IEEE, June 2009

    2009

  33. [41]

    JESD235D JEDEC Standard, High Bandwidth Memory DRAM (HBM1, HBM2)

    JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, “JESD235D JEDEC Standard, High Bandwidth Memory DRAM (HBM1, HBM2).” 2021

    2021

  34. [42]

    TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings,

    N. Jouppi et al., “TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings,” in Proceedings of the 50th Annual International Symposium on Computer Architecture, ACM, June 2023. 14 > REPLACE THIS LINE WITH YOUR MANUSCRIPT ID N...

    2023

  35. [43]

    JESD209 - 5C, Low Power Double Data Rate (LPDDR) 5/5X

    JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, “JESD209 - 5C, Low Power Double Data Rate (LPDDR) 5/5X.” 2021

    2021

  36. [44]

    Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures,

    P. Dhingra, J. R. Doppa, P. P. Pande, “Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures,” IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. , vol. 44, no. 8, Aug. 2025. Pratyush Dhingra (Graduate Student Member, IEEE) is cur...

    2025

Pith tools

Reviewed August 1, 2026 · model on record in the stance chip above.