DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

Changxi Liu; Trevor E. Carlson; Yun Chen

REVIEW 4 major objections 6 minor 55 references

DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

T0 review · 4 major / 6 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read DGNA uses one SM to warm L2 and another to time it, exposing a two-node NUMA memory layout on A100 and H100 GPUs.

desk verdict Credible first map of A100/H100 L2/DRAM NUMA, but the load-bearing no-prefetch assumption needs a control and some structural claims are underdetermined. read the letter →

arxiv 2607.19922 v1 pith:73OX46JU submitted 2026-07-22 cs.AR

Changxi Liu , Yun Chen , Trevor E. Carlson This is my paper

classification cs.AR

keywords GPUmicrobenchmarkingNUMAarchitectureL2cacheDRAMlatencyGaussianmixturemodelNVIDIAA100H100coherence

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces DGNA, a microbenchmarking and data-analysis method that reconstructs the memory topology of closed-source GPUs. Applied to NVIDIA's A100 and H100, it shows that the L2 cache and DRAM are split into two non-uniform access regions (NUMA nodes), with distinct latencies of 385 vs 546 cycles for A100 DRAM and 554 vs 728 cycles for H100 DRAM. It further shows L2 fills follow a first-touch policy, that the H100 has four sub-NUMA regions inside its L2, and that SMs and GPCs map to these regions in specific, partly imbalanced ways. The method also reveals how reads and writes behave when the accessing SM is on the home node versus a remote node. A sympathetic reader would care because it turns a black-box GPU into a measurable NUMA system, which matters for memory placement optimizations and for building accurate simulators.

What carries the argument

The load-bearing mechanism is the two-SM latency probe: one SM reads a data block to fill the shared L2 (and its own private L1), then a different SM times a read of the same block, so the timed access must come from L2, not the first SM's L1. The resulting latency distributions are separated with a Gaussian mixture model that removes outliers from DRAM refresh, TLB misses, and other noise; K-means clustering of per-address latency feature vectors then groups SMs into NUMA nodes and sub-NUMA nodes.

What would settle it

Run the two-SM probe on a kernel that warms L2 with SM A, then before SM B reads, issue a long stream of sequential reads on SM C over unrelated addresses; if a hardware prefetcher exists, SM B's measured latency for the original block will drop or show a third latency component, which the no-prefetch model cannot explain. Alternatively, use performance counters (e.g., lts__t_sectors or l1tex__t_sectors) to count L2 fills during the warmup phase and check whether fills occur before SM B's access.

Watch

Extended reading notes

Core claim

The central claim is that the memory hierarchy of the A100 and H100 is physically non-uniform below the shared-L2 level: there are two DRAM NUMA nodes and two L2 NUMA nodes, and on the H100 each L2 node contains two sub-NUMA nodes. Using a two-SM probe (one SM warms the L2, another SM times the access), the paper derives latency distributions after Gaussian-mixture outlier filtering: local/remote DRAM latencies of 385/546 cycles (A100) and 554/728 cycles (H100), and local/remote L2 latencies of 218/379 and 295/470 cycles. It concludes that L2 placement follows a first-touch mechanism, that the 32-cycle sub-NUMA gap on H100 is an effect of the larger 50 MB L2, and that GPC-to-node mapping is

Load-bearing premise

The entire argument rests on the claim that the A100 and H100 do not prefetch data into L2 ahead of the measurement reads; the paper asserts 'based on our observations' but presents no such observation, and if prefetching occurs the second SM's timed latency reflects where the prefetcher placed the block, not where the warmup SM's first-touch placed it.

Editorial extensions

If this is right

If correct, NUMA-aware allocation on A100/H100 (placing pages on the local DRAM node for a given SM) should cut average DRAM latency by roughly 160 cycles on A100 and 175 on H100.
The first-touch placement rule implies the SM that touches a page first determines its L2 home node; schedulers and runtime systems can influence this.
The revealed read/write behavior gives a concrete model for cache coherence traffic: remote writes invalidate or update multiple L2 nodes depending on hit location, which affects power and performance.
The floorsweeping imbalance found on A100 (46/62 SM split) explains asymmetric behavior across GPCs and suggests die-harvesting differences between vendor parts.
The method's independence from vendor intrinsics means it can be rerun on new GPUs (the paper demonstrates an RTX 5090 case) without trusting undocumented instructions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The two-SM probe should transfer to other multi-GPU or chiplet systems: any hierarchy with private per-core caches and a shared last level can be mapped the same way.
The identified sub-NUMA split on H100 suggests that as L2 grows, vendors may partition it further; latency-vector clustering would generalize DGNA to three or more nodes without redesign.
One testable consequence left implicit: if first-touch placement is real, deliberately touching a page with a remote SM before the compute SM should swap which node is 'home'; the paper's write experiments hint at this but do not measure the swapped topology directly.
The prefetch-absence assumption could be stress-tested by comparing DGNA's measured L2 latencies against a stream of purely sequential reads: a hardware prefetcher would raise the fraction of short-latency L2 hits in a way the current model does not predict.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague — this one is worth a look. The headline: DGNA gives a clean, credible microbenchmarking method to infer L2/DRAM NUMA topology on A100/H100, and produces the first empirical map of that topology, including an H100 sub-NUMA tier. The central bimodal latency evidence looks real; what's shakier is how much of the physical structure the authors claim to reconstruct from it.

What's genuinely new: the pairwise SM warmup/measure trick (one SM touches the line, another times it) neatly sidesteps L1 and vendor intrinsics, and the GMM-based outlier filtering is a thoughtful way to handle DRAM refresh and TLB noise. The specific numbers — 385/546-cycle DRAM and 218/379-cycle L2 on A100, 554/728 and 295/470 on H100, plus the 32-cycle sub-NUMA gap and the 4KB/8KB allocation formula — are the kind of facts the field has been lacking. The read/write mechanism analysis is a nice attempt at coherence-level inference, even if the evidence there is thinner.

The soft spots are real but not all equal. The biggest is the no-prefetch assumption. It's stated in Section 4 as an assumption and defended with reasonable arguments, but the paper later asserts the A100/H100 lack prefetchers 'based on our observations' without showing what those observations were. A prefetching control would be straightforward — e.g., compare timing of a single line vs. a stride that would trigger prefetch — and it matters because the first-touch and allocation conclusions assume the measured latency reflects exactly one explicit fetch. Without it, the bimodal distributions are still compatible with some prefetch placement, though I'd bet on the authors' interpretation.

Second, the structural inventory — sub-NUMA nodes, GPC-to-node mapping, write mechanism — is largely derived from clustering the same latency features the clusters are built from. The raw bimodality is direct evidence; the labeling of which component corresponds to 'remote' vs 'local' involves post-hoc interpretation. That's not fatal, but the paper should be more careful about what is measured vs. inferred.

Third, craft issues: a broken '??' reference in Section 5.4, Table 5 has no variance or error bars, and code isn't released yet. All fixable.

Who should read it: anyone working on GPU memory systems, coherence, or simulation. It deserves a serious referee, and I'd send it with the expectation of revision — ask for the prefetch control, released code/data, error bars, and a cleaned-up write-mechanism section. If those land, this will be a useful reference for years.

My recommendation: engage. Bring it to the next reading group; the methodology debate is worth the time.

Referee Report

4 major / 6 minor

Summary. The paper introduces DGNA, a microbenchmarking methodology intended to reveal the NUMA architecture of the L2 cache and DRAM in NVIDIA GPUs. The core technique uses one SM to warm up a cache block and a second SM to measure access latency, avoiding vendor-specific load intrinsics. A Gaussian mixture model (GMM) is then used to remove outliers and to identify latency components, after which K-Means clustering of feature vectors assigns SMs to DRAM, L2, and (on H100) sub-L2 NUMA nodes. On A100 and H100 the paper reports two DRAM NUMA nodes and two L2 NUMA nodes with latency pairs (385/546 and 218/379 cycles on A100; 554/728 and 295/470 cycles on H100), a first-touch allocation mechanism, an H100-specific sub-NUMA structure with a 32-cycle gap, and read/write coherence behavior summarized in Table 5. The paper also reports applying the same methodology to an RTX 5090. The authors conclude that they are the first to detail NUMA architecture inside the GPU memory subsystem.

Significance. If the conclusions hold, this is a useful contribution: it would give the community a non-intrinsic measurement approach and concrete evidence that commercial GPUs expose non-uniform L2/DRAM latencies at the granularity of SMs and GPCs. The raw bimodality shown in Figures 4 and 5 is an interesting observation in itself, and the latency-gap argument connecting L2 and DRAM NUMA overheads is plausible. The paper also generalizes to a third GPU, which strengthens the empirical basis. However, the high-level architectural claims go beyond the raw bimodality and depend on several unverified assumptions, most importantly the lack of hardware prefetching. The absence of artifact or machine-checked verification, combined with the post-hoc nature of several analysis choices, currently limits reproducibility. With additional control experiments and robustness analysis, the methodology could become a valuable tool for GPU architecture research.

major comments (4)

[Section 4.1, Listing 1] The no-prefetch assumption is load-bearing for the causal interpretation, not a minor caveat. Section 4 states 'DGNA assumes that GPUs do not employ hardware prefetching,' and Section 4.1 later asserts, without showing the supporting observation, that 'the A100 and H100 GPUs lack prefetch mechanisms.' In TestLatencies, SM_warmup touches address i and SM_measure times the next access; if the hardware prefetches the next line or the next loop iteration into L2, the measured latency reflects prefetched placement, not the explicit first-touch placement. That would invalidate the first-touch mechanism of Section 5.3, the DRAM NUMA allocation formula, and the read-after-write classification in Table 5. I ask the authors to add a direct prefetch probe, for example by comparing timings of sequentially accessed lines with randomly accessed lines, or by touching only odd/even lines and timing the
[Section 4.1, Eq. (1), and Section 5.2, Fig. 4] The 'two distinct means' conclusion is conditioned on a chain of post-hoc modeling choices: the number of GMM components K, the shared-variance approximation Σ0, and the 3-sigma outlier cutoff. The sensitivity is visible in the paper itself: for H100 the second DRAM mean changes from 759 cycles in the raw data to 728 cycles after filtering, a nontrivial 31-cycle shift. The paper provides no test of whether K=2 is preferred over K=1 or K=3, and no justification that the shared-variance model is appropriate given that the text admits remote-access variances are more unstable. Please add a robustness analysis varying K, the outlier threshold, and the variance model, and report goodness-of-fit or model-selection criteria. Without this, the claimed bimodality could be an artifact of the filter rather than a property of the hardware.
[Section 4.2, Sections 5.3, Table 3 and Table 4] There is a circularity risk in the topology reconstruction: the same latency distributions are first used to infer the existence of NUMA nodes and then clustered to assign SMs to those nodes, so the 'reconstruction' partially restates the clustering. The paper asserts in Section 4.2 that 'the mapping between allocated virtual pages and NUMA nodes remains stable after resetting the device' and leverages it to remove virtual-memory effects, but this stability is not demonstrated. To break the circularity, I would like to see an independent validation: for example, hold out a set of memory addresses, predict their NUMA node using the inferred formula, and verify the prediction against latency measurements that were not used in fitting. Currently the K-Means feature-vector groups are unlabeled clusters whose interpretation as NUMA nodes is assumed rather than tested.
[Section 5.2, Figs. 7 and 10, and Table 4] The existence of H100 'sub-NUMA nodes' is a headline new finding, but the evidence is only a bimodal distribution of local-L2 access latencies (280 vs. 312 cycles) plus latency differences across SM pairs. This pattern could also be produced by L2 slice/bank mapping, a physical address hash, or another microarchitectural effect. The conclusion that NVIDIA implemented a sub-NUMA microarchitecture within each L2 NUMA node therefore needs an independent test, such as demonstrating a consistent address-interleaving rule that maps a given offset to a predicted subgroup and verifying it on unseen addresses, or cross-checking with an NVIDIA-documented feature. The current support is suggestive but not conclusive, and this claim is too prominent in the abstract and conclusion to rest on a single bimodal fit.

minor comments (6)

[Listing 1] The code has a compilation-inconsistent name: the macro is defined as LDCG_TEST_READ, but the branch at line 16 tests LDCG_TEST_LOAD. Please make the names consistent.
[Section 5.4] The sentence 'Using the NUMA allocation results in ??, we can control...' contains an unresolved cross-reference ('??').
[Section 4.1] Typo: 'TBL misses' should be 'TLB misses'. Also, 'Additionaly' in the introduction and 'clusterred' in the caption of Figure 4 should be corrected.
[References] References [40] and [41] appear to be duplicate entries for the same HMG paper; please merge or disambiguate.
[Figure 1] The caption says 'The L2 latencies measured by __ldcg [16, 21] and DGNA on the A100 show clear gaps,' but the two curves are not labeled in the figure. Adding a legend and explicitly noting which curve corresponds to which method would improve clarity.
[Section 5.2 (RTX 5090)] The RTX 5090 result is presented without the same configuration details as A100/H100 (L2 size, SM count, driver version, measurement conditions). Since this is an additional data point and a different architecture generation, please include a brief setup description.

Circularity Check

1 steps flagged · score 2.0 of 10

Mild definitional labeling of GMM clusters as NUMA nodes; the core measurements are empirical but the no-prefetch premise is unverified.

self definitional [Section 4 (Eq. 1) and Section 5.2]
"Assume that latencies are only influenced by NUMA architecture, the latency distribution can be modeled as a Gaussian mixture... Since we assume that NUMA architecture is the primary factor influencing latencies, the means μ_i represent the latencies of different SMs accessing various NUMA nodes... The DRAM latencies on GPUs exhibit a mixed Gaussian distribution, with two distinct means observed for each architecture: 385 cycles and 546 cycles for the A100... Accessing DRAM through a local L2 NUMA node results in lower latencies, while accessing it through a remote L2 NUMA node incurs higher l"

The GMM is fit to the latency measurements, so the two extracted means are by construction the two fitted components of the latency distribution. Labeling these fitted means as 'local L2 NUMA node' and 'remote L2 NUMA node' latencies, and then presenting the two-mean distribution as evidence of a two-node NUMA architecture, restates the clustering as a discovery rather than independently verifying that the two latency classes correspond to physical NUMA nodes. The raw bimodality is real evidence of two latency classes, but the NUMA-node interpretation is an assumption encoded in Eq. (1), not a separate finding. This is a mild definitional circularity, not a forced result.

full rationale

The paper's central latency measurements are empirical and not circular: the warmup/measure SM-pair procedure, the GMM outlier filtering, and the K-Means grouping are applied to raw timing data, and the read/write mechanism experiments use controlled warmup combinations. There are no self-citations or fitted parameters that are later renamed as predictions. The main circularity concern is interpretive: the GMM components are defined, via Eq. (1), as latencies of accesses to different NUMA nodes, and the later 'two NUMA nodes' conclusion is largely a restatement of the two fitted means. This lowers the score but does not invalidate the raw latency distributions. A separate, non-circular correctness risk is the load-bearing no-prefetch assumption: Section 4 states 'DGNA assumes that GPUs do not employ hardware prefetching,' while Section 4.1 claims 'based on our observations, the A100 and H100 GPUs lack prefetch mechanisms' without presenting the observation. This is an unsupported premise that affects the first-touch and allocation interpretations, but it is not itself a circular derivation.

Assumptions & free parameters 5 free parameters · 5 assumptions · 1 invented entities

The central contribution is an interpretive reconstruction from latency measurements. The main modeling inputs are the no-prefetch assumption, the GMM decomposition, the K-Means cluster counts, and the address-interleaving formula. These are reasonable tools for black-box reverse engineering, but each is fit to the same data that is later described as architectural discovery.

free parameters (5)

GMM component means μ_i for each architecture and memory level = A100 DRAM: 385/546; A100 L2: 218/379; H100 DRAM: 554/728; H100 L2: 295/470; H100 sub-L2: 280/312; RTX 5090 DRAM: 922 (cy
Fitted to latency histograms by Gaussian mixture; these are the paper's central quantitative outputs, so their interpretation as 'true' latencies depends on model assumptions.
GMM shared-variance parameter Σ₀ and 3σ outlier cutoff = not reported numerically
Uses Σ₀ for all components and removes latencies > μ_K + 3Σ; changing the cutoff changes reported means (H100 remote DRAM mean shifts from 759 to 728 cycles after filtering).
Number of GMM components K and K-Means cluster counts = K=2 for DRAM/L2; 2 then 4 clusters for H100 sub-NUMA
Component/cluster counts are determined from the data; the clusters are then labeled as NUMA or sub-NUMA nodes without external validation.
H100 DRAM interleaving formula parameters = ID_NUMA = ⌊(x+1−H(x−8))/2⌋ mod 2, with x=⌊(addr mod 64KB)/4KB⌋
Compact empirical fit to the address-offset latency pattern in Figure 8; it describes the data but is not an independently measured spec.
A100 8KB NUMA alternation span = 8KB
Inferred from Figure 8(a); exact boundary and granularity are not otherwise justified.

assumptions (5)

domain assumption A100 and H100 do not employ hardware prefetching
Section 4 opening says 'DGNA assumes that GPUs do not employ hardware prefetching'; if false, warmup/measure reads may be affected by fetch-ahead, so second-SM latency would not isolate explicitly placed data.
ad hoc to paper After outlier removal, all remaining latency variation is due to NUMA architecture
Eq. (1) is justified by 'Assume that latencies are only influenced by NUMA architecture'; other sources (TLB, refresh, frequency) are treated as removable noise, not modeled.
domain assumption cudaDeviceReset yields a stable virtual-page-to-NUMA mapping and clears all caches
Section 4.2: 'the mapping between allocated virtual pages and NUMA nodes remains stable after resetting the device' — stated as observation, no data shown.
domain assumption L1 caches are flushed after kernel execution while L2 contents persist
Section 5.4: 'the L1 cache is flushed after the kernel finishes executing, but the data inside the L2 NUMA node remains'; needed so the second SM's read hits L2, not stale L1.
domain assumption clock() around a single memory access by thread 0 gives a usable latency sample
Listing 1 wraps one load with clock(); no calibration, overhead subtraction, or sampling distribution is reported.

invented entities (1)

H100 L2 sub-NUMA node
purpose: Explains the 280 vs 312 cycle bimodality in local L2 latency and the ~32 cycle sub-node penalty
Inferred solely from GMM components of local L2 latencies; no NVIDIA documentation, patent, or external measurement corroborates the sub-node structure.

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Cite this review

Pith. "Pith review of DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis." pith.science (2026). https://pith.science/paper/73OX46JU

@misc{pith2026260719922,
  author       = {Pith},
  title        = {Pith review of: DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/73OX46JU}},
  note         = {Machine review of arXiv:2607.19922}
}

read the original abstract

Graphics Processing Units (GPUs), due to their immense parallel processing capabilities, have become essential across various fields, including gaming and artificial intelligence. With significant advancements in GPU cores, GPU memory efficiency has lagged, resulting in bottlenecks that can limit workload efficiency. To bridge this gap, a deep understanding of GPU memory architectures, particularly Non-Uniform Memory Access (NUMA) mechanisms within L2 and DRAM, is essential for optimizing applications, designing new architectures, and building accurate simulators. However, the latest GPU hardware from vendors like NVIDIA and AMD is still a black-box, making it challenging for researchers to understand the details of their design. In this paper, we introduce DGNA, a methodology designed to unveil the NUMA architecture of the GPU memory hierarchy through microbenchmarking and data analysis. Specifically, we propose an approach to measuring the latency of L2 caches and DRAM without relying on the intrinsic instructions of the architecture and apply a Gaussian mixture model to filter out outliers and accurately determine latency distributions. We apply DGNA on NVIDIA's A100 and H100 GPUs, revealing NUMA node architecture, SM-NUMA relationships, and NUMA-aware memory allocation strategies used to maintain cache coherence. To the best of our knowledge, this is the first paper to detail the NUMA architecture within the GPU memory subsystem.

Figures

Figures reproduced from arXiv: 2607.19922 by the authors.

**Figure 1.** The L2 latencies measured by __ldcg [16, 21] and DGNA on the A100 show clear gaps, suggesting that __ldcg introduces additional operations for certain L2 memory accesses. For the H100, the similar results indicate that __ldcg may directly fetch data from the L2 cache. These findings suggest that vendor-provided intrinsics contain undisclosed implementation details that can impact final results. these vendor-specific… view at source ↗

**Figure 2.** DGNA leverages the fact that L2 caches are shared among all SMs, while each SM has its own private L1 cache, to measure L2 [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗

**Figure 3.** The workflow for analyzing the NUMA architecture topology. The first step is to generate feature vectors for any pair of SMs [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗

Figures from the paper (8 more)

**Figure 4.** Figure 4: The distribution of access latencies for all SMs on GPUs accessing all DRAM NUMA nodes follows a mixed Gaussian distribution [PITH_FULL_IMAGE:figures/full_fig_p012_4.png]

**Figure 5.** Figure 5: The latency distribution for all SMs accessing all L2 NUMA nodes, after removing outliers, follows a mixed Gaussian distribution [PITH_FULL_IMAGE:figures/full_fig_p012_5.png]

**Figure 6.** Figure 6: The distribution of access latencies for all SMs on GPUs accessing all DRAM NUMA nodes follows a Gaussian distribution for RTX 5090. These latencies are clusterred around a single central value: 922 cycles for the RTX 5090 after removing outliers. 180 200 220 240 260 L…

**Figure 7.** Figure 7: The latency distribution for all SMs accessing their local L2 NUMA nodes on the H100 follows a mixed Gaussian distribution, [PITH_FULL_IMAGE:figures/full_fig_p013_7.png]

**Figure 8.** Figure 8: We measure the latency feature vectors by accessing consecutive memory addresses through DRAM NUMA nodes. [PITH_FULL_IMAGE:figures/full_fig_p014_8.png]

**Figure 9.** Figure 9: Accessing consecutive memory addresses to derive the L2 NUMA node information. For measuring L2 latency within the same [PITH_FULL_IMAGE:figures/full_fig_p015_9.png]

**Figure 10.** Figure 10: The sub-NUMA information is obtained by accessing consecutive memory addresses using different SMs to warm up and [PITH_FULL_IMAGE:figures/full_fig_p015_10.png]

**Figure 11.** Figure 11: The mechanism of GPUs to read data on L2 NUMA includes 3 cases: [PITH_FULL_IMAGE:figures/full_fig_p016_11.png]

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