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REVIEW 3 major objections 7 minor 51 references

Ascend to Science: Exploration of AI Chips for Scientific Computing

T0 review · 3 major / 7 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read Scientific workloads can run on AI-native NPUs when numerical formulation, execution placement, and data movement are coordinated.

desk verdict A useful state-of-the-practice study of five scientific workloads on Ascend NPUs, but the LRSVD baseline is described inconsistently and one of the five evidence pillars is compromised; worth a serious referee if that is fixed. read the letter →

arxiv 2607.20120 v1 pith:BZ6UYWTU submitted 2026-07-22 cs.DC

Weicheng Xue , Kai Yang , Yongxiang Liu , Baisong Xu , Dengdong Fan , Xianglin Liu , Pengxiang Xu , Yonghong Tian This is my paper
classification cs.DC
keywords AIacceleratorsNeuralProcessingUnitscientificcomputingmixedprecisionheterogeneousexecutionemulationdatamovementHPL-MxP
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that AI-oriented NPUs—specifically the Ascend 910 series—can support scientific computing that demands numerical robustness, irregular access, and scalability, provided three gaps are worked around: precision, execution mismatch, and data movement. It validates this across five applications spanning dense linear algebra, low-rank factorization, quantum simulation, and Monte Carlo, showing competitive throughput and accuracy against GPU and CPU baselines. If true, this means the HPC community need not dismiss AI accelerators as unusable for science, but instead must adapt algorithms and orchestration to the hardware's tensor-centric model.

What carries the argument

The DaVinci architecture's asymmetric execution model is the central mechanism: Cube Units provide dense tensor throughput, Vector Units handle flexible but slower element-wise work, and a software-managed memory hierarchy (UB, L0/L1 buffers, L2, HBM) makes data movement explicit. The paper's key insight is that scientific workloads must be split into stages matched to these resources, with precision-sensitive or control-heavy stages placed on the CPU, and that memory traffic must be orchestrated through tiling, fusion, and prefetching. The five application mappings are the concrete machinery that turns this insight into validated outcomes.

What would settle it

Running a sparse, communication-heavy iterative solver (e.g., conjugate gradient on an unstructured mesh) on the same Ascend stack while applying the paper's stated principles; if it fails to achieve numerical robustness, competitive throughput, or scaling beyond a few dies, the central claim that the three gap-bridging techniques are sufficient for scientific computing would be falsified.

Watch

Extended reading notes

Core claim

The paper's central claim is that scientific codes can be made to run efficiently and robustly on AI-native NPUs through coordinated treatment of numerical formulation, execution placement, and data movement. On the Ascend 910 series, the authors demonstrate this by mapping five workloads to the DaVinci architecture's Cube and Vector units: HPL-MxP uses mixed-precision LU factorization with CPU-side refinement and communication overlap; LRSVD partitions precision-sensitive QR onto the CPU while offloading data-parallel sketching to the NPU; SGEMM-cube emulates FP32 GEMM by splitting operands into FP16 components and accumulating on Cube units; PQSim applies gate fusion and cache-blocking to

Load-bearing premise

The five studied applications are assumed to be representative of scientific computing, but the paper itself concedes that highly irregular, communication-dominated, or control-flow-heavy applications are underrepresented, so the claimed transferability of the principles is only established for these five workloads.

Editorial extensions

If this is right

  • Mixed-precision iterative refinement can be made to work on NPUs, enabling HPL-MxP-class benchmarks to scale to hundreds of dies with near-linear scaling and FP64-accurate solutions.
  • FP32-level accuracy is achievable on FP16-native tensor engines through mantissa-splitting emulation, offering a path to run legacy dense linear algebra without hardware FP64 support.
  • Bandwidth-bound workloads like quantum state-vector simulation can outpace higher-bandwidth GPUs when gate fusion and on-chip tile reuse reduce HBM traffic.
  • Irregular Monte Carlo simulations can be regularized into vectorized kernels that approach GPU throughput on NPUs, at least for local-energy-dominated workloads.
  • The paper's principles are transferable to other tensor-centric accelerators, though specific tuning for memory hierarchy and software stack remains necessary.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same 'three-gap' framing could serve as a portability checklist for moving any scientific code to a tensor-centric accelerator, potentially reducing trial-and-error in future deployment efforts.
  • Compiler and runtime support that automates stage partitioning, precision emulation, and memory orchestration could make these expert-driven mappings broadly accessible; the paper's manual approaches hint at what such automation would need to handle.
  • The success of SMC-X on NPUs suggests that even inherently sequential algorithms can be stripped of their irregularity when the underlying data dependencies are localized, which may extend to other rejection-sampling or agent-based simulations.
  • The energy-to-solution measurements, though limited, imply that NPUs could offer efficiency advantages for specific scientific workloads, which would become more significant as AI-centric HPC systems proliferate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. This paper investigates whether AI-oriented NPUs can support scientific workloads, using the Ascend 910 family as a case study. The authors characterize Cube- vs Vector-/memory-bound kernels with roofline analysis, then present five application studies—HPL-MxP, LRSVD, SGEMM-cube, PQSim, and SMC-X—that combine mixed-precision reformulation, heterogeneous CPU/NPU execution, precision emulation, memory-hierarchy orchestration, and communication–computation overlap. The central claim is that AI-native NPUs can achieve numerical robustness, competitive performance, and satisfactory scalability when numerical formulation, execution placement, and data movement are coordinated. The paper is explicitly positioned as a state-of-the-practice synthesis rather than a claim of new optimization primitives, and it acknowledges in its Limitations section that the five workloads do not cover highly irregular, communication-dominated, or control-flow-heavy applications.

Significance. If the results hold, the paper provides one of the most complete public case studies of scientific computing on Ascend NPUs, with credible kernel-level roofline analysis, a within-NPU gate-fusion comparison for PQSim, FP32-emulation error measurements for SGEMM-cube, and HPL-MxP scaling across 8–128 dies. The paper also explicitly separates transferable optimization principles (heterogeneous stage partitioning, precision emulation, hierarchical data orchestration, communication overlap) from Ascend-specific implementation details, which is valuable for the HPC community. However, the evidence is partly self-referential: three of the five application studies (HPL-MxP, SGEMM-cube, SMC-X) are based on the authors' prior work, and the LRSVD comparison contains a baseline inconsistency that weakens one of the five pillars. The central claim is defensible only after those comparison issues are repaired.

major comments (3)
  1. [§6.1.2 / §6.3 / Fig. 9] The LRSVD GPU baseline is described inconsistently. Section 6.1.2 states the baseline is 'a GPU-accelerated randomized SVD on NVIDIA H800/A800 using cuSOLVER,' while Section 6.3 says the same GPU baseline is 'cuSOLVER full-rank SVD.' These cannot both be true. If the baseline is full-rank SVD, the order-of-magnitude speedup in Fig. 9(a) at N=10,000 is mostly the algorithmic complexity difference between low-rank randomized SVD and full-rank SVD, not evidence of NPU efficiency. The energy-to-solution comparison in Fig. 17 has the same problem. Please specify the exact cuSOLVER routine, target rank, tolerance, and whether a matched randomized low-rank GPU baseline was used; if not, recompute the performance and energy comparisons against a matched baseline or clearly label them as algorithmic comparisons.
  2. [§6.1.3 / Eq. (4) / Fig. 11(b)] Two issues. First, the SGEMM-cube implementation is evaluated on a 910A, while the 'cann sgemm' baseline is measured on a 910B. The conclusion that 'sgemm-cube outperforms the vendor implementation' conflates algorithmic advantage with hardware-generation differences; please provide a same-generation comparison (e.g., CANN sgemm on 910A, or sgemm-cube on 910B) or explicitly frame the result as cross-generation. Second, Eq. (4) drops the A_L B_L term without an error bound. The empirical 1e-7 relative error is suggestive, but the 'negligible' claim is an ad hoc assumption; please add an error analysis or a sensitivity study over matrix sizes and value ranges.
  3. [Abstract / §6.1.1 / §6.2.2] The abstract's 'satisfactory scalability' claim is supported mainly by HPL-MxP, which shows scaling from 8 to 128 dies. The other four studies are single-chip or four-chip evaluations: LRSVD and SGEMM-cube are single-chip, PQSim is single-die, and SMC-X uses four NPUs with no scaling curve. If the claim is that the coordinated methodology yields scalability across the workload classes, please provide at least one additional multi-node scaling result (e.g., SMC-X or PQSim) or qualify the scalability claim to HPL-MxP only. The current wording overgeneralizes from a single scaling study.
minor comments (7)
  1. [§6.1.3 / Fig. 11] Figure 11(b) compares SGEMM-cube on 910A with CANN sgemm on 910B; the caption should state the platform difference explicitly and should also show the FP32 peak line for the corresponding platform.
  2. [§5 / Fig. 5] The sgemv point lies above the drawn roofline. The text explains this as effective bandwidth above the simple GM→L1 assumption, but a roofline plot should either use the effective memory hierarchy or annotate why the point is not a roofline violation; otherwise the 'reproducible' OI model in Table 4 is unclear.
  3. [§6.1.2 / Fig. 9] Figure 9 caption and labels contain unicode/font artifacts in the submitted PDF, making the legend and axis labels unreadable. Please regenerate the figure with a standard font embedding.
  4. [§6.1.2 / Eq. (3)] The QR convergence tolerance epsilon=0.005 appears arbitrary. Please justify this value or provide a sensitivity analysis; the manuscript already reports that nloop=2 works best, but the tolerance choice is not discussed.
  5. [§4.3 / §6.1.2] LRSVD validation is described qualitatively ('stable convergence,' 'numerically consistent,' 'under single-precision constraints'). Please report a quantitative accuracy metric for LRSVD, such as relative reconstruction error or subspace distance, so that the numerical-robustness claim is verifiable.
  6. [§3.4.1 / §3.4.2] Section 3.4.1 appears to duplicate the CANN paragraph already given in Section 3.4; please merge or remove the redundant subsection.
  7. [Appendix 7] The paper says artifacts are described in Appendix 7, but the appendix is an environment description, not an artifact or code repository. If code is available, provide a DOI or repository link; otherwise state that no artifact is released.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity; self-citations are not load-bearing. LRSVD baseline inconsistency is a validity issue, not circularity.

full rationale

This is a state-of-the-practice empirical evaluation rather than a derivation whose outputs are built from its own inputs. The five application studies report direct measurements against external references (OpenBLAS FP32, CANN sgemm, cuQuantum, cuSOLVER/MKL, published SMC-GPU), so the performance and accuracy claims are not constructed from the paper's own fitted values. The optimization primitives (Ozaki splitting, mixed-precision iterative refinement, gate fusion, dynamic link-cell Monte Carlo) are either standard or explicitly attributed to prior work, and the paper disclaims novelty of the primitives themselves. HPL-MxP, SGEMM-cube, and SMC-X draw on same-group prior results, but HPL-MxP (SC24) and SMC-X (npj Comput. Mater., JCTC) are peer-reviewed and externally falsifiable, while SGEMM-cube's key accuracy and throughput data are re-presented with external baselines, so these self-citations do not carry the argument independently. The LRSVD study has a serious non-circular flaw: Section 6.1.2 describes the GPU baseline as 'a GPU-accelerated randomized SVD on NVIDIA H800/A800 using cuSOLVER,' but Section 6.3 states that 'the GPU baseline uses cuSOLVER full-rank SVD' and admits the energy comparison reflects 'the algorithmic difference between the evaluated implementations.' If the Fig. 9 baseline is full-rank SVD, the order-of-magnitude speedup may reflect randomized low-rank versus full-rank complexity rather than NPU competitiveness. This is a benchmark-validity and reproducibility issue that weakens one of five evidence pillars, but it is not a circular reduction of the paper's claims to its inputs. Overall, the central claim retains independent empirical content, so circularity is minimal.

Assumptions & free parameters 5 free parameters · 6 assumptions · 0 invented entities

No new physical entities are postulated. The main auxiliary constructs—the atomic virtual layer in SMC-NPU, dual-lattice organization, and UB-resident data staging—are software/data-structure adaptations, not new physical entities. The paper's dependencies are hardware-spec assumptions, an unproven approximation in the SGEMM-cube decomposition, hand-tuned LRSVD thresholds, and a workload-selection assumption that the five applications are representative.

free parameters (5)
  • LRSVD QR convergence tolerance epsilon = 0.005
    Eq. (3) states epsilon = 0.005 is 'tailored for the Ascend single-precision environment.' This is a hand-chosen threshold used in all plotted LRSVD results.
  • LRSVD iterative orthogonalization loop count nloop = 2 (or 3)
    Section 6.1.2 says 'in practice, nloop = 2 or 3 provides the best balance between stability and overhead'; the plotted config uses nloop = 2. This is tuned by experiment.
  • PQSim cache-blocking tile size (tileSize)
    Section 6.2.1 introduces a tile size for UB-resident blocking but never specifies its value; it is a tunable parameter affecting HBM-UB traffic.
  • SMC-NPU local-energy vector assignment
    Section 6.2.2 says the number of local energies assigned per vector unit was 'carefully determined' to maximize buffer utilization; no value or method is given.
  • HPL-MxP GEMM fusion window size
    Section 6.1.1 describes a 'multi-iteration fusion strategy' that combines multiple GEMM updates into a single execution window, but the window size is not specified.
assumptions (6)
  • domain assumption The five applications are representative of the scientific workload classes relevant to AI-oriented NPUs.
    The conclusion that AI NPUs can support scientific workloads depends on the sample covering the important workload space. The paper's own Limitations section concedes that highly irregular, communication-dominated, or control-flow-heavy applications are underrepresented.
  • domain assumption The Ascend 910A/B/C hardware specifications and DaVinci architecture description in Table 1 and Fig. 1 are accurate.
    All performance claims are interpreted against these peak throughput, bandwidth, and memory-capacity numbers, which are taken from vendor or related sources without independent measurement.
  • domain assumption HPL-MxP GMRES-based iterative refinement recovers FP64-accurate solutions on the tested matrices.
    Section 6.1.1 states correctness follows the standard benchmark requirement but reports no residual or error quantities to verify convergence.
  • ad hoc to paper The omitted A_L B_L term in SGEMM-cube is negligible for the claimed FP32-accuracy across the tested matrix-size range.
    Eq. (4) drops the A_L B_L product, which introduces an approximation at roughly 2^-22 relative scale. The paper does not prove a bound covering subnormals, overflow, or all input distributions.
  • domain assumption The SMC-X restructuring preserves Monte Carlo semantics and detailed balance.
    Section 6.2.2 asserts that the dual-lattice/masked-vector reformulation 'preserves the Monte Carlo update semantics,' but no formal proof or acceptance-rate validation is given.
  • standard math The single-level global-memory roofline model is adequate for interpreting kernel performance.
    Table 4 and Fig. 5 use a roofline model with single-level memory bandwidth; the paper itself notes that sgemv exceeds the model due to on-chip reuse, so the model is an approximation.

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Cite this review

Pith. "Pith review of Ascend to Science: Exploration of AI Chips for Scientific Computing." pith.science (2026). https://pith.science/paper/BZ6UYWTU

@misc{pith2026260720120,
  author       = {Pith},
  title        = {Pith review of: Ascend to Science: Exploration of AI Chips for Scientific Computing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BZ6UYWTU}},
  note         = {Machine review of arXiv:2607.20120}
}
read the original abstract

The rapid rise of AI-oriented accelerators has reshaped compute systems around low-precision tensor engines, raising a practical question for the HPC community: under what conditions can such hardware support scientific workloads that demand numerical robustness, irregular memory access, and scalability? Using the Ascend 910 NPU series as a representative tensor-centric platform, we characterize precision, execution, and memory-hierarchy bottlenecks that hinder the direct deployment of scientific codes. We then develop and evaluate workload-specific mappings across five application studies -- HPL-MxP, LRSVD, SGEMM-cube, PQSim, and SMC-X -- combining heterogeneous execution, mixed-precision numerical formulations, precision emulation, hierarchical memory orchestration, and communication--computation overlap. These studies show that AI-native NPUs can achieve numerical robustness, competitive performance, and satisfactory scalability when numerical formulation, execution placement, and data movement are addressed in a coordinated manner. Our results provide a state-of-the-practice case study of how scientific workloads can be adapted to tensor-centric architectures, while distinguishing transferable optimization principles from Ascend-specific implementation details.

Figures

Figures reproduced from arXiv: 2607.20120 by the authors.

Figure 1
Figure 1. A schematic of the DaVinci architecture. Adapted from [26, 5]. [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. A layered view of the Ascend software stack. [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Hierarchical Interconnect and System Topology of the 910C Cluster. A standard 910C node contains four [PITH_FULL_IMAGE:figures/full_fig_p008_3.png] view at source ↗
Figures from the paper (13 more)
Figure 4
Figure 4. Figure 4: Achieved throughput of representative scientific kernels on Ascend 910B, 910C, and NVIDIA GPUs. [PITH_FULL_IMAGE:figures/full_fig_p010_4.png]
Figure 5
Figure 5. Figure 5: Roofline analysis of representative scientific kernels on Ascend 910B, 910C and GPU. The plot shows [PITH_FULL_IMAGE:figures/full_fig_p011_5.png]
Figure 6
Figure 6. Figure 6: Fused hierarchical pipeline for HPL-MxP LU factorization. The workflow shows orchestration of LU [PITH_FULL_IMAGE:figures/full_fig_p012_6.png]
Figure 7
Figure 7. Figure 7: Strong-scaling performance of HPL-MxP on three generations of Ascend NPUs (910A, 910B, and 910C). The [PITH_FULL_IMAGE:figures/full_fig_p013_7.png]
Figure 8
Figure 8. Figure 8: Heterogeneous execution workflow and hardware mapping for the LRSVD solver. The algorithmic pipeline is [PITH_FULL_IMAGE:figures/full_fig_p014_8.png]
Figure 9
Figure 9. Figure 9: Performance characterization of LRSVD. (a) Execution time scaling versus matrix dimension [PITH_FULL_IMAGE:figures/full_fig_p015_9.png]
Figure 11
Figure 11. Figure 11: (a): Relative error across increasing matrix sizes. [PITH_FULL_IMAGE:figures/full_fig_p017_11.png]
Figure 12
Figure 12. Figure 12: The systematic workflow of PQSim for high-performance quantum circuit simulation. The pipeline illustrates [PITH_FULL_IMAGE:figures/full_fig_p019_12.png]
Figure 13
Figure 13. Figure 13: Performance benchmarking of PQSim on NPUs and GPUs using Random Circuit Sampling (RCS). The [PITH_FULL_IMAGE:figures/full_fig_p020_13.png]
Figure 14
Figure 14. Figure 14: Schematics to illustrate the SMC-X algorithm. The dynamical LC is employed to isolate MC moves of [PITH_FULL_IMAGE:figures/full_fig_p021_14.png]
Figure 15
Figure 15. Figure 15: Architectural mapping and execution flow of the SMC-NPU algorithm. Green blocks highlight vector [PITH_FULL_IMAGE:figures/full_fig_p022_15.png]
Figure 16
Figure 16. Figure 16: Schematic of local-energy vectorization in SMC-NPU. Queues of contiguous SIMD operands are staged in [PITH_FULL_IMAGE:figures/full_fig_p023_16.png]
Figure 17
Figure 17. Figure 17: Normalized energy-to-solution comparison of representative applications. For each workload, the GPU [PITH_FULL_IMAGE:figures/full_fig_p025_17.png]

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Pith tools

Reviewed August 1, 2026 · model on record in the stance chip above.