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REVIEW 4 major objections 4 minor 101 references

DMG: A Scalable and Efficient Memory-Disaggregated Graph Processing System

T0 review · 4 major / 4 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read This paper claims that DMG is the first practical graph processing system for disaggregated memory, one that scales across multiple compute and memory nodes while keeping compute-side caches at conventional DM sizes and delivering performan

desk verdict Genuinely new multi-CN/MN graph processing on DM, with a thorough ablation, but the MN-CPU assumption is tested only on 24-core EPYC nodes and could be the weak point. read the letter →

arxiv 2607.20881 v1 pith:LKQIBDWU submitted 2026-07-23 cs.DB cs.DC

Yizou Chen , Tsun-Yu Yang , Zhisheng Hu , Baotong Lu , Ming-Chang Yang This is my paper · ORCID
classification cs.DBcs.DC
keywords graphprocessingdisaggregatedmemoryRDMACXLcacheefficiencypartitioningloadbalancingstore
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Traditional distributed graph platforms couple CPU and memory in fixed-ratio servers, wasting resources; existing attempts to run graph analytics on disaggregated memory are stuck on one compute node and one memory node and demand tens of gigabytes of compute-side cache. DMG claims to be the first practical disaggregated-memory graph system that scales out both compute and memory elastically, needs only about 1–2 GB of cache per compute node, and still runs billion-edge graphs within roughly 40% of a local-memory distributed system’s computation time. It achieves this with a DM-friendly graph store that inlines short edge lists into the index, an adaptive update coordinator that moves update work to whichever node holds the destination vertex’s attributes, and a two-stage workload manager that partitions fast at startup and re-schedules hub vertices at runtime. If these claims hold, disaggregated memory stops being a toy for graph analytics and becomes a way to allocate graph memory independently of compute.

What carries the argument

The central mechanism is an adaptive per-vertex index and edge-store combined with a redistribute update path. The 32-byte per-vertex index lives in a single range-partitioned array on the memory pool; for low-degree vertices it stores the edge list inline (‘in-place’), turning two dependent remote reads into one, while for high-degree vertices it stores the edge-list address and compressed per-segment lengths (‘out-of-place’). The segment lengths let a node fetch only the portion of a hub’s edge list that falls in a given partition, and they let the update coordinator hand whole segments to the node that owns the destination attributes. This machinery converts RDMA’s IOPS bottleneck into fe

What would settle it

Run the same BFS and PageRank workloads with memory nodes limited to one or two low-power cores and measure both end-to-end time and memory-node CPU utilization during the densest iteration; if any memory node’s utilization saturates or the end-to-end time degrades disproportionately, the collaborative-update claim collapses.

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Extended reading notes

Core claim

The paper’s core discovery is that the three obstacles to practical graph processing on DM—IOPS-limited remote reads, costly remote update propagation, and tail effects from hub vertices—can each be turned around by exploiting where data already resides. DMG stores vertex attributes once in a shared memory pool and gives each compute node a small cache covering its assigned chunk. For retrieval, a 32-byte per-vertex index entry either embeds the edge list of low-degree vertices or stores a compressed segment layout for high-degree vertices, so most vertex reads become one merged RDMA request instead of two dependent fine-grained ones. For updates, a collaborative scheme batches update candid

Load-bearing premise

The load-bearing premise is that a memory node’s scarce CPU can absorb the offloaded update work (ValRD) and RPC service without becoming a bottleneck—the testbed gives each memory node a 24-core server running only two threads, so the reported numbers depend on memory-node CPU being cheap.

Editorial extensions

If this is right

  • Disaggregated-memory graph systems can store one copy of the graph in a shared memory pool and elastically add compute nodes without re-coupling memory, so tenants pay only for the resource they need.
  • A conventional 1–2 GB compute-side cache is enough for billion-scale graphs, because each compute node caches only the attribute slice of its assigned chunk; aggregate compute-node memory stays a small fraction of memory-pool usage.
  • Graph partitioning for load balancing can be redone in sub-seconds using tiny-chunk metadata, making repeated resource reconfiguration practical on DM.
  • The computation-time gap versus a local-memory distributed system stands at about 40%, and the paper argues this gap will narrow as interconnect bandwidth rises toward 800 Gbps and beyond.
  • The same storage and update techniques carry over to CXL-based memory pooling, because they reduce fine-grained remote accesses rather than relying on RDMA-specific behavior.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper does not test memory nodes with truly scarce CPU: its memory nodes are 24-core servers running only two threads. If a real memory node has one or two weak cores, the offloaded ValRD update path could saturate that CPU, and the reported cache savings and speedups would shrink.
  • The in-place index scheme exploits power-law degree distributions; on graphs with more uniform degrees, fewer vertices fit inline and the retrieval benefit should diminish. The paper includes a synthetic R-MAT graph but does not isolate this effect.
  • The collaborative-update advantage depends on chunk locality; a graph whose vertex IDs are shuffled to destroy locality would send far more update candidates across the network. DMG does not report a degradation curve for such adversarial layouts.
  • Because the loaded graph store and segment metadata are reusable across different compute-node counts, a natural extension is mid-query elastic resizing of the compute pool without reloading the graph; the paper does not implement this.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. DMG proposes a graph processing system for memory-disaggregated (DM) architectures. It contributes three main designs: (i) a DM-friendly graph store that embeds low-degree edge lists in an enlarged index and applies merged/batched RDMA retrieval; (ii) an adaptive update coordinator that selects between collaborative update (with pass-by-reference and pass-by-value re-distribution) and direct remote update depending on update density; and (iii) a two-stage workload manager using coarse-grained tiny-chunk partitioning plus runtime hub re-scheduling. The paper claims this is the first practical multi-CN/multi-MN graph processing system on DM, achieving up to 4.9× speedup over FAM-Graph, up to 18.9× reduction in compute-side cache demand, and computation time within 40% of the local-memory distributed system Gemini. The evaluation includes internal ablations over the proposed components and comparisons with FAM-Graph, DMG-Base, and Gemini on four billion-scale graphs.

Significance. If the claims hold, this is a substantial contribution to the DM systems literature. The paper identifies an important practical gap in existing DM graph systems (single CN/MN and large compute-side caches) and proposes concrete mechanisms to address it. A particular strength is the internal ablation in §5.4: separating the effects of index embedding, retrieval optimizations, the two re-distribution modes, and runtime re-scheduling gives good evidence that the design choices, not just the overall architecture, drive the reported gains. The cache-efficiency result (orders of magnitude below FAM-Graph) and the startup-time comparison with Gemini are also compelling. However, the central scalability and performance claims rest on assumptions about memory-node CPU availability and on a fixed 4-MN testbed; these are not yet fully stress-tested, and the absence of repeated-run statistics makes some quantitative claims difficult to assess.

major comments (4)
  1. [§5.1/§5.4.2] MN CPU model: The system model in §2.2 assumes MNs have weak computation power (e.g., 1–2 CPU cores), but the testbed uses 24-core EPYC 7402P MNs (only two threads active). The ValRD mechanism (§4.3.1) is load-bearing: Fig. 25 shows +ValRD provides a large improvement over +RefRD. However, the MN CPU validation in Fig. 26 reports at most 44% usage of one EPYC core for TW; this does not establish that the same offload is sustainable on a real 1–2 core, lower-performance MN that also runs RPC-serving threads. I recommend adding an experiment that pins MN threads to one or two cores, or otherwise models weak MNs, and reports end-to-end performance and ValRD CPU/throughput under that constraint. If ValRD saturates, the fallback path could erode the reported speedups.
  2. [§5.2/§5.1] Memory-side scalability is not directly demonstrated. The abstract claims elastic scaling of both compute and memory, but all scaling experiments vary only the number of CNs (1, 2, 4) with a fixed 4-MN pool. I could not find an experiment that varies the number of MNs, or that increases graph size while scaling MNs. The clueweb12 result shows DMG can use a 4-MN pool where FAM-Graph cannot, but not that adding MNs elastically accommodates ever-increasing graphs. Please add a memory-scaling experiment (e.g., 1→4 MNs with fixed CN count, or a graph that grows with MN count) or temper the claim.
  3. [§5 (general methodology)] All reported numbers appear to be from single executions, with no error bars or variance information. This matters for the quantitative headline claims (4.9× speedup, 18.9× cache reduction) and for small differences such as the UK 0.91–1.19× speedup range in §5.2. I request repeated runs (at least 3–5 per configuration) with confidence intervals, or at minimum a statement of run-to-run variability, for the key figures (Figs. 15–19, 24, 25, 28).
  4. [§4.2.1/§5.4.1] Several design thresholds—32B index entry size, in-place degree ≤7, RS hub threshold >1024, 4 coroutines per thread, 1024 tiny-chunks—appear to be chosen based on the four benchmark graphs, and the index-size sweep (Fig. 22) is shown only for TW. Since the main comparisons use the same datasets, it is unclear whether these values are overfit to the testbed. Please add a sensitivity analysis for the most impactful thresholds across datasets and at least one other hardware configuration, or give an explicit argument that the thresholds are hardware- and dataset-independent.
minor comments (4)
  1. [Figs. 15–18] The captions do not define what the annotated ratios (e.g., '99x', '179x') refer to. Clarify whether they are speedups of DMG over DMG-Base or over FAM-Graph, and how FAM-Graph is plotted at 2 and 4 CNs when it supports only one CN.
  2. [Fig. 19] Please define 'per-CN cache usage' precisely (maximum RSS, allocated cache size, or measured working set) and state whether the FAM-Graph bar is for one CN only. This would help readers interpret the 18.9× claim.
  3. [§5.3] The statement that DMG achieves computation time 'within 40% of Gemini' is ambiguous: does it mean 40% slower, or 40% of Gemini's time? The text later says 'moderate computation overhead,' suggesting the former. Please rephrase.
  4. [Abstract and §5.3] There are small text issues: 'toDM-friendly' in the abstract and 'ontwitter-2010' in §5.3 are missing spaces. Also, the paper promises open-source code; please include the repository or artifact link at the final version.

Circularity Check

0 steps flagged · score 0.0 of 10

No load-bearing circularity: claims are measured against external baselines; self-citations and the MN-CPU setup are caveats, not circular inputs.

full rationale

DMG is an evaluation-driven systems paper; its central claims are established by direct measurements against external baselines (FAM-Graph, Gemini) and an internal ablation (DMG-Base) across four billion-scale graphs, not by a derivation in which an output is defined in terms of an input. The design constants (32B index, in-place degree threshold, RS threshold, 2GB cache) are presented as empirical tuning choices with parameter studies (Figs. 22-23) and ablations (Figs. 24-28), and the headline 4.9x/18.9x numbers are measured comparisons, not fitted outputs. Self-citations ([21] Aceso, [36] DEX, [74-76] Seraph/Oasis) support background claims or appear in related work; the one load-bearing assumption they touch—that MNs can execute offloaded ValRD work cheaply—is independently measured in Fig. 26, so the citations do not carry the argument. The stated limitations (§4.5.2 dual-mode selection restricted by hardware; §4.5.3 static graphs only) narrow scope but do not create circularity. The main caveat is external validity, not circularity: MNs are simulated on 24-core EPYC machines (§5.1) while §2.2 assumes 1-2 weak cores, so the ValRD CPU-usage numbers may overstate real-MN headroom; this affects how representative the results are, not whether the results were derived from their own assumptions.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The paper's central claims rely mainly on engineering assumptions about RDMA behavior, graph structure, and DM hardware conventions rather than unproved mathematical axioms. No new physical or formal entities are introduced. The principal 'costs' are empirical design constants fit to the benchmark graphs.

free parameters (5)
  • Index entry size = 32 bytes
    Chosen to balance performance and memory efficiency (Figure 22) on benchmark graphs; a fitted design constant.
  • In-place / ValRD degree threshold = degree ≤ 7
    Threshold below which edges are embedded in the index or passed by value; tuned to power-law graphs in the evaluation.
  • RS hub threshold = degree > 1024
    Degree above which a vertex's edge list is split into segments for runtime re-scheduling; chosen empirically (§4.4.2).
  • Coroutines per thread = 4
    Default concurrency level for hiding RDMA latency; set by the system and not swept in the evaluation.
  • Tiny-chunk count = 1024
    Granularity for coarse-grained initial partitioning; a fixed system constant chosen for fast partition times.
assumptions (5)
  • domain assumption RDMA NIC throughput is IOPS-bound for requests < 4 KB
    Used to justify increasing request size via in-place index and merged/batched reads; supported by Figure 6 but treated as a hardware property.
  • domain assumption Real-world graphs exhibit power-law degree distributions
    Underlies in-place scheme, RefRD/ValRD split, and hub-vertex RS; the four benchmark graphs may not cover all graph types.
  • domain assumption Chunk-based contiguous partitioning preserves locality in real graphs
    Adopted from Gemini [92]; DMG's cache-efficiency argument depends on neighbors being clustered within chunks.
  • domain assumption DM compute nodes have 1-2 GB local cache and MNs have scarce CPU
    Standard DM convention from prior work; the testbed uses 24-core machines as MNs, so the scarcity is not fully reproduced.
  • domain assumption DM pool is globally addressable via 16-bit MN ID + 48-bit offset
    Addressing scheme from prior DM systems [40,62]; assumed to hold in the target deployment.

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Cite this review

Pith. "Pith review of DMG: A Scalable and Efficient Memory-Disaggregated Graph Processing System." pith.science (2026). https://pith.science/paper/LKQIBDWU

@misc{pith2026260720881,
  author       = {Pith},
  title        = {Pith review of: DMG: A Scalable and Efficient Memory-Disaggregated Graph Processing System},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LKQIBDWU}},
  note         = {Machine review of arXiv:2607.20881}
}
read the original abstract

Traditional graph processing systems are built on monolithic servers, which couple a fixed ratio of compute and memory resources but often result in resource under-utilization in data centers. Although the disaggregated memory (DM) architecture has emerged to address this inefficiency, we identify that existing graph processing systems on DM remain highly impractical. They rely on unscalable architectures that fail to scale beyond a single memory node and a single compute node, and they require compute-side caches that are orders of magnitude larger than conventional practice in DM. To this end, this paper presents DMG, the first practical graph processing system on DM, which demonstrates superior system scalability and cache efficiency while delivering high performance. To improve efficiency of graph retrieval on DM, DMG proposes a DM-friendly graph store with retrieval optimizations. To mitigate costly update propagation, DMG presents an adaptive update coordinator that coordinates compute and memory nodes to perform update propagation with low overhead. To enable fast and effective load balancing, DMG employs a two-stage workload manager that includes a coarse-grained initial partitioning and a fine-grained runtime re-scheduling. Experimental results substantiate that compared with the state-of-the-art DM-based graph processing system, DMG can elastically scale up both compute and memory resources, delivering up to 4.9X better performance and accommodating graphs with ever-increasing sizes; meanwhile, it effectively tames the compute-side cache demands by up to 18.9X, positioning itself as a DM-ready solution in practice.

Figures

Figures reproduced from arXiv: 2607.20881 by the authors.

Figure 1
Figure 1. Data structures and workflow in graph processing. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. The Disaggregated Memory Architecture. The disaggregated memory (DM) architecture has recently been proposed for cloud infrastructure [45, 51] to address the resource inefficiency in traditional data centers built on monolithic servers, which couple different resource components together [19, 37, 57]. As shown in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. An example of vertex replication in distributed [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: Different system architectures and data layouts for [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: CDF of access granu￾larity for graph retrieval dur￾ing BFS on twitter-2010 8 32 128 512 2k 8k 32k Access Granularity (Bytes) 1 10 IOPS (Million/sec) IOPS bound IOPS Bandwidth 1 10 100 Bandwidth (Gbps) Bandwidth bound [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 9
Figure 9. Figure 9: The Overview of DMG. 4.2 DM-friendly Graph Store The storage format fundamentally determines the efficiency of storing and accessing graph data on DM [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]
Figure 11
Figure 11. Figure 11: Merged and batched retrieval of graph data. [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]
Figure 12
Figure 12. Figure 12: Different strategies in DMG to perform update [PITH_FULL_IMAGE:figures/full_fig_p007_12.png]
Figure 14
Figure 14. Figure 14: Structure of Batched Re-Distribution (RD) Buffer [PITH_FULL_IMAGE:figures/full_fig_p008_14.png]
Figure 15
Figure 15. Figure 15: Computation time on twitter-2010. 1 2 4 Number of CN (a) BFS 2 1 2 2 2 3 2 4 2 5 Comp. Time (s) FAM-Graph 1 2 4 Number of CN (b) CC 2 3 2 4 2 5 2 6 DMG-Base 1 2 4 Number of CN (c) PR 2 2 2 3 2 4 2 5 2 6 DMG [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]
Figure 16
Figure 16. Figure 16: Computation time on uk-2007-05. 1 2 4 Number of CN (a) BFS 2 3 2 4 2 5 2 6 2 7 Comp. Time (s) 9.1x 12x FAM-Graph 1 2 4 Number of CN (b) CC 2 4 2 5 2 6 2 7 10x 16x DMG-Base 1 2 4 Number of CN (c) PR 2 6 2 7 2 8 2 9 2 10 16x 23x DMG [PITH_FULL_IMAGE:figures/full_fig_p0…
Figure 19
Figure 19. Figure 19: Cache demands in each CN. social network graph, rmat-29 (R29) as a synthetic graph gener￾ated by R-MAT [5] with default parameters, uk-2007-05 (UK) and clueweb12 (CW) [3] as web crawler graphs. We evaluate three rep￾resentative graph processing workloads: breadth-firs…
Figure 20
Figure 20. Figure 20: Startup time (s) of DMG and Gemini for clueweb12 with 4 servers/CNs. 10 1 10 2 10 3 Mem Usage (GB) 7 7 7 128 256 512 10 2 10 3 Mem Usage (GB) Gemini OOM Gemini OOM 195 195 196 512 1 2 4 CN/Server Num (a) twitter-2010 0 1 2 Comp Time (s) 1 2 4 CN/Server Num (b) clueweb…
Figure 24
Figure 24. Figure 24: Design effect of retrieval optimizations. [PITH_FULL_IMAGE:figures/full_fig_p012_24.png]
Figure 25
Figure 25. Figure 25: Design effect of two types of RD. BFS CC PR (a) twitter-2010 0 20 40 60 1 Core CPU Usage Rate (%) 21.8 44.4 30.2 44.1 36.2 36.2 BFS CC PR (b) clueweb12 0 10 20 30 3.86 8.67 7.24 13.9 0.86 0.86 Total Exec Densest Iter [PITH_FULL_IMAGE:figures/full_fig_p012_25.png]

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