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REVIEW 4 major objections 7 minor 28 references

CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation

T0 review · 4 major / 7 minor · reviewed 2026-07-30 · grok-4.5

Pith's one-line read Separating schematic topology from textual behavior into an explicit circuit contract before writing RTL improves executable pass rates over text-only generation.

desk verdict Clean contract-mediated multimodal RTL method with a released 5K executable corpus and an honest 2×2; gains are real but still conditioning on text-derived schematics, not proven visual grounding. read the letter →

arxiv 2607.23523 v1 pith:YDHONHNO submitted 2026-07-26 cs.AR

classification cs.AR
keywords RTLgenerationVerilogmultimodallearningcircuitcontractstopology-behavioralignmentexecutableverificationelectronicdesignautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Natural-language specs for hardware often leave wiring, register boundaries, and state-to-output links implicit, even when ports and cycle behavior are clear. Schematics can show that structure, but dumping an image into a multimodal model does not force the system to keep text evidence and picture evidence apart or to mark what is missing or in conflict before code is written. CircuitWeave extracts a topology contract from the schematic and a behavior contract from the text, fuses them into one circuit contract that records correspondences, gaps, and conflicts, and generates RTL only from that fused record. Trained on 5,000 packages that each include a self-checking testbench and pass simulation, an adapted small multimodal model gains several points of executable pass rate when the schematic is added—most clearly at pass@1 on VerilogEval-Human—relative to the same adapted model without the image.

What carries the argument

The circuit contract: a fused serialization of topology (from the schematic) and behavior (from the text) that records field correspondences, missing evidence, and conflicts, and is the sole input to the RTL-generation step (Eq. 1).

What would settle it

Rerun the same adapted checkpoint with blank, mismatched, or topology-perturbed schematics (or independently authored diagrams): if the image-minus-text pass-rate gains disappear or reverse while text-only stays fixed, the central claim that schematic topology evidence is doing the work fails.

Watch

Extended reading notes

Core claim

Under a matched comparison of checkpoint state and input, contract-mediated multimodal RTL generation—source-restricted topology and behavior contracts fused into a single circuit contract, with RTL decoded only from that contract—raises executable pass rates for an adapted 4B model above the same adapted checkpoint run text-only, by 8.46 / 5.85 / 2.57 points on VerilogEval-Human pass@1/5/10 and by 2 points on RTLLM at each cutoff.

Load-bearing premise

The schematics, which are generated from the same task text rather than drawn independently, still carry structural information useful enough that the measured gains reflect real topology evidence and not just redundant restatement or formatting.

Editorial extensions

If this is right

  • RTL generators can treat fusion as an explicit intermediate artifact rather than free-form multimodal decoding.
  • Missing and conflicting constraints can be serialized before code emission instead of left implicit in a rationale.
  • Description-derived schematics plus contract adaptation can lift small models on simulation-based Verilog benchmarks without larger-scale text-only training alone.
  • Training packages that co-locate contracts, reference RTL, and executable testbenches become a reusable substrate for multimodal hardware generation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If contracts become the API between perception and codegen, human designers could edit or override fused fields before RTL is emitted.
  • The same topology–behavior split may transfer to other diagram-plus-spec domains (timing charts, FSM drawings, block diagrams) where prose under-specifies connectivity.
  • Without independent diagram authorship or grounding controls, future work will need to separate true visual grounding from training that merely teaches the model to exploit generated restatements.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. The paper presents CircuitWeave, a contract-mediated pipeline for multimodal RTL generation: a topology contract is extracted from a schematic and a behavior contract from text, the two are fused into a serialized circuit contract recording correspondences, missing fields, and conflicts, and RTL is decoded from the fused contract only (Eq. 1, Listing 1). A five-term objective (Eq. 3) supervises both contracts, fusion, contract-conditioned RTL, and reverse reconstruction of covered contract fields; Qwen3.5-4B is adapted with LoRA on a newly constructed 5,000-package executable-qualified corpus (Icarus-gated reference RTL/testbench pairs). Evaluation is a matched 2×2 over checkpoint state (base/adapted) and input (text/text+image) on VerilogEval-Human and RTLLM with a shared extraction and EDA harness. Headline results: 46.60/61.49/65.39% pass@1/5/10 on VerilogEval-Human for the adapted text+image condition, +8.46 points at pass@1 over the same checkpoint without the image, versus −3.01 for the base checkpoint; RTLLM deltas are +2 points at all cutoffs. The authors are careful to state that schematics are generated from the same task descriptions, that no grounding controls (blank/mismatched/anonymized images) were run, and that all numbers are descriptive point estimates without intervals, seed replicates, or component ablations.

Significance. If the results hold, the paper contributes (i) a well-controlled matched 2×2 study isolating adaptation-by-image interaction in multimodal RTL generation — a design most prior work in this space lacks; (ii) executable acceptance throughout (Eq. 4), with a shared extraction/EDA harness across all controlled rows; (iii) a publicly released 5K-package corpus co-locating schematic, modality-specific and fused contracts, reference RTL, and an Icarus-qualified testbench, which has standalone value; and (iv) a compact 4B model that, under its own protocol, exceeds reported StarCoder2-15B values. The manuscript is also commendably explicit about what it does not show (no visual-grounding verification, no loss-term isolation, descriptive point estimates only), which raises confidence in what it does claim. The significance ceiling is set by the descriptive nature of the evidence: the schematics are restatements of the same text, so the measured image deltas bound, but do not establish, the value of independently authored diagrams — the setting where the approach would matter most in practice.

major comments (4)
  1. [§5.2, Tables 4–5 (RQ2/RQ3)] All reported effects are point estimates from a single training run and a single sampling pass (n=20, temperature 0.7), with no task-level bootstrap intervals or seed replicates. This is load-bearing for the headline claims: the VerilogEval-Human pass@1 interaction of +11.47 points (Table 5) could plausibly survive resampling, but the RTLLM deltas of +2.00 points at every cutoff correspond to roughly one task or fewer on that benchmark's task set (the paper does not state the RTLLM task count; on the standard ~29-task set, 2 points is below single-task resolution). Similarly, the pass@10 interaction of −0.63 versus +11.47 at pass@1 is the basis for the RQ3 'no consistent direction' conclusion, yet without intervals one cannot tell whether any of these interactions differ from zero. Section 6 acknowledges this, but acknowledgment does not substitute for the estimate. Task-level paired (i)
  2. [§4.2, §5.1 (RQ1 attribution)] RQ1 attributes a 14–26 point improvement to 'the combined adaptation recipe,' but the paper's first contribution is specifically the contract-mediated framework, and no experiment isolates it. The missing condition is a direct RTL SFT baseline: the same 4,750 packages, the same LoRA configuration, trained on (description → RTL) pairs without contracts, L_align, or L_cons. Without it, the adaptation gain is equally consistent with (a) generic SFT on 4.75K executable-qualified RTL pairs, (b) the multi-task contract supervision, or (c) the reverse-reconstruction auxiliary. A related unquantified gap: training conditions L_RTL on the reference fused contract while inference conditions on the predicted contract (§3.4), and no stage-wise failure counts or contract-quality measurements are reported (§6), so it is unknown how much of the residual error is contract-phase versus RTL-phase. The ab
  3. [§4.1, §2.2 (grounding controls)] The paper explicitly cites VeriGround [20] showing that blank-image and anonymized-identifier controls can reveal apparent image benefits without visual grounding, states that its own schematics are generated from the same task description by Nano Banana 2 (§4.1), and discloses that its image deltas 'measure conditioning rather than verified visual grounding' (§2.2). Given this explicit awareness, the absence of the two cheapest controls — a blank/placeholder image and a mismatched schematic (generated from a different task's description) run through the identical adapted-checkpoint pipeline — is a conspicuous evidential gap for RQ2. These require only inference, no retraining. As it stands, the +8.46 point adapted image delta is equally consistent with genuine topology evidence, with a redundant-restatement/'second-opinion' effect, or with formatting variance in the contract pipeline. A
  4. [§3.2 (benchmark overlap)] The corpus's text and RTL are web-collected, and the authors state that 'the available records do not support a benchmark-aware semantic-overlap count' (§3.2). This leaves the absolute VerilogEval-Human levels (and hence the RQ1 base-to-adapted deltas of up to +26 points) exposed to contamination: VerilogEval-Human tasks derive from HDLBits-style problems that are heavily represented in public RTL repositories and tutorials. The within-checkpoint RQ2 image deltas are protected because both conditions share the checkpoint, so the central interaction claim survives; but the abstract leads with absolute pass@k numbers that are contextualized against external systems in Table 4, and those levels depend on decontamination that was not performed. A modest effort — exact/ near-
minor comments (7)
  1. [§4.2 (hyperparameters)] The loss weights λ (L_align) and μ (L_cons) from Eq. (3) are never given in §4.2, which otherwise reports LoRA rank, learning rate, epochs, warmup, batching, sequence length, and image-token budget. Please report λ and μ (and any sensitivity) for reproducibility.
  2. [§4.1 (benchmarks)] The RTLLM variant and task count are not specified (the original release has ~29 tasks; later versions differ). Given that the RTLLM deltas are 2 points, the denominator matters for interpreting them; please state the version and N.
  3. [§5.3 (case study)] Figure 2 is a single paired example; it is suggestive but should be explicitly labeled illustrative, and ideally complemented by a count of how often the image-conditioned and text-only candidates differ semantically across the benchmark (even a coarse diff-rate would strengthen §5.3).
  4. [§3.1, Eq. (2)] Eq. (2) marginalizes contract sequences that are never enumerated at inference; a sentence clarifying that the four-call pipeline is a single deterministic sample from the factorization (not an approximation of the sum) would prevent misreading.
  5. [Listing 1 / §3.3] Listing 1's serialization format is described only schematically; including one full (anonymized-length) example of a fused contract z, or pointing to one in the released dataset, would make the supported/missing/conflict labeling concrete.
  6. [Table 2; §3.2] Table 2's comparison is useful, but the 'TB use' column mixes curation-time and learning-time testbench roles; a footnote defining the column (partially given) directly in the header would help. Also, 'Nano Banana 2' and 'GPT-5.5' are product names whose version pinning relies on blog citations [5, 13]; please pin model snapshot identifiers where available, since schematic and testbench quality depend on them.
  7. [Abstract] Abstract: '8.46, 5.85, and 2.57 points above those of the same adapted checkpoint without the schematic' — consider adding the base-checkpoint delta (−3.01) or a 'descriptive point estimates' qualifier in the abstract itself, consistent with the care taken in §5.2.

Circularity Check

0 steps flagged · score 1.0 of 10

Empirical ML paper on external executable benchmarks; no load-bearing derivation reduces to its inputs by construction.

full rationale

CircuitWeave’s central claims are empirical pass@k improvements under a matched 2×2 of checkpoint state and text vs text+image input on VerilogEval-Human and RTLLM (Tables 4–5), with acceptance defined by hidden testbench compilation and simulation (Eq. 4). Those outcomes are not algebraically forced by the training targets: the model must emit RTL that elaborates and passes checks it never saw. Equation 1 is an intentional source-restricted factorization (topology from image only, behavior from text only, RTL from fused z only), not a claimed first-principles prediction. L_align supervises agent-written fusion records and is explicitly disclaimed as an independent alignment metric; L_cons is an auxiliary reverse reconstruction on reference RTL, not reported as a benchmark result. Schematics are description-derived (Nano Banana 2 from task text), so image deltas measure conditioning rather than independent visual grounding—the paper states this in §§1, 4.1, 6—but that is a validity limit on interpreting the multimodal gap, not a circular reduction of pass@k to fitted inputs. No uniqueness theorem, self-citation chain, or renamed known law carries the result. Minor self-citation to overlapping-author ReasoningV appears only in related work and is not load-bearing. Score 1 only for the mild training-side fact that topology contracts rest on text-generated schematics; the evaluation chain itself is non-circular.

Assumptions & free parameters 5 free parameters · 6 assumptions · 5 invented entities

The central empirical claim rests on standard LLM fine-tuning practice, executable simulation as correctness, and several paper-specific modeling choices: that agent-generated schematics and contracts are adequate supervision, that fused-contract-only decoding is the right inductive bias, and that Icarus-qualified web-collected packages are clean enough for benchmark gains to be meaningful. Hyperparameters are chosen rather than derived. No physical constants; free parameters are training/decoding knobs and unspecified loss weights.

free parameters (5)
  • LoRA rank and scaling (r=32, α=64) = r=32, scaling 64
    Adapter capacity chosen by authors; affects how much the joint objective can move the base multimodal model.
  • Learning rate, epochs, warmup, batching = lr=1e-4, 3 epochs
    Optimization schedule fixed by hand (1e-4, 3 epochs, warmup 0.05, batch 2, accum 2); not cross-validated in the paper.
  • Loss weights λ (L_align) and μ (L_cons) = unreported
    Eq. 3 introduces λ and μ but the manuscript does not report fitted or default values; central multi-task balance depends on them.
  • Sampling temperature and n=20 candidates = T=0.7, n=20
    pass@k estimates depend on T=0.7 and 20 samples per task/condition.
  • Image-token budget 1024 / seq length 8192 = 1024 image tokens, 8192 seq
    Truncation and visual resolution knobs that can change what topology is visible to the model.
assumptions (6)
  • domain assumption Icarus elaboration+simulation pass of reference RTL against an agent-synthesized self-checking testbench is a sufficient package qualification signal for training data.
    Section 3.2 and Table 1; paper admits this does not establish coverage or cross-modal fidelity.
  • ad hoc to paper Source-restricted decoder calls (topology←image only, behavior←text only, RTL←fused z only) implement the intended evidence separation even though modalities are statistically dependent.
    Eq. 1 and Section 3.1 explicitly redefine restriction as call-level, not independence.
  • ad hoc to paper Description-derived schematics are valid multimodal inputs for measuring image-conditioning benefits on text benchmarks.
    Sections 1, 4.1, 6; core premise of RQ2–RQ3.
  • domain assumption Unbiased pass@k under compile+simulate against hidden testbenches is the right primary success metric for RTL generation quality.
    Standard in VerilogEval/RTLLM; Section 4.1; ignores synthesis/timing/PPA.
  • domain assumption Teacher-forced supervision on agent-produced contract serializations teaches transferable contract extraction rather than only imitating agent style.
    Section 3.4 joint objective; contracts not independently audited (Section 6).
  • standard math Standard next-token cross-entropy with LoRA on frozen vision encoder/aligner is an adequate adaptation regime for the multimodal base model.
    Section 3.4–4.2; conventional PEFT setup.
invented entities (5)
  • Topology contract z_v
    purpose: Serialize schematic-only structural evidence (components, connectivity, operators, registers, state, unknowns).
    Paper-defined intermediate representation; schema in Table 3 and Listing 1.
  • Behavior contract z_t
    purpose: Serialize text-only interface, timing, function, and corner-case constraints.
    Complementary paper-defined IR paired with z_v.
  • Fused circuit contract z (with supported/missing/conflict status)
    purpose: Sole conditioning input to RTL generation; make cross-modal correspondence and disagreements explicit.
    Central invented mediation object of CircuitWeave; not a prior standard IR like a compiler CIR.
  • Covered-contract projection z_cov for reverse reconstruction
    purpose: Auxiliary y→z_cov task regularizing shared parameters on ports, events, and selected datapath fields.
    Deterministic projection P_cov(z) defined in Section 3.4; training-only construct.
  • Executable-qualified multimodal design–verification package (5K corpus) independent evidence
    purpose: Joint training resource binding text, schematic, contracts, RTL, and testbench under Icarus gate.
    New dataset artifact; public HF release claimed.

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Cite this review

Pith. "Pith review of CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation." pith.science (2026). https://pith.science/paper/YDHONHNO

@misc{pith2026260723523,
  author       = {Pith},
  title        = {Pith review of: CircuitWeave: Topology-Behavior Alignment for Executable Multimodal RTL Generation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YDHONHNO}},
  note         = {Machine review of arXiv:2607.23523}
}
read the original abstract

Text-only LLMs generate RTL from natural-language specifications, but prose can leave connectivity, register boundaries, and state-output relations implicit even when interfaces and cycle-level behavior are specified. Schematics can make these structural relations explicit and thereby complement the behavioral constraints conveyed by text. Yet simply adding an image creates a fusion challenge: direct multimodal decoding does not explicitly separate the evidence roles of text and schematics or make missing and conflicting constraints explicit before code generation.We present CircuitWeave, a contract-mediated multimodal framework that extracts a topology contract from the schematic and a behavior contract from the text. It fuses these records into a circuit contract that serializes correspondences, missing evidence, and conflicts, then generates RTL only from this contract. A joint objective supervises both contracts, serialized fusion, contract-conditioned RTL generation, and reverse reconstruction of covered contract fields from reference RTL.We construct 5,000 executable-qualified packages, each containing a specification, generated schematic, structured contracts, reference RTL, and self-checking testbench, and use the training split to adapt Qwen with LoRA. On VerilogEval-Human, CircuitWeave reaches 46.60% pass@1, 61.49% pass@5, and 65.39% pass@10. These point estimates are 8.46, 5.85, and 2.57 percentage points above those of the same adapted checkpoint without the schematic. On RTLLM, it reaches 40.00%, 48.00%, and 52.00%, two percentage points above the adapted text-only condition at each cutoff.The dataset is publicly available at https://huggingface.co/datasets/fengjiahao0421/CircuitWeave.

Figures

Figures reproduced from arXiv: 2607.23523 by the authors.

Figure 1
Figure 1. Conceptual overview of CircuitWeave. Text and the generated schematic provide behavior and topology evidence, which reconciliation combines into fused contract 𝑧. The RTL-generation call receives only 𝑧, and only extracted RTL reaches the hidden EDA boundary. The source-restricted calls follow Eq. 1; the training-only reverse-reconstruction task is omitted. which come from the schematic. A model may follow visual co… view at source ↗
Figure 2
Figure 2. Paired outputs from the same adapted Qwen3.5-4B [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗

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Works this paper leans on

28 extracted references · 2 canonical work pages

  1. [20]

    Guang Yang, Xing Hu, Xiang Chen, and Xin Xia. 2026. From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation. arXiv:2604.27969. doi:10.48550/arXiv.2604.27969

  2. [1]

    Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, and Ying Wang. 2024. Natural Language is Not Enough: Benchmarking Multi-modal Gen- erative AI for Verilog Generation. InProceedings of the IEEE/ACM International Conference on Computer-Aided Design. Association for Comp...

  3. [2]

    Mark Chen, Jerry Tworek, Heewoo Jun, Qiming Yuan, Henrique Ponde de Oliveira Pinto, Jared Kaplan, Harri Edwards, Yuri Burda, Nicholas Joseph, Greg Brockman, Alex Ray, Raul Puri, Gretchen Krueger, Michael Petrov, Heidy Khlaaf, Girish Sastry, Pamela Mishkin, Brooke Chan, Scott Gray, Nick Ryder, Mikhail Pavlov, Alethea Power, Lukasz Kaiser, Mohammad Bavarian...

  4. [3]

    Fan Cui, Chenyang Yin, Kexing Zhou, Youwei Xiao, Guangyu Sun, Qiang Xu, Qipeng Guo, Yun Liang, Xingcheng Zhang, Demin Song, and Dahua Lin. 2024. OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. InProceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design. Association for Computing Machinery,...

  5. [4]

    Google. 2026. Gemini 3 Flash Preview. https://ai.google.dev/gemini-api/docs/m odels/gemini-3-flash-preview. Endpoint: gemini-3-flash-preview; accessed: 2026-07-18

  6. [5]

    Google DeepMind. 2026. Nano Banana 2: Combining Pro Capabilities with Lightning-Fast Speed. https://blog.google/innovation-and-ai/technology/ ai/nano-banana-2/. Endpoint: gemini-3.1-flash-image-preview; accessed: 2026-07-18

  7. [6]

    Hu, Yelong Shen, Phillip Wallis, Zeyuan Allen-Zhu, Yuanzhi Li, Shean Wang, Lu Wang, and Weizhu Chen

    Edward J. Hu, Yelong Shen, Phillip Wallis, Zeyuan Allen-Zhu, Yuanzhi Li, Shean Wang, Lu Wang, and Weizhu Chen. 2022. LoRA: Low-Rank Adaptation of Large Language Models. InInternational Conference on Learning Representations. OpenReview.net, Virtual Event, 26 pages. https://openreview.net/forum?id=nZ eVKeeFYf9

  8. [7]

    Icarus Verilog Project. 2026. Icarus Verilog Documentation. https://steveicarus. github.io/iverilog/. Accessed: 2026-07-10

Show all 28 references
  1. [8]

    Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, and Haoxing Ren. 2023. In- vited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation. InProceedings of the 2023 IEEE/ACM International Conference on Computer-Aided Design. IEEE, San Francisco, CA, U...

  2. [9]

    Mingjie Liu, Yun-Da Tsai, Wenfei Zhou, and Haoxing Ren. 2025. CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct- by-Construction Non-Textual Representations and Targeted Code Repair. In International Conference on Learning Representations, Y...

  3. [10]

    Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, and Zhiyao Xie. 2025. RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems44, 4 (2025), 1448–1461....

  4. [11]

    Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie. 2024. RTLLM: An Open- Source Benchmark for Design RTL Generation with Large Language Model. In Proceedings of the 29th Asia and South Pacific Design Automation Conference. IEEE, Incheon, Republic of Korea, 722–727. doi:10.1109/AS...

  5. [12]

    ModelScope Team. 2026. MS-Swift: Command-Line Parameters. Software doc- umentation. Accessed: 2026-07-11. https://github.com/modelscope/ms- swift/blob/main/docs/source_en/Instruction/Command-line-parameters.md

  6. [13]

    OpenAI. 2026. Introducing GPT-5.5. https://openai.com/index/introducing-gpt- 5-5/. Accessed: 2026-07-10

  7. [14]

    Hammond Pearce, Benjamin Tan, and Ramesh Karri. 2020. DAVE: Deriving Au- tomatically Verilog from English. InProceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD. Association for Computing Machinery, New York, NY, USA, 27–32. doi:10.1145/3380446.3430634

  8. [15]

    Haiyan Qin, Zhiwei Xie, Jingjing Li, Liangchen Li, Xiaotong Feng, Junzhan Liu, and Wang Kang. 2025. ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model. arXiv:2504.14560. doi:10.48550/arXiv.2504. 14560

  9. [16]

    Qwen Team. 2026. Qwen3.5-4B Model Card. Hugging Face model repository. Accessed: 2026-07-11. https://huggingface.co/Qwen/Qwen3.5-4B

  10. [17]

    Fu Teng, Miao Pan, Xuhong Zhang, Zhezhi He, Yiyao Yang, Xinyi Chai, Mengnan Qi, Liqiang Lu, and Jianwei Yin. 2025. VeriRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning. In2025 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE...

  11. [18]

    Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, and Siddharth Garg. 2024. VeriGen: A Large Lan- guage Model for Verilog Code Generation.ACM Transactions on Design Automa- tion of Electronic Systems29, 3 (2024), 46:1–46:31. doi:1...

  12. [19]

    Yiting Wang, Guoheng Sun, Wanghao Ye, Gang Qu, and Ang Li. 2025. VeriRea- son: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. arXiv:2505.11849

  13. [21]

    Shuo Yin, Yihe Wang, Lancheng Zou, Xufeng Yao, Tinghuan Chen, Chen Bai, Zhengrong Wang, Tsung-Yi Ho, and Bei Yu. 2026. CPPL: A Circuit Prompt Programming Language. arXiv:2605.17892

  14. [22]

    Patrick Yubeaton, Andre Nakkab, Weihua Xiao, Luca Collini, Ramesh Karri, Chinmay Hegde, and Siddharth Garg. 2025. VeriThoughts: Enabling Automated Verilog Code Generation Using Reasoning and Formal Verification. InAdvances in Neural Information Processing Systems 38: Datasets ...

  15. [23]

    Yang Zhang, Rui Zhang, Jiaming Guo, Lei Huang, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, and Yunji Chen

  16. [24]

    Zixi Zhang, Balint Szekely, Pedro Gimenes, Greg Chadwick, Hugo McNally, Jianyi Cheng, Robert Mullins, and Yiren Zhao. 2025. LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation. In2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Co...

  17. [25]

    Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Muxin Song, Yinan Xu, Ziyuan Nan, Mingju Gao, Tianyun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, and Xing Hu. 2026. CodeV: Empowering LLMs with HDL Generation through Multilevel Summariza...

  18. [26]

    Yaoyu Zhu, Di Huang, Hanqi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, and Yunji Chen. 2025. QiMeng-CodeV-R1: Reasoning-Enhanced Ve...

  19. [2021]

    arXiv:2107.03374

    Evaluating Large Language Models Trained on Code. arXiv:2107.03374. doi:10.48550/arXiv.2107.03374

  20. [2025]

    In Advances in Neural Information Processing Systems, Vol

    QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation. In Advances in Neural Information Processing Systems, Vol. 38. Curran Associates, Inc., Red Hook, NY, USA, 159613–159633. https://papers.neurips.cc/paper_files/p aper/2025/hash/ea052d3e98adfefa0fbff1766ee2efde-Abs...

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