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REVIEW 4 major objections 5 minor 30 references

Monitoring in the Dark: Privacy-Preserving Runtime Verification of Cyber-Physical Systems

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Garbled circuits can make runtime verification of cyber-physical systems privacy-preserving, so a monitor checks a system's timed trace against a secret specification and both parties learn only the robustness score.

desk verdict First garbled-circuit STL robustness monitor, but the variable-clock-cycle leak undercuts the privacy claim until a fixed-cycle implementation is used. read the letter →

arxiv 2505.16059 v1 pith:32YE2QGS submitted 2025-05-21 cs.LO

Charles Koll , Preston Tan Hang , Mike Rosulek , Houssam Abbas This is my paper · ORCID
classification cs.LO
keywords runtimeverificationprivacy-preservingmonitoringgarbledcircuitsmulti-partycomputationsignaltemporallogicrobustnesssemanticscyber-physicalsystemsdynamicprogramming
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that runtime verification of cyber-physical systems can be made privacy-preserving without giving up the quantitative information that engineers use: the robustness score. The proposed protocol lets a system owner (for example a drone operator) and a monitor (for example a traffic authority) jointly evaluate a Signal Temporal Logic formula on a timed trace, so that each party learns only the final robustness value at time zero. The monitor never sees the trace, and the system never sees the formula. The construction uses garbled circuits over a synthesized logic circuit that implements the DP-TALIRO dynamic program, and the experiments map where that construction is practical: feasible in software for short traces and shallow formulas, and promising in hardware for larger workloads. The authors answer their two research questions affirmatively: private robustness monitoring is implementable with garbled circuits, and it is practical under identifiable conditions.

What carries the argument

The load-bearing object is a synthesizable hardware implementation of DP-TALIRO, a dynamic program that computes STL robustness by filling an $N_x \times M$ table: one column per sub-formula, one row per trace sample, starting at the end of the trace and ending at $\rho(x,\varphi,0)$. The circuit is written as a controller-plus-datapath design in Verilog, with a finite-state machine handling the formula's syntax and a BOUNDS module computing the index ranges for temporal intervals; after synthesis the netlist is evaluated inside a sequential garbled-circuit protocol, which is what turns a public computation into a private two-party one. Because the formula itself is an input to the circuit, the same netlist serves any formula up to a fixed depth, so the circuit size does not leak the formula; only the agreed maximum depth and trace length are common knowledge. Sequential gates (flip-flops) keep the circuit small, and the protocol's communication complexity is $O(C \cdot cc \cdot \kappa)$ bits for circuit size $C$, clock cycles $cc$, and security parameter $\kappa$, while memory is $O(C\cdot\kappa)$.

What would settle it

Compare the circuit's output against a trusted reference implementation of DP-TALIRO on a large random corpus of traces and formulas; any input pair for which the sign or numeric value of $\rho(x,\varphi,0)$ differs would refute the claim that the circuit is a faithful robustness monitor.

Watch

Extended reading notes

Core claim

The central discovery is that the robustness-monitoring computation itself—not just satisfiability—can be run inside a garbled circuit, so the quantitative verdict is private by construction. The protocol has two parties: the Designer, who holds a finite timed trace of samples, and the Verifier, who holds an STL formula. They agree on a circuit that accepts both as inputs and outputs the robustness value $\rho(x,\varphi,0)$; following the garbled-circuit protocol, each party learns this value and nothing else beyond input lengths, with formulas padded to a fixed maximum depth to hide their true length. The circuit implements the DP-TALIRO dynamic program, which fills a table of robustness values indexed by trace positions and sub-formulas, and a BOUNDS subroutine that finds the timestamps inside a temporal interval. The paper reports that a gate-level netlist synthesized from Verilog, evaluated through a sequential garbled-circuit engine, computes robustness for traces up to length 500 and formulas of depth 4, with memory use linear in trace length and runtime growing roughly exponentially in trace length in software, while the number of hardware clock cycles suggests that a hardware implementation would be much faster. The authors take this as evidence that private monitoring is feasible today for testing and offline monitoring, and would be practical online once garbled circuits run in hardware.

Load-bearing premise

The whole practical claim rests on the synthesized circuit computing exactly the same robustness values as DP-TALIRO on fixed 32-bit scaled integers; the paper gives no formal equivalence proof between the Verilog and the algorithm, so a silent bug in the circuit would produce a wrong verdict while still satisfying the privacy guarantee.

Editorial extensions

If this is right

  • In software, the private monitor is fast enough for short inputs: a trace of length 10 with a depth-3 formula takes about one second, which is acceptable in a testing loop when simulation of the system under test dominates the cost.
  • Peak memory grows linearly with trace length, so a device with 1 GB of RAM can in principle handle a trace of 500 samples and a depth-4 formula, making embedded deployment plausible on the memory axis.
  • Because the synthesized circuit is independent of the particular formula and trace, it can be synthesized once, offline, on a powerful machine and then reused for arbitrary monitoring sessions, amortizing the high synthesis cost.
  • If garbled circuits are implemented directly in hardware, the measured clock-cycle counts indicate online monitoring could become practical; the paper estimates 40,000 cycles at 2.1 GHz as 19 ms, which is in the range of real-time control loops.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper leaves implicit that padding formulas and traces to fixed maxima converts the protocol's known input-length leakage into merely an upper bound, so a deployment could pad beyond the actual values and reveal even less than the nominal lengths.
  • The semi-honest threat model is what the measurements target; hardening the protocol against a malicious system owner or monitor would require additional proofs or zero-knowledge machinery, and the added overhead is not included in the reported runtimes.
  • A hardware garbled-circuit engine is the natural next experiment: running the same netlist on such an engine would directly test the authors' conjecture that online monitoring becomes practical, and would let engineers measure whether the 19 ms estimate holds at full circuit scale.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes a privacy-preserving runtime monitoring protocol in which a Designer holds a timed trace and a Verifier holds an STL formula, and both parties learn only the robustness of the trace with respect to the formula. The protocol is based on garbled circuits: DP-TALIRO is implemented as a parameterized Verilog sequential circuit that accepts both the trace and the formula as inputs, the netlist is synthesized with Synopsys Design Compiler, and the resulting circuit is garbled and evaluated with TinyGarble. The paper reports circuit sizes, clock-cycle counts, software runtime, peak memory, and synthesis time for traces up to length 500 and formulas of depth 3 and 4, and concludes that the approach is feasible for design testing and offline monitoring and for short traces in online monitoring. The authors state that security is inherited from standard garbled-circuit security, and that correctness of the underlying algorithm is inherited from DP-TALIRO.

Significance. If the result holds, this is the first garbled-circuit implementation of STL robustness monitoring over timed state sequences, and it is a useful feasibility baseline for private runtime verification. The paper has real strengths: security is inherited from the standard Bellare-Hoang-Rogaway garbled-circuits model rather than from an ad hoc primitive; the circuit is parameterized by maximum trace length and formula depth, so the formula is an input rather than compiled per formula; and the experimental evaluation makes concrete, falsifiable claims about runtime, clock cycles, memory, and synthesis time. However, the strongest privacy claim is not met by the reported implementation because the number of clock cycles varies with the formula, and the correctness of the synthesized circuit relative to DP-TALIRO is asserted rather than demonstrated. Both issues are fixable, but they are load-bearing for the central contribution.

major comments (4)
  1. [§4.2, §5.1, §6 (Fig. 6)] The implementation as reported does not realize the claimed guarantee that the system 'learns nothing about the formula.' The controller in §4.2 is an FSM whose control path depends on the formula's operator types and temporal intervals (e.g., the U_ZERO_UNB branch for [0,∞) and the looping branch for general [a,b) intervals), and Fig. 6 explicitly shows different clock-cycle counts for different formulas of the same depth and trace length. In a TinyGarble-style sequential garbled circuit, each clock cycle is a separate garbled-evaluation step, so the number of cycles is observable to both parties through execution time and communication volume. The ideal-world model in §2.3 allows leakage only of maximum input lengths and the output, not of the actual number of evaluation rounds. The paper itself acknowledges in §6 that 'an industrial implementation would run for a fixed number of cycles regardless of the formula,' confirming that the reported implementation is not constant-cycle. To meet the stated privacy claim, the protocol must fix a maximum cycle count and pad all evaluations to that count; the security statement and all reported measurements must then refer to the padded circuit.
  2. [§4.1–4.2, §6] The paper provides no correctness evidence that the Verilog RTL computes DP-TALIRO and hence the STL robustness function. Correctness of DP-TALIRO is cited to [29], and the RTL is described informally as a controller/datapath implementation of Algorithm 1, but there is no equivalence proof between Algorithm 1 and the RTL, no systematic test suite covering all operator types and interval boundary cases, and no theorem about the 32-bit fixed-point integer scaling introduced in §6 (signal values, timestamps, formula thresholds, and interval endpoints are all scaled by 10^5). If the synthesized circuit computes a different function than the true robustness, the privacy guarantee is vacuous because both parties learn the output of the wrong computation. A revision should add a formal or at least rigorous differential verification of the RTL and synthesized netlist against a reference DP-TALIRO implementation, including overflow behavior of the scaled arithmetic.
  3. [§5.2, §6 (Fig. 5), §7] The paper's claim that runtime 'scales exponentially with the size of the inputs' and that 'execution time in software scales exponentially with the trace length' is not supported by its own complexity model. Section 5.2 bounds the total work and communication by O(C·cc·κ), Fig. 9 reports circuit size C as linear in trace length, and DP-TALIRO is a dynamic program over N_x·M table entries, so even a conservative bound on the clock-cycle count cc is polynomial in N_x and formula depth for the bounded loops used in this implementation. The steep increase visible in Fig. 5 may reflect implementation overheads or fitting artifacts, but the paper gives no fitted functional form or confidence bounds. Please replace the exponential claim with a precise statement about the measured clock-cycle scaling, or with fitted curves and their error measures, and adjust the practicability discussion in §6 and §7 accordingly.
  4. [§6] The empirical evaluation is the basis for the feasibility claims, but the manuscript provides no code, Verilog sources, synthesized netlists, or raw data. Without these artifacts, the reported runtimes, memory usage, and synthesis times cannot be reproduced, and the claimed equivalence of the synthesized circuit to DP-TALIRO cannot be checked beyond the illustrative example in Table 3. I request that the artifacts be made available with the revision; if this is impossible, the empirical claims should be explicitly marked as preliminary and the paper should state what would be needed to reproduce them.
minor comments (5)
  1. [§2.1, Eq. (5)] In the Until robustness definition, the left-hand side uses the evaluation time variable t while the right-hand side uses the index i inside t^{-1}(t(i)+I); please make the notation consistent.
  2. [§4.1] Algorithm 1 returns R[1,1], while the text says 'the final value located at entry[0,0]'; Table 3 also uses row index 0. Please standardize the indexing convention.
  3. [§6] The fitted curves in Figs. 5–7 are described only as 'best fit'; please report the fitted functional forms and error measures, since the exponential-vs-polynomial interpretation in the text hinges on those curves.
  4. [§1] The sentence 'We show that privacy-preserving monitoring or CPS is indeed feasible' appears to contain a typo; it should likely read 'of CPS.'
  5. [§5.1] The claim that padding a shorter formula with 1-bits 'does not impact the robustness calculation' depends on the circuit's formula decoder treating padded subtrees as neutral for every operator encoding; please state this design invariant explicitly.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the privacy claim rests on external garbled-circuit security and an externally validated robustness algorithm, with empirical measurements rather than predictions.

full rationale

The paper's central derivation chain is not circular. The privacy guarantee is inherited from standard garbled-circuit security, cited to the external Bellare-Hoang-Rogaway foundations in [3], and the ideal-world model in Section 2.3 is an independent framing rather than a self-supplied theorem. The monitored function itself is DP-TALIRO, adopted from the external work [29], whose correctness is cited to that external source; the Verilog circuit is described as an implementation of that algorithm, and any gap between the RTL and Algorithm 1 is a correctness risk, not a circular reduction. The runtime, memory, and clock-cycle figures in Section 6 are measured experimental characterizations, not predictions derived from the target claim. The only self-citations ([1] and [16]) are motivational or related-work references and do not carry the proof burden. The acknowledged variable-clock-cycle leak in Section 6 is a privacy gap relative to the stated ideal functionality, but it is not a case of fitting an input and renaming it as a prediction, nor of defining one quantity in terms of another. Accordingly, no circular step is present and the score is 0.

Assumptions & free parameters 1 free parameters · 5 assumptions · 0 invented entities

The protocol's correctness rests on standard GC security, DP-TALIRO's correctness, the discrete sampling semantics, and faithful synthesis; no fitted constants or invented physical or mathematical entities are introduced.

free parameters (1)
  • integer scaling factor = 10^5
    Chosen by hand in Section 6 to convert real-valued signal values, thresholds, timestamps, and interval endpoints into 32-bit integers. The computed robustness is exact only if all quantities share this scale and no overflow occurs; the paper does not analyze overflow bounds.
assumptions (5)
  • domain assumption Security of Yao garbled circuits under the semi-honest model
    Section 5.1 relies on [3] and [5] for the claim that each party learns nothing beyond input length, circuit, and output.
  • domain assumption Correctness of DP-TALIRO
    Section 4.1 states correctness is shown in [29]; the paper's circuit is a Verilog port of this algorithm, not a new correctness proof.
  • domain assumption STL robustness semantics over timed state sequences with half-open intervals
    Section 2.1 defines traces as finite samples with timestamps and restricts formulas to the given syntax; this discrete sampling semantics is assumed throughout.
  • domain assumption Faithful synthesis and garbling of the Verilog design
    Section 4.2 and Section 6 assume Synopsys Design Compiler correctly synthesizes the RTL and that TinyGarble correctly garbles the resulting sequential gate-level netlist.
  • ad hoc to paper No overflow in 32-bit arithmetic
    Section 6 uses 32-bit signed integers with large random differences; the paper does not prove that all intermediate robustness values stay within range for the chosen scale and input bounds.

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Cite this review

Pith. "Pith review of Monitoring in the Dark: Privacy-Preserving Runtime Verification of Cyber-Physical Systems." pith.science (2026). https://pith.science/paper/32YE2QGS

@misc{pith2026250516059,
  author       = {Pith},
  title        = {Pith review of: Monitoring in the Dark: Privacy-Preserving Runtime Verification of Cyber-Physical Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/32YE2QGS}},
  note         = {Machine review of arXiv:2505.16059}
}
read the original abstract

In distributed Cyber-Physical Systems and Internet-of-Things applications, the nodes of the system send measurements to a monitor that checks whether these measurements satisfy given formal specifications. For instance in Urban Air Mobility, a local traffic authority will be monitoring drone traffic to evaluate its flow and detect emerging problematic patterns. Certain applications require both the specification and the measurements to be private -- i.e. known only to their owners. Examples include traffic monitoring, testing of integrated circuit designs, and medical monitoring by wearable or implanted devices. In this paper we propose a protocol that enables privacy-preserving robustness monitoring. By following our protocol, both system (e.g. drone) and monitor (e.g. traffic authority) only learn the robustness of the measured trace w.r.t. the specification. But the system learns nothing about the formula, and the monitor learns nothing about the signal monitored. We do this using garbled circuits, for specifications in Signal Temporal Logic interpreted over timed state sequences. We analyze the runtime and memory overhead of privacy preservation, the size of the circuits, and their practicality for three different usage scenarios: design testing, offline monitoring, and online monitoring of Cyber-Physical Systems.

Figures

Figures reproduced from arXiv: 2505.16059 by the authors.

Figure 1
Figure 1. CPS monitoring-and-testing loop. This paper introduces a way to do the monitoring in a privacy [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Privacy-preserving monitoring using secure multi-party computation (MPC). Designer inputs the [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Finite state machine of the controller. Temporal blocks are labeled with conditions on their intervals [PITH_FULL_IMAGE:figures/full_fig_p010_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Movement of data between the Datapath, Controller, and Bounds modules. The Datapath handles [PITH_FULL_IMAGE:figures/full_fig_p011_4.png]
Figure 5
Figure 5. Figure 5: Monitoring runtime vs trace length. For each length, we tried multiple formulas of depths 3 and 4. [PITH_FULL_IMAGE:figures/full_fig_p014_5.png]
Figure 6
Figure 6. Figure 6: Hardware cycles vs trace length. For each length, we tried multiple formula of depths 3 and 4. The [PITH_FULL_IMAGE:figures/full_fig_p014_6.png]
Figure 7
Figure 7. Figure 7: Monitoring peak memory consumption vs trace length. For each length, we tried multiple formula of [PITH_FULL_IMAGE:figures/full_fig_p015_7.png]
Figure 8
Figure 8. Figure 8: Synthesis time in hours for each trace length, across formulas of depths 3 and 4. [PITH_FULL_IMAGE:figures/full_fig_p015_8.png]
Figure 9
Figure 9. Figure 9: Size of the synthesized circuit, measured by number of gates (in 1000s). Compared across formulas of [PITH_FULL_IMAGE:figures/full_fig_p016_9.png]

Discussion (0). Continue with ORCID to comment.

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