Pith. sign in

REVIEW 4 major objections 5 minor 128 references

Themis: Software-Defined Hardware Prefetching

T0 review · 4 major / 5 minor · reviewed 2026-08-04 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read Themis claims that a single software-set bit in each page-table entry, telling the hardware prefetcher whether a data page is worth prefetching, removes about 40% of useless prefetch requests and improves performance for every prefetcher te

desk verdict Novel page-granular software-controlled prefetch throttling that deserves a serious look; the evaluation is broad, but λ tuning on test workloads and an internal SPEC mismatch need fixing. read the letter →

arxiv 2608.00259 v1 pith:34JPC5RN submitted 2026-07-31 cs.AR cs.OS

Keisuke Kamahori , Neil Adit , Kan Zhu , Yuqi Mai , Victor Lee , Heiner Litz , Chris Kennelly , Snehasish Kumar
show 8 more authors
Hanna Alam Milad Hashemi David Li Adrian Sampson Baris Kasikci Tipp Moseley Parthasarathy Ranganathan Akanksha Jain
This is my paper
classification cs.ARcs.OS
keywords hardwareprefetchingprefetchthrottlingpage-tablehintsprofile-guidedoptimizationhardware-softwareco-designdatacenterworkloadsmemorybandwidthTLB
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that, for datacenter workloads, the useless prefetches emitted by hardware prefetchers can be filtered at page granularity without sacrificing coverage, and that software is the better place to do the filtering. It proposes Themis, which uses a profile-guided per-page prefetch-enable bit stored in page-table entries and replicated in TLB entries. A lightweight kernel module samples cache evictions to learn which pages receive useless prefetches, then sets or clears the bit; the hardware prefetcher reads the bit and stops training and predicting for disabled pages. In simulated datacenter traces, this removes about 40.6% of useless prefetch requests on average across seven state-of-the-art prefetchers, raises useful-prefetch coverage by 5.7%, and improves IPC for all seven (geometric mean +3.5%, with BOP +4.1%, SPP+PPF +3.1%, and Pythia +1.4%). A sympathetic reader would care because it offers a low-cost, post-silicon knob that makes existing hardware prefetchers more accurate in bandwidth-constrained environments without new instructions or binary changes.

What carries the argument

The load-bearing mechanism is a per-page prefetch-enable bit delivered through the page-table/TLB path and read directly by the hardware prefetcher as an enable signal. The software sets the bit according to the criterion λ × #useful < #useless, using eviction records sampled by a small FIFO in the cache PMU; because hints propagate lazily with normal TLB fills, updating the page table costs no shootdowns. The hardware change is minimal: a small buffer to log useless-prefetch evictions for profiling, and the prefetcher gating its training and prediction logic on the hint bit.

What would settle it

Profile the same set of pages in two disjoint execution windows (or on two different cores) and compare the per-page prefetch-usefulness decisions. If a substantial fraction of pages flip from useful to useless between windows—or if re-profiling every 1 billion instructions instead of every 40 billion changes the set of disabled pages and materially improves IPC—then the stability assumption behind Themis's one-shot profiling is wrong, and the headline gains would not carry to production.

Watch

Extended reading notes

Core claim

The central discovery is that, in datacenter workloads, prefetch usefulness is strongly concentrated at the page level: 50–75% of pages have prefetch accuracy below 20%, so a per-page on/off switch can remove most useless prefetches while keeping the useful ones. The paper shows that this switch can be implemented with a single hint bit carried from the OS page table through the TLB to the prefetcher, avoiding the hundreds of kilobytes of on-chip storage a hardware-only per-page tracker would need. The software computes the hint from the ratio of useful to useless prefetch evictions using the criterion λ × #useful < #useless, updates page-table entries lazily with no TLB shootdown, and the p

Load-bearing premise

The load-bearing premise is that a page's prefetch usefulness is stable enough that a profile taken once from a single 100-million-instruction region on one core stays valid for other threads, later execution windows, and all ten evaluation samples; if page usefulness drifts over time or varies across cores, the one-shot hints become stale and the reported speedups lose their basis.

Editorial extensions

If this is right

  • Any existing hardware prefetcher can be wrapped with Themis; the paper reports IPC gains for all seven evaluated prefetchers on datacenter traces (BOP +4.1%, SPP+PPF +3.1%, Pythia +1.4%) with average useless-prefetch reduction of 40.6%.
  • Because hints travel through existing page-table/TLB attributes, deployment needs no binary rewriting, no ISA changes, and no TLB shootdowns; profiling overhead is about 0.2% of execution time when re-profiling roughly every 15 seconds.
  • The benefit grows as DRAM bandwidth shrinks, and the optimal throttling strength (λ) shifts downward, so the same mechanism can tune prefetchers for bandwidth-constrained many-core systems.
  • Disabling training on marked pages is essential: without it, the average gain drops from 3.5% to 1.9%, and the effect is comparable to or better than enlarging the prefetcher's on-chip metadata tables.
  • Themis outperforms CLIP, a state-of-the-art throttler, on datacenter traces: CLIP slows the system by 4.9% on average while Themis speeds it up by 3.5%, showing that page-granular software control suits large-footprint workloads better than PC-granular hardware throttling.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If page-granular usefulness remains stable across cores and longer production windows, the same PTE hint channel could carry richer directives—multi-bit aggressiveness levels, page-local prefetching, or per-page prefetch-distance hints—rather than a single on/off bit.
  • Because the mechanism works by improving utilization of small hardware metadata tables, it could plausibly be combined with temporal or machine-learning prefetchers whose accuracy depends heavily on table capacity; the paper evaluates spatial and ML prefetchers, so this is an untested extrapolation.
  • A testable extension is adaptive re-profiling: instead of a fixed λ and a ~40-billion-instruction cadence, tie re-profiling frequency to page churn or phase changes, since the overhead argument assumes page prefetchability is static after allocation.
  • One bit per page implies coarse control for huge pages; on 2 MB pages, mixed-content regions may need either finer-grained sub-page hints or acceptance of coarser throttling.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes Themis, a hardware-software co-design mechanism that controls hardware data prefetchers at page granularity. A software profiler computes per-page prefetch-usefulness statistics, stores a prefetch-enable hint in page-table/TLB attributes, and hardware prefetchers use this hint to suppress training/prediction on pages where prefetching is unlikely to be useful. The mechanism is evaluated in ChampSim on Google datacenter traces, SPEC2017, and GAP, across seven hardware prefetchers. The main reported results are a ~40.6% reduction in useless prefetches, a mean 3.5% IPC improvement on Google traces (with all seven prefetchers benefiting), and a small average coverage increase of 5.7%, attributed to reduced cache pollution and better use of prefetcher training resources.

Significance. If correct, the paper makes a timely and useful contribution: it offers a low-cost, orthogonal mechanism for improving prefetcher effectiveness in bandwidth-constrained datacenter workloads, with minimal hardware changes and no binary/ISA modifications. The use of page-table attributes as a communication channel is plausible, and the evaluation is unusually broad: seven prefetchers, public Google traces, SPEC2017, and GAP, plus sensitivity studies on lambda, DRAM bandwidth, training behavior, and prefetcher metadata sizes. A particular strength is that the main evaluation uses a single 100M-instruction profile region that is at least 100M instructions away from the ten evaluation regions, so the headline results are not a same-region self-test. The paper also explicitly compares against CLIP and hardware-only throttling baselines. These strengths make the central idea worth pursuing. The main weaknesses are in the completeness of the profiling/implementation story and in the selection of lambda on the test workloads.

major comments (4)
  1. [§3.3, Eq. (1)] The profiling flow as described cannot compute the criterion in Eq. (1). Step 1 buffers only useless prefetches: "Cache evictions for useless prefetches are buffered" and a useless prefetch is identified by the prefetch tag bit still being set at eviction. Eq. (1), however, requires per-page counts of both useful and useless prefetches (lambda x #useful < #useless). The paper does not explain how per-page useful-prefetch counts are obtained from the proposed PMU FIFO, nor how the kernel derives the ratio shown in the §3.2 figure. If the ChampSim evaluation instead uses ground-truth per-page useful/useless counts from a perfect profile, then the end-to-end mechanism—including FIFO sampling loss and PMU event fidelity—is not actually evaluated. The authors need to specify the full profiling data path or evaluate the profile mechanism's fidelity.
  2. [§3.3 / §4.1] The delivery of page hints to L2 prefetchers is under-specified. Hints are stored in PTEs/TLBs as attributes of virtual pages, but the evaluated prefetchers operate at the L2 and the paper states "we assume prefetchers are working on physical addresses; hence, there is no additional overhead to look up the page attribute values." This assumption skips the central implementation question: how does a physical-address prefetcher know the hint for a predicted address, especially for prefetches that cross page boundaries or target pages other than the triggering demand page? A TLB attribute on a demand load does not automatically provide the attribute for a prefetch target physical page. The paper should explain the hardware lookup (or attribute propagation) for prefetch targets and account for any overhead in the model.
  3. [§3.2 / §4.4, Fig. 15] The usefulness factor lambda=4 is chosen empirically on the same Google workloads used for the headline results (§3.2: "We empirically find lambda=4 to work best"; §4.4 Fig. 15 selects the peak on the evaluation set). This is a form of test-set tuning. The authors mitigate this by showing the sensitivity is modest (less than 1% average IPC difference for lambda in [2.5, 5]), but the reported mean speedup in Fig. 7 may still be slightly optimistic. The paper should either report results for a lambda chosen on a validation split or present the headline numbers across a range of lambda values to make the selection bias transparent.
  4. [§4.1 / §4.3, Fig. 12] The stability argument for the page-usefulness assumption does not fully cover the multi-core usage model. The profile is collected from a single core and then shared across all cores/threads of a multi-threaded Google workload, but Fig. 12 measures consistency across trace segments of the same workload, not across different cores or thread interleavings affecting the same physical page. A page could be prefetch-friendly for one core's access stream and not for another, or could change behavior under different interleavings. Since the correctness of the whole mechanism depends on page-level usefulness being stable enough for a one-profile-fits-all-cores approach, the paper should at least report whether the single-core profile's decisions agree with per-core profiles, or discuss why cross-core variation is not a concern for the evaluated workloads.
minor comments (5)
  1. [§4.2] The first paragraph of §4.2 says "Across seven prefetchers, geometric mean of speedup is 3.5% (0.4% for arizona, 3.1% for bravo.a, ...)." The parenthetical values are per-workload means, not per-prefetcher numbers. This should be reworded to avoid confusing the level of aggregation.
  2. [§4.2 / Fig. 8] The paper alternates between "coverage" as a fraction of LLC misses and "the number of useful prefetches." Since Themis reduces total misses, a normalized fraction can increase even if the absolute number of useful prefetches is flat. Please state explicitly whether the +5.7% coverage increase is an absolute count or a normalized fraction, and define the metric once in §2.
  3. [§3.4] The claim that PTE attribute updates cost "around 1 μs per bit" needs a brief description of how this number was measured or estimated, since it is used in the 0.2% overhead calculation.
  4. [§4.3 / Fig. 12] The histogram would benefit from reporting the number of pages included, the bin width, and whether pages appearing in only one trace were excluded (the text says at least two traces). This helps the reader judge the statistical weight of the bimodal distribution.
  5. [Throughout] There are several spacing/formatting issues in the PDF text (e.g., "Themisutilizes", "Themisis"). A final copyedit pass is needed.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: page-hint control is empirically validated out-of-sample; Equation 1 is a policy, not a tautology.

full rationale

The central derivation is not circular. Equation (1) (λ×#useful < #useless) is a policy for selecting pages on which to disable prefetching, not a mathematical identity that entails the reported reduction. The headline results—40.6% useless-prefetch reduction, 3.5% IPC improvement, and 5.7% coverage increase—are measured on evaluation regions that are disjoint from the profiling region, as stated in §4.1: 'We ensure a gap of at least 100 million instructions between the profiling region and the regions used for performance measurement.' Nothing in Eq. (1) forces the out-of-sample magnitudes or the coverage increases; they are simulator outcomes. The §4.3 stability check is also not self-referential: Figure 12 is constructed by independently recomputing the disable decision from ten traces ('we collect profiling data from ten distinct traces and then analyze how often page addresses were marked to disable prefetching'), so it tests the page-stability premise rather than assuming it. The main tuning concern is that λ=4 is selected from the same Google workload results (Fig. 15); however, the paper reports low sensitivity (<1% IPC difference across λ=2.5–5), so this is a benchmark-selection caveat rather than a structural circularity. Self-citations such as Limoncello [52] are motivational and independently supported by the in-paper data in Figure 2. The explicit limitation in §4.4—'Here, we show the results with one trace per workload due to long simulation time'—affects the bandwidth-sensitivity evidence but not the paper's central claim. No equation reduces to its input by construction, and no fitted parameter is renamed as a prediction.

Assumptions & free parameters 1 free parameters · 5 assumptions · 2 invented entities

Central claim rests on one fitted parameter (λ), several domain assumptions about workload stability/representativeness, and two proposed hardware mechanisms with no independent silicon evidence. The paper provides internal consistency data (Fig. 12, training on/off) that partially supports the stability assumption, but the evaluation does not simulate TLB propagation, page walks, or virtual-address prefetching, so those costs are assumed away.

free parameters (1)
  • λ (usefulness factor) = 4 (at 25.6 GB/s; optimal shifts to 0.5–3 for 1.6–12.8 GB/s)
    Introduced in Eq. 1; 'We empirically find λ=4 to work best' (§3.2, §4.4). It sets the disable threshold and is tuned on the same workloads used for headline results.
assumptions (5)
  • domain assumption A page's prefetch usefulness is stable over long execution windows and across cores; a 100M-instruction single-core profile generalizes to other regions.
    Used in profiling methodology §4.1 and overhead analysis §4.3 (Fig. 12). If false, directives would be stale and speedups would not transfer.
  • domain assumption Disabling prefetch and training on a page based on profile will not systematically miss high-value pages that the profiler did not observe.
    The criterion in Eq. 1 only sees sampled evictions; unsampled pages get no directive and remain enabled. Soundness depends on sample representativeness.
  • domain assumption ChampSim simulations with physical-address prefetchers and no modeled page walk/TLB propagation cost faithfully represent the proposed hardware.
    Stated §4.1: 'we assume prefetchers are working on physical addresses; hence, there is no additional overhead to look up the page attribute values.' Real L1 prefetchers may be virtual-address and hint transport has costs.
  • ad hoc to paper Prefetch-usefulness can be tracked by a cache-tag bit and sampled through a PMU FIFO without perturbing cache behavior.
    Proposed microarchitectural mechanism §3.3; no silicon or detailed cycle-level model of the FIFO is provided.
  • domain assumption Arm PBHA or equivalent PTE attribute bits exist and are propagated with each memory operation.
    Cited as existing (§3.1), but the paper's evaluation does not simulate TLB entry propagation or shootdown-free lazy updates.
invented entities (2)
  • Per-page prefetch-enable attribute bit in PTE/TLB
    purpose: Carries software-computed directive to hardware prefetcher to enable/disable training and prediction on a page.
    The bit is the core interface but only exists in the design/simulation; no real implementation or independent measurement is provided. It relies on Arm PBHA availability, but the specific prefetch-enable semantics are new.
  • Cache PMU useless-prefetch eviction FIFO
    purpose: Samples physical addresses of prefetched-but-unused cache lines for software profiling.
    Proposed hardware addition; no implementation or measured overhead is given. The LBR analogy is not a verification.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Themis: Software-Defined Hardware Prefetching." pith.science (2026). https://pith.science/paper/34JPC5RN

@misc{pith2026260800259,
  author       = {Pith},
  title        = {Pith review of: Themis: Software-Defined Hardware Prefetching},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/34JPC5RN}},
  note         = {Machine review of arXiv:2608.00259}
}
read the original abstract

Data cache misses represent a significant portion of stall cycles in datacenter workloads. Hardware prefetchers that reduce such stalls by fetching data ahead of time have become increasingly sophisticated. However, to achieve high coverage, they have to prefetch aggressively, generating many inaccurate accesses that waste memory bandwidth. This is problematic in datacenter environments where memory bandwidth is a limited resource due to high multi-tenancy. We observe that for datacenter workloads, inaccurate prefetches can be effectively filtered on a data page granularity, without sacrificing prefetch coverage. However, storing per-page metadata about prefetch usefulness in hardware is costly, so we propose a novel hardware-software interface for data prefetching: The software directs the hardware on where to prefetch, and the hardware identifies and issues prefetches in the regions of interest. We propose Themis, a profile-guided hardware prefetching solution that implements this new interface. Themis utilizes page-level hints stored in page-table entries to disable the prefetcher for certain data pages at runtime. Themis requires no binary or ISA changes and can be used to optimize processes without disrupting their execution. Themis is also orthogonal to existing works on prefetching and can be applied to optimize any hardware prefetcher. Our results show that Themis is able to achieve around 40% reduction in useless prefetch requests, resulting in speedup for all the evaluated prefetchers for datacenter workloads, including 4.1% for BOP, 3.1% for SPP+PPF, and 1.4% for Pythia.

Figures

Figures reproduced from arXiv: 2608.00259 by the authors.

Figure 1
Figure 1. Cumulative distribution of the number of pages as a function of the prefetch accuracy. The x-axis shows the per-page accuracy of the prefetcher. workloads. For example, it has shown significant improve￾ments for instruction prefetching [7], branch prediction [64] and cache replacement policies [65] by providing (1) the abil￾ity to leverage vast amounts of profiling data, (2) application￾specific customizations, and … view at source ↗
Figure 3
Figure 3. Coverage, accuracy, and IPC improvement over the original configurations of existing throttling mechanisms. We make two observations. First, the coverage (the frac￾tion of misses covered by the prefetcher) is lower on Google traces. The average coverage on Google workloads is only 25.1%, with the best-performing prefetcher (Pythia) provid￾ing 35.8% coverage. By contrast, the average coverage on SPEC is 53.0%, with t… view at source ↗
Figure 4
Figure 4. Comparison of IPC with and without CLIP for different prefetchers for Google traces. As a case study, [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Usage model of Themis. VIRT ADDR PHY ADDR ATTRIBUTE TLB Prefetcher ENABLE SIGNAL Cache PMU Eviction Buffer PF=1 RD=0 LAST LEVEL CACHE Kernel SAMPLE EVICTION BUFFER PHYS ADDR PF=1 RD=0 PGD PUD PUD PMD PMD PTE PTE Page Table PTE_SET_FLAG (NOPF) DRAM AGGREGATE PAGE STATIS…
Figure 6
Figure 6. Figure 6: Microarchitecture and profiling mechanisms of Themis. useless prefetches. As the value of 𝜆 decreases, the throttling increases, causing fewer prefetches to be emitted. We empir￾ically find 𝜆 = 4 to work best. More detail about the value of 𝜆 is discussed in §4.4. Afte…
Figure 7
Figure 7. Figure 7: IPC ratios of baseline prefetchers, Themis, and CLIP over no prefetching for Google traces. The numbers above each bar show the speedup from the baseline prefetchers (leftmost bars). Nextline BOP SPP Bingo SPP+PPF DSPatch Pythia Mean 0 50 100 150 200 250 300 350 Fracti…
Figure 9
Figure 9. Figure 9: Cache miss rates with and without Themis for L2 cache and LLC for Google traces. Nextline BOP SPP Bingo SPP+PPF DSPatch Pythia Mean 1.0 1.1 1.2 1.3 1.4 1.5 1.6 IPC Ratio Over No Prefetching +1.6% +3.8% +0.3% +0.6% +0.3% +1.8% +0.8% +1.3% -1.7% -0.8% -22.3% -14.1% -6.3%…
Figure 10
Figure 10. Figure 10: IPC of baseline prefetchers, Themis, and CLIP for SPEC2017 benchmark suite. Numbers above bars show the speedup from the baseline prefetchers (leftmost bars). Themis. We observe a reduction in the LLC and L2 cache miss rate for all the prefetchers except for SPP, wher…
Figure 13
Figure 13. Figure 13: The number of pages to be analyzed and the PTEs to be updated for Themis with 100 million instructions profile for Google traces. 256 (original) 512 1024 2048 4096 8192 SPT size 0.8 0.9 1.0 1.1 1.2 IPC Ratio Over No Prefetching (a) DSPatch w/o Themis w/ Themis 32 64 (…
Figure 12
Figure 12. Figure 12: Histogram showing how often each page has prefetching disabled. traces, while 1.3% for SPEC2017. This result shows that Themis is especially suited for optimizing the performance of datacenter applications with large instruction and memory footprints. GAP [PITH_FULL_…
Figure 16
Figure 16. Figure 16: IPC improvement over baseline prefetchers of Themis and a variant of Themis that does not disable training. 0 1 2 3 4 5 1.00 1.02 1.04 1.06 IPC improvement 1.6GB/s 3.2GB/s 6.4GB/s 12.8GB/s 25.6GB/s [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 17
Figure 17. Figure 17: Average IPC improvement of Themis with differ￾ent DRAM bandwidths as a function of usefulness factor 𝜆. To show the effect of disabled training, [PITH_FULL_IMAGE:figures/full_fig_p010_17.png]
Figure 18
Figure 18. Figure 18: Performance with simple accuracy- and bandwidth-based prefetch throttling. 256 512 1024 2048 4096 8192 16384 32768 Buffer Size 1.00 1.05 1.10 1.15 IPC Ratio Over No Prefetching Themis Baseline Prefetchers [PITH_FULL_IMAGE:figures/full_fig_p011_18.png]
Figure 19
Figure 19. Figure 19: Performance of hardware-only throttling based on page addresses with different buffer sizes (defined as the number of pages to track). prior work [4, 107]. These approaches disable prefetching when memory bandwidth utilization exceeds𝑋% and prefetch accuracy falls bel…

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

128 extracted references · 3 linked inside Pith

  1. [1]

    Sam Ainsworth and Timothy M Jones. 2017. Software prefetching for indirect memory accesses. In2017 IEEE/ACM International Sym- posium on Code Generation and Optimization (CGO). 305–317

    2017

  2. [2]

    Sam Ainsworth and Lev Mukhanov. 2024. Triangel: A High- Performance, Accurate, Timely On-Chip Temporal Prefetcher. In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, 1202–1216

    2024

  3. [3]

    Arm. [n. d.]. Page-based hardware attributes.https: //developer.arm.com/documentation/100798/0401/Memory- Management-Unit/Page-based-hardware-attributesAccessed: July 28, 2026

    2026

  4. [4]

    2025.Use of CBusy.https://developer.arm.com/ documentation/109252/latest/MPAM-System-Guidance-for- Infrastructure/Use-of-CBusyAccessed: July 28, 2026

    Arm Ltd. 2025.Use of CBusy.https://developer.arm.com/ documentation/109252/latest/MPAM-System-Guidance-for- Infrastructure/Use-of-CBusyAccessed: July 28, 2026

    2025

  5. [5]

    Grant Ayers, Jung Ho Ahn, Christos Kozyrakis, and Parthasarathy Ranganathan. 2018. Memory hierarchy for web search. In2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 643–656

    2018

  6. [6]

    Grant Ayers, Heiner Litz, Christos Kozyrakis, and Parthasarathy Ran- ganathan. 2020. Classifying memory access patterns for prefetching. InProceedings of the Twenty-Fifth International Conference on Archi- tectural Support for Programming Languages and Operating Systems. 513–526

    2020

  7. [7]

    Grant Ayers, Nayana Prasad Nagendra, David I August, Hyoun Kyu Cho, Svilen Kanev, Christos Kozyrakis, Trivikram Krishnamurthy, Heiner Litz, Tipp Moseley, and Parthasarathy Ranganathan. 2019. Asmdb: understanding and mitigating front-end stalls in warehouse- scale computers. InProceedings of the 46th International Symposium on Computer Architecture. 462–473

    2019

  8. [8]

    Jean-Loup Baer and Tien-Fu Chen. 1991. An effective on-chip preload- ing scheme to reduce data access penalty. InProceedings of the 1991 ACM/IEEE conference on Supercomputing. 176–186

    1991

Show all 128 references
  1. [9]

    Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad. 2018. Domino temporal data prefetcher. In2018 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 131–142

    2018

  2. [10]

    Mohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi- Kamran, and Hamid Sarbazi-Azad. 2019. Accurately and maximally prefetching spatial data access patterns with bingo.The 3rd Data Prefetching Championship (DPC3)(2019)

    2019

  3. [11]

    Mohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi- Kamran, and Hamid Sarbazi-Azad. 2019. Bingo spatial data prefetcher. In2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 399–411

    2019

  4. [12]

    Scott Beamer, Krste Asanović, and David Patterson. 2015. The GAP benchmark suite.arXiv preprint arXiv:1508.03619(2015)

    2015 arXiv

  5. [13]

    Michael Bekerman, Stephan Jourdan, Ronny Ronen, Gilad Kirshen- boim, Lihu Rappoport, Adi Yoaz, and Uri Weiser. 1999. Correlated load-address predictors.ACM SIGARCH Computer Architecture News 27, 2 (1999), 54–63

    1999

  6. [14]

    Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, and Onur Mutlu. 2022. Hermes: Accelerating long-latency load requests via perceptron-based off-chip load prediction. In2022 55th IEEE/ACM International Symposium on M...

    2022

  7. [15]

    Rahul Bera, Konstantinos Kanellopoulos, Anant Nori, Taha Shahroodi, Sreenivas Subramoney, and Onur Mutlu. 2021. Pythia: A customizable hardware prefetching framework using online rein- forcement learning. InMICRO-54: 54th Annual IEEE/ACM Interna- tional Symposium on Microarchi...

    2021

  8. [16]

    Rahul Bera, Anant V Nori, Onur Mutlu, and Sreenivas Subramoney

  9. [17]

    Eshan Bhatia, Gino Chacon, Seth Pugsley, Elvira Teran, Paul V Gratz, and Daniel A Jiménez. 2019. Perceptron-based prefetch filtering. In Proceedings of the 46th International Symposium on Computer Archi- tecture. 1–13

    2019

  10. [18]

    Eshan Bhatia, Gino Chacon, Elvira Teran, Paul V Gratz, and Daniel A Jiménez. 2019. Enhancing signature path prefetching with perceptron prefetch filtering.The 3rd Data Prefetching Championship (DPC3) (2019)

    2019

  11. [19]

    David Callahan, Ken Kennedy, and Allan Porterfield. 1991. Software prefetching.ACM SIGARCH Computer Architecture News19, 2 (1991), 40–52

    1991

  12. [20]

    Robert S Chappell, Jared Stark, Sangwook P Kim, Steven K Reinhardt, and Yale N Patt. 1999. Simultaneous subordinate microthreading (SSMT). InProceedings of the 26th annual international symposium 12 on Computer architecture. 186–195

    1999

  13. [21]

    Tien-Fu Chen and Jean-Loup Baer. 1995. Effective hardware-based data prefetching for high-performance processors.IEEE transactions on computers44, 5 (1995), 609–623

    1995

  14. [22]

    Trishul M Chilimbi and Martin Hirzel. 2002. Dynamic hot data stream prefetching for general-purpose programs. InProceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation. 199–209

    2002

  15. [23]

    Yuan Chou. 2007. Low-cost epoch-based correlation prefetching for commercial applications. In40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007). IEEE, 301–313

    2007

  16. [24]

    Jamison D Collins, Dean M Tullsen, Hong Wang, and John Paul Shen

  17. [25]

    Jamison D Collins, Hong Wang, Dean M Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, and John P Shen. 2001. Speculative precomputation: Long-range prefetching of delinquent loads.ACM SIGARCH Computer Architecture News29, 2 (2001), 14–25

    2001

  18. [26]

    Robert Cooksey, Stephan Jourdan, and Dirk Grunwald. 2002. A state- less, content-directed data prefetching mechanism.ACM SIGPLAN Notices37, 10 (2002), 279–290

    2002

  19. [27]

    CVP1. 2018. The 1st championship value prediction.https: //microarch.org/cvp1/cvp1/index.htmAccessed: July 28, 2026

    2018

  20. [28]

    DPC2. 2015. The 2nd data prefetching championship.https:// comparch-conf.gatech.edu/dpc2/Accessed: July 28, 2026

    2015

  21. [29]

    DPC3. 2019. The 3rd data prefetching championship.https://dpc3. compas.cs.stonybrook.eduAccessed: July 28, 2026

    2019

  22. [30]

    James Dundas and Trevor Mudge. 1997. Improving data cache perfor- mance by pre-executing instructions under a cache miss. InProceed- ings of the 11th international conference on Supercomputing. 68–75

    1997

  23. [31]

    Quang Duong, Akanksha Jain, and Calvin Lin. 2024. A New For- mulation of Neural Data Prefetching. In2024 ACM/IEEE 51st An- nual International Symposium on Computer Architecture (ISCA). IEEE, 1173–1187

    2024

  24. [32]

    DynamoRIO. [n. d.]. DynamoRIO: Dynamic Instrumentation Tool Platform.https://github.com/DynamoRIO/dynamorioAccessed: July 28, 2026

    2026

  25. [33]

    Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, and Yale N Patt. 2009. Coordinated control of multiple prefetchers in multi-core systems. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 316–326

    2009

  26. [34]

    Eiman Ebrahimi, Onur Mutlu, and Yale N Patt. 2009. Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. In2009 IEEE 15th International Symposium on High Performance Computer Architecture. 7–17

    2009

  27. [35]

    2014.A Primer on Hardware Prefetching

    Babak Falsafi and Thomas F Wenisch. 2014.A Primer on Hardware Prefetching. Morgan & Claypool Publishers

    2014

  28. [36]

    Michael Ferdman, Almutaz Adileh, Onur Kocberber, Stavros Volos, Mohammad Alisafaee, Djordje Jevdjic, Cansu Kaynak, Adrian Daniel Popescu, Anastasia Ailamaki, and Babak Falsafi. 2012. Clearing the clouds: a study of emerging scale-out workloads on modern hardware. Acm sigplan n...

    2012

  29. [37]

    Michael Ferdman and Babak Falsafi. 2007. Last-touch correlated data streaming. In2007 IEEE International Symposium on Performance Analysis of Systems & Software. IEEE, 105–115

    2007

  30. [38]

    Gelin Fu, Tian Xia, Zhongpei Luo, Ruiyang Chen, Wenzhe Zhao, and Pengju Ren. 2024. Differential-Matching Prefetcher for Indi- rect Memory Access. In2024 IEEE International Symposium on High- Performance Computer Architecture (HPCA). IEEE, 439–453

    2024

  31. [39]

    John WC Fu, Janak H Patel, and Bob L Janssens. 1992. Stride directed prefetching in scalar processors.ACM SIGMICRO Newsletter23, 1-2 (1992), 102–110

    1992

  32. [40]

    Gerasimos Gerogiannis and Josep Torrellas. 2023. Micro-Armed Ban- dit: Lightweight & reusable reinforcement learning for microarchi- tecture decision-making. InProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture. 698–713

    2023

  33. [41]

    Nathan Gober, Gino Chacon, Lei Wang, Paul V Gratz, Daniel A Jimenez, Elvira Teran, Seth Pugsley, and Jinchun Kim. 2022. The championship simulator: Architectural simulation for education and competition.arXiv preprint arXiv:2210.14324(2022)

    2022 arXiv

  34. [42]

    Google. [n. d.]. Google Workload Traces Version 2.https://storage. googleapis.com/external-traces-v2/Accessed: July 28, 2026

    2026

  35. [43]

    Milad Hashemi, Onur Mutlu, and Yale N Patt. 2016. Continuous runahead: Transparent hardware acceleration for memory intensive workloads. In2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 1–12

    2016

  36. [44]

    Milad Hashemi and Yale N Patt. 2015. Filtered runahead execution with a runahead buffer. InProceedings of the 48th International Sym- posium on Microarchitecture. 358–369

    2015

  37. [45]

    Milad Hashemi, Kevin Swersky, Jamie Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, and Parthasarathy Ran- ganathan. 2018. Learning memory access patterns. InInternational Conference on Machine Learning. PMLR, 1919–1928

    2018

  38. [46]

    Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, and Ibrahim Hur. 2018. Near-side prefetch throttling: Adaptive prefetching for high-performance many-core processors. InProceed- ings of the 27th International Conference on Parallel Architectures and Compilation ...

    2018

  39. [47]

    Zhigang Hu, Margaret Martonosi, and Stefanos Kaxiras. 2003. TCP: Tag correlating prefetchers. InThe Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Pro- ceedings.IEEE, 317–326

    2003

  40. [48]

    Sorin Iacobovici, Lawrence Spracklen, Sudarshan Kadambi, Yuan Chou, and Santosh G Abraham. 2004. Effective stream-based and execution-based data prefetching. InProceedings of the 18th annual international conference on Supercomputing. 1–11

    2004

  41. [49]

    Intel. 2016. Intel®64 and IA-32 Architectures Software Devel- oper’s Manual Volume 3A: System Programming Guide, Part 1.https://www.intel.com/content/dam/www/public/us/en/ documents/manuals/64-ia-32-architectures-software-developer- vol-3a-part-1-manual.pdfAccessed: July 28, 2026

    2016

  42. [50]

    Yasuo Ishii, Mary Inaba, and Kei Hiraki. 2009. Access map pattern matching for data cache prefetch. InProceedings of the 23rd interna- tional conference on Supercomputing. 499–500

    2009

  43. [51]

    Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. InProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture. 247–259

    2013

  44. [52]

    Akanksha Jain, Hannah Lin, Carlos Villavieja, Baris Kasikci, Chris Kennelly, Milad Hashemi, and Parthasarathy Ranganathan. 2024. Limoncello: Prefetchers for Scale. InProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Ope...

    2024

  45. [53]

    Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A Jiménez, Lluc Alvarez, and Marc Casas. 2024. A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. In 2024 IEEE International Symposium on High-Performance Computer Architecture (HPC...

    2024

  46. [54]

    Saba Jamilan, Tanvir Ahmed Khan, Grant Ayers, Baris Kasikci, and Heiner Litz. 2022. Apt-get: Profile-guided timely software prefetching. InProceedings of the Seventeenth European Conference on Computer Systems. 747–764

    2022

  47. [55]

    Lin Jia, James Patrick Mcmahon, Sumanth Gudaparthi, Shreyas Singh, and Rajeev Balasubramonian. 2024. PATHFINDER: Practical Real- Time Learning for Data Prefetching. InProceedings of the 29th ACM International Conference on Architectural Support for Programming 13 Languages and...

    2024

  48. [56]

    Doug Joseph and Dirk Grunwald. 1997. Prefetching using markov predictors. InProceedings of the 24th annual international symposium on Computer architecture. 252–263

    1997

  49. [57]

    Norman P Jouppi. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. ACM SIGARCH Computer Architecture News18, 2SI (1990), 364–373

    1990

  50. [58]

    Changhee Jung, Daeseob Lim, Jaejin Lee, and Yan Solihin. 2006. Helper thread prefetching for loosely-coupled multiprocessor sys- tems. InProceedings 20th IEEE International Parallel & Distributed Processing Symposium. IEEE, 10–pp

    2006

  51. [59]

    David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, and Daniel Jimenez. 2014. B-fetch: Branch prediction directed prefetching for chip-multiprocessors. In2014 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 623–634

    2014

  52. [60]

    Svilen Kanev, Juan Pablo Darago, Kim Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, and David Brooks. 2015. Profiling a warehouse-scale computer. InProceedings of the 42nd Annual International Symposium on Computer Architecture. 158–169

    2015

  53. [61]

    Magnus Karlsson, Fredrik Dahlgren, and Per Stenstrom. 2000. A prefetching technique for irregular accesses to linked data structures. InProceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No. PR00550). IEEE, 206–217

    2000

  54. [62]

    Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subra- money, Gilles A Pokam, Heiner Litz, and Baris Kasikci. 2021. Twig: Profile-guided btb prefetching for data center applications. InMICRO- 54: 54th Annua...

    2021

  55. [63]

    Tanvir Ahmed Khan, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz, and Baris Kasikci. 2020. I-spy: Context-driven conditional instruction prefetching with coalescing. In2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MI- CRO). IEEE, 146–159

    2020

  56. [64]

    Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A Jiménez, and Baris Kasikci. 2022. Whisper: Profile-guided branch misprediction elimination for data center applications. In2022 55th IEEE/ACM International Symposium on Microarchitecture ...

    2022

  57. [65]

    Tanvir Ahmed Khan, Dexin Zhang, Akshitha Sriraman, Joseph De- vietti, Gilles Pokam, Heiner Litz, and Baris Kasikci. 2021. Ripple: Profile-guided instruction cache replacement for data center appli- cations. In2021 ACM/IEEE 48th Annual International Symposium on Computer Archit...

    2021

  58. [66]

    Jinchun Kim, Paul V Gratz, and A. L. Narasimha Reddy. 2015. Looka- head prefetching with signature path.The 2nd Data Prefetching Championship (DPC2)(2015)

    2015

  59. [67]

    Jinchun Kim, Seth H Pugsley, Paul V Gratz, AL Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. Path confidence based lookahead prefetching. In2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 1–12

    2016

  60. [68]

    Sushant Kondguli and Michael Huang. 2018. Division of labor: A more effective approach to prefetching. In2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, 83– 95

    2018

  61. [69]

    Sanjeev Kumar and Christopher Wilkerson. 1998. Exploiting spatial locality in data caches using spatial footprints. InProceedings of the 25th Annual International Symposium on Computer Architecture. 357–368

    1998

  62. [70]

    Wei-Fen Lin, Steven K Reinhardt, and Doug Burger. 2001. Reducing DRAM latencies with an integrated memory hierarchy design. InPro- ceedings HPCA Seventh International Symposium on High-Performance Computer Architecture. 301–312

    2001

  63. [71]

    Linux. 2019. mm_types.h: struct page.https://elixir.bootlin.com/ linux/v5.4.2/source/include/linux/mm_types.h#L30Accessed: July 28, 2026

    2019

  64. [72]

    Linux. 2019. pgtable.h: pte_set_flags.https://elixir.bootlin.com/ linux/v5.4.2/source/arch/x86/include/asm/pgtable.h#L299Accessed: July 28, 2026

    2019

  65. [73]

    Linux. 2019. rmap.c: reverse mapping.https://elixir.bootlin.com/ linux/v5.4.2/source/mm/rmap.cAccessed: July 28, 2026

    2019

  66. [74]

    Heiner Litz, Grant Ayers, and Parthasarathy Ranganathan. 2022. CRISP: critical slice prefetching. InProceedings of the 27th ACM In- ternational Conference on Architectural Support for Programming Lan- guages and Operating Systems. 300–313

    2022

  67. [75]

    Chi-Keung Luk. 2001. Tolerating memory latency through software- controlled pre-execution in simultaneous multithreading processors. InProceedings of the 28th annual international symposium on Com- puter architecture. 40–51

    2001

  68. [76]

    Pierre Michaud. 2015. A best-offset prefetcher.The 2nd Data Prefetch- ing Championship (DPC2)(2015)

    2015

  69. [77]

    Pierre Michaud. 2016. Best-offset hardware prefetching. In2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 469–480

    2016

  70. [78]

    Todd C Mowry, Monica S Lam, and Anoop Gupta. 1992. Design and evaluation of a compiler algorithm for prefetching.ACM SIGPLAN Notices27, 9 (1992), 62–73

    1992

  71. [79]

    Onur Mutlu, Saugata Ghose, Juan Gómez-Luna, and Rachata Ausavarungnirun. 2022. A modern primer on processing in memory. InEmerging computing: from devices to systems: looking beyond Moore and Von Neumann. Springer, 171–243

    2022

  72. [80]

    Onur Mutlu, Hyesoon Kim, and Yale N Patt. 2005. Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns. In38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’05). IEEE, 233–244

    2005

  73. [81]

    Onur Mutlu, Hyesoon Kim, and Yale N Patt. 2005. Techniques for effi- cient processing in runahead execution engines. In32nd International Symposium on Computer Architecture (ISCA’05). IEEE, 370–381

    2005

  74. [82]

    Onur Mutlu, Hyesoon Kim, and Yale N Patt. 2006. Efficient runahead execution: Power-efficient memory latency tolerance.IEEE Micro26, 1 (2006), 10–20

    2006

  75. [83]

    Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N Patt. 2005. On reusing the results of pre-executed instructions in a runahead ex- ecution processor.IEEE Computer Architecture Letters4, 1 (2005), 2–2

    2005

  76. [84]

    Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N Patt. 2003. Runahead execution: An alternative to very large instruction win- dows for out-of-order processors. InThe Ninth International Sympo- sium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings....

    2003

  77. [85]

    Ajeya Naithani, Sam Ainsworth, Timothy M Jones, and Lieven Eeck- hout. 2021. Vector runahead. In2021 ACM/IEEE 48th Annual Interna- tional Symposium on Computer Architecture (ISCA). IEEE, 195–208

    2021

  78. [86]

    Carlos Navarro, Josué Feliu, Salvador Petit, Maria E Gomez, and Julio Sahuquillo. 2020. Bandwidth-aware dynamic prefetch configuration for IBM POWER8.IEEE Transactions on Parallel and Distributed Systems31, 8 (2020), 1970–1982

    2020

  79. [87]

    Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey- Benedé, Pablo Ibáñez, Víctor Viñals-Yúfera, and Alberto Ros

  80. [88]

    Guilherme Ottoni and Bin Liu. 2021. HHVM jump-start: Boost- ing both warmup and steady-state performance at scale. In2021 IEEE/ACM International Symposium on Code Generation and Opti- mization (CGO). IEEE, 340–350. 14

    2021

  81. [89]

    Samuel Pakalapati and Biswabandan Panda. 2020. Bouquet of instruc- tion pointers: Instruction pointer classifier-based spatial hardware prefetching. In2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 118–131

    2020

  82. [90]

    Maksim Panchenko, Rafael Auler, Laith Sakka, and Guilherme Ottoni

  83. [91]

    Biswabandan Panda. 2016. SPAC: A synergistic prefetcher aggres- siveness controller for multi-core systems.IEEE Trans. Comput.65, 12 (2016), 3740–3753

    2016

  84. [92]

    Biswabandan Panda. 2023. CLIP: Load criticality based data prefetch- ing for bandwidth-constrained many-core systems. InProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchi- tecture. 714–727

    2023

  85. [93]

    Leeor Peled, Shie Mannor, Uri Weiser, and Yoav Etsion. 2015. Se- mantic locality and context-based prefetching using reinforcement learning. InProceedings of the 42nd Annual International Symposium on Computer Architecture. 285–297

    2015

  86. [94]

    Seth H Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, and Rajeev Balasubramonian. 2014. Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers. In2014 IEEE 20th International Symposium on Hi...

    2014

  87. [95]

    Tanausu Ramirez, Alex Pajuelo, Oliverio J Santana, and Mateo Valero

  88. [96]

    Alberto Ros. 2019. Berti: A per-page best-request-time delta prefetcher.The 3rd Data Prefetching Championship (DPC3)(2019)

    2019

  89. [97]

    Mehran Shakerinava, Mohammad Bakhshalipour, Pejman Lotfi- Kamran, and Hamid Sarbazi-Azad. 2019. Multi-lookahead offset prefetching.The 3rd Data Prefetching Championship (DPC3)(2019)

    2019

  90. [98]

    Zhan Shi, Akanksha Jain, Kevin Swersky, Milad Hashemi, Parthasarathy Ranganathan, and Calvin Lin. 2019. A neural hier- archical sequence model for irregular data prefetching. InML For Systems Workshop, NeurIPS

    2019

  91. [99]

    Zhan Shi, Akanksha Jain, Kevin Swersky, Milad Hashemi, Parthasarathy Ranganathan, and Calvin Lin. 2021. A hierarchical neural model of data prefetching. InProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Syst...

    2021

  92. [100]

    Zhan Shi, Kevin Swersky, Daniel Tarlow, Parthasarathy Ranganathan, and Milad Hashemi. 2019. Learning execution through neural code fusion.arXiv preprint arXiv:1906.07181(2019)

    2019 arXiv

  93. [101]

    Alan Jay Smith. 1978. Sequential program prefetching in memory hierarchies.Computer11, 12 (1978), 7–21

    1978

  94. [102]

    Yan Solihin, Jaejin Lee, and Josep Torrellas. 2002. Using a user-level memory thread for correlation prefetching.ACM SIGARCH Computer Architecture News30, 2 (2002), 171–182

    2002

  95. [103]

    Stephen Somogyi, Thomas F Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming.ACM SIGARCH Computer Architecture News37, 3 (2009), 69–80

    2009

  96. [104]

    Stephen Somogyi, Thomas F Wenisch, Anastassia Ailamaki, Babak Falsafi, and Andreas Moshovos. 2006. Spatial memory streaming. ACM SIGARCH Computer Architecture News34, 2 (2006), 252–263

    2006

  97. [105]

    Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh Shahri, Ak- shitha Sriraman, Niranjan K Soundararajan, Sreenivas Subramoney, Daniel A Jiménez, Heiner Litz, and Baris Kasikci. 2022. Thermome- ter: profile-guided btb replacement for data center applications. In Proceedings of th...

    2022

  98. [106]

    SPEC. 2017. SPEC CPU 2017.https://www.spec.org/cpu2017/ Accessed: July 28, 2026

    2017

  99. [107]

    Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N Patt. 2007. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In2007 IEEE 13th International Symposium on High Performance Computer Architecture. IEEE, 63–74

    2007

  100. [108]

    Akshitha Sriraman and Abhishek Dhanotia. 2020. Accelerometer: Un- derstanding acceleration opportunities for data center overheads at hyperscale. InProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems...

    2020

  101. [109]

    Elvira Teran, Zhe Wang, and Daniel A Jiménez. 2016. Perceptron learning for reuse prediction. In2016 49th Annual IEEE/ACM Interna- tional Symposium on Microarchitecture (MICRO). IEEE, 1–12

    2016

  102. [110]

    Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V Gratz, Daniel A Jiménez, and Marc Casas. 2022. Page Size Aware Cache Prefetching. In2022 55th IEEE/ACM International Symposium on Mi- croarchitecture (MICRO). IEEE, 956–974

    2022

  103. [111]

    Georgios Vavouliotis, Marti Torrents, Boris Grot, Kleovoulos Kalaitzidis, Leeor Peled, and Marc Casas. 2025. To Cross, or Not to Cross Pages for Prefetching?. In2025 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 188–203

    2025

  104. [112]

    Perry H Wang, Jamison D Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B Yunus, Terry Sych, Stephen F Moore, and John P Shen. 2004. Helper threads via virtual multithread- ing on an experimental itanium®2 processor-based platform.ACM SIGPLAN Notices39, 11 ...

    2004

  105. [113]

    Zhenlin Wang, Doug Burger, Kathryn S McKinley, Steven K Rein- hardt, and Charles C Weems. 2003. Guided region prefetching: A cooperative hardware/software approach.ACM SIGARCH Computer Architecture News31, 2 (2003), 388–398

    2003

  106. [114]

    Thomas F Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and Andreas Moshovos. 2009. Practical off-chip meta-data for temporal memory streaming. In2009 IEEE 15th International Symposium on High Performance Computer Architecture. IEEE, 79– 90

    2009

  107. [115]

    Thomas F Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and Andreas Moshovos. 2010. Making address-correlated prefetching practical.IEEE micro30, 1 (2010), 50–59

    2010

  108. [116]

    Thomas F Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jang- woo Kim, Anastassia Ailamaki, and Babak Falsafi. 2005. Temporal streaming of shared memory. In32nd International Symposium on Computer Architecture (ISCA’05). IEEE, 222–233

    2005

  109. [117]

    Hao Wu, Krishnendra Nathella, Joseph Pusdesris, Dam Sunwoo, Akanksha Jain, and Calvin Lin. 2019. Temporal prefetching without the off-chip metadata. InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. 996–1008

    2019

  110. [118]

    Hao Wu, Krishnendra Nathella, Dam Sunwoo, Akanksha Jain, and Calvin Lin. 2019. Efficient metadata management for irregular data prefetching. InProceedings of the 46th International Symposium on Computer Architecture. 449–461

    2019

  111. [119]

    Weifeng Zhang, Dean M Tullsen, and Brad Calder. 2007. Accelerating and adapting precomputation threads for effcient prefetching. In2007 IEEE 13th International Symposium on High Performance Computer Architecture. IEEE, 85–95

    2007

  112. [120]

    Yuxuan Zhang, Tanvir Ahmed Khan, Gilles Pokam, Baris Kasikci, Heiner Litz, and Joseph Devietti. 2022. OCOLOS: Online COde Layout OptimizationS. In2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 530–545

    2022

  113. [121]

    Yuxuan Zhang, Tanvir Ahmed Khan, Gilles Pokam, Baris Kasikci, Heiner Litz, and Joseph Devietti. 2023. Online COde Layout Opti- mizationS via OCOLOS.IEEE Micro43, 4 (2023), 71–79. 15

    2023

  114. [122]

    Yuxuan Zhang, Nathan Sobotka, Soyoon Park, Saba Jamilan, Tan- vir Ahmed Khan, Baris Kasikci, Gilles A Pokam, Heiner Litz, and Joseph Devietti. 2024. RPG2: Robust Profile-Guided Runtime Prefetch Generation. InProceedings of the 29th ACM International Conference on Architectural...

    2024

  115. [123]

    Craig Zilles and Gurindar Sohi. 2001. Execution-based prediction using speculative slices. InProceedings of the 28th annual international symposium on Computer architecture. 2–13. 16

    2001

  116. [2001]

    InProceedings

    Dynamic speculative precomputation. InProceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34. IEEE, 306–317

  117. [2008]

    In2008 IEEE 14th International Symposium on High Performance Computer Archi- tecture

    Runahead threads to improve SMT performance. In2008 IEEE 14th International Symposium on High Performance Computer Archi- tecture. IEEE, 149–158

  118. [2019]

    InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

    Dspatch: Dual spatial pattern prefetcher. InProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. 531–544

  119. [2021]

    InProceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction

    Lightning BOLT: powerful, fast, and scalable binary optimiza- tion. InProceedings of the 30th ACM SIGPLAN International Conference on Compiler Construction. 119–130

  120. [2022]

    In2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

    Berti: an Accurate Local-Delta Data Prefetcher. In2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 975–991

Pith tools

Reviewed August 4, 2026 · model on record in the stance chip above.