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arxiv: 2606.22635 · v1 · pith:3OULD5NUnew · submitted 2026-06-21 · 💻 cs.ET · cs.AR· cs.NE

Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming

Poornima Kumaresan , Santhosh Sivasubramani This is my paper

Pith reviewed 2026-06-26 09:20 UTC · model grok-4.3

classification 💻 cs.ET cs.ARcs.NE
keywords neuromorphic hardwaredigital IP blocksSTDP controllerstochastic LIF neuronPVT sensormemristive crossbarSPI interfaceSkyWater 130 nm
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The pith

Four digital IP blocks for neuromorphic edge hardware share one SPI register interface and one verification flow.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents four standard-cell CMOS blocks designed to work together in compact edge neuromorphic systems. One block senses process voltage and temperature while also generating random numbers and monitoring health. A second implements a stochastic leaky integrate-and-fire neuron with programmable activation and refractory behavior. A third provides on-chip spike-timing-dependent plasticity with multiple learning modes. The fourth controls memristive crossbars for forming, set, reset, read and sweep operations. All four blocks use the same serial peripheral interface register file, occupy one tile each at 50 MHz, and were taken through an open 130 nm implementation flow with full register-transfer and gate-level verification.

Core claim

The paper establishes that a coherent, openly released set of four interface-compatible digital IP blocks can be built on the SkyWater 130 nm process: a PVT sensor built from selectable ring oscillators that also supplies a jitter-based true-random-number generator, a stochastic LIF neuron with configurable LFSR and activation table, an on-chip STDP controller with programmable curve and reward-modulated modes, and a memristive-crossbar controller supporting forming, set, reset, read and automated sweeps. The blocks share a common SPI register file, each fits in one tile, passes 99 cocotb tests, meets timing at 50 MHz, and draws 0.64 to 0.70 mW in post-synthesis estimates, with all results o

What carries the argument

The common SPI register file that unifies the four blocks and enables a single verification flow across sensing, stochastic inference, local learning and crossbar programming.

If this is right

  • Designers can drop any combination of the four blocks into a larger neuromorphic ASIC without redesigning the control interface.
  • The shared register file allows a single software driver to configure sensing, neuron behavior, plasticity rules and crossbar operations.
  • The open standard-cell flow and 99 passing cocotb tests provide a reusable verification template for similar mixed neuromorphic-digital designs.
  • Each block maps to roughly 9-11 thousand square micrometres and 61-70 percent tile utilisation, giving predictable area budgets for larger arrays.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The unified interface could shorten the time needed to prototype hybrid digital-analogue neuromorphic systems that combine these functions with emerging memory.
  • Releasing the blocks openly may encourage community reuse and incremental improvement of the STDP modes or crossbar controller without starting from scratch.
  • Because the PVT sensor also supplies random numbers, future chips could use the same silicon area for both calibration and stochastic computation without extra hardware.

Load-bearing premise

The post-synthesis simulation and timing analysis will match the behavior of the designs once they are fabricated in silicon.

What would settle it

Fabricate the submitted Tiny Tapeout chip and confirm that each of the four blocks operates at 50 MHz with positive setup and hold margin while consuming power within the reported 0.64-0.70 mW range under the default activity assumption.

Figures

Figures reproduced from arXiv: 2606.22635 by Poornima Kumaresan, Santhosh Sivasubramani.

Figure 1
Figure 1. Figure 1: Intended composition of the four neuromorphic blocks. The dashed arrows show the design-level dataflow for which the blocks were made interface-compatible: PVT characterisation feeding stochastic inference, spike-timing-dependent learning, and crossbar programming. All four blocks share a serial peripheral interface register bus; the ring-oscillator sensor additionally exposes a direct parallel readout. Ea… view at source ↗
Figure 2
Figure 2. Figure 2: Shared serial interface. The 16-bit command frame carries a read/write bit, a seven-bit address, and an eight-bit data field, transferred most significant bit first. The timing diagram shows a mode-0 transaction in which the address phase is presented on the host data line and read data is returned on the device data line during the second byte. a 16-bit frame whose first bit selects read or write, the nex… view at source ↗
Figure 3
Figure 3. Figure 3: Modelled response of three representative on-chip ring oscillators (7, 11, and 15 stages). (a) Normalised frequency, referenced to the seven-stage ring at 1.8 V, against supply voltage at room temperature. (b) Normalised frequency, referenced to the seven-stage ring at the cold corner, against temperature at a 1.2 V supply. The trends follow an alpha-power stage-delay model and indicate the monotonic depen… view at source ↗
Figure 4
Figure 4. Figure 4: Datapath of the stochastic leaky integrate-and-fire neuron. The configurable linear-feedback shift register supplies an address to the activation table and a comparison value. A successful comparison or an external spike drives the saturating membrane integrator, which leaks each idle cycle and emits a spike with reset when the upper byte of the membrane reaches the programmed threshold. 6 [PITH_FULL_IMAG… view at source ↗
Figure 5
Figure 5. Figure 5: Simulated neuron behaviour from the register-transfer model. (a) Membrane potential and emitted spikes using a maximal-length polynomial, showing accumulation toward the threshold followed by reset. (b) Mean firing rate against the thresh￾old register value, demonstrating monotonic rate control over the configured range. 0 1 2 3 4 5 6 7 activation LUT entry (LFSR[15:13]) 0.0 0.2 0.4 0.6 0.8 1.0 P(stochasti… view at source ↗
Figure 6
Figure 6. Figure 6: Stochastic transfer behaviour of the neuron from the register-transfer model, using a maximal-length polynomial (period 65535). (a) The per-state stochastic-fire probability matches the programmed activation table divided by 256, a by-construction check that the pseudorandom source is uniform across states. (b) The mean output spike rate increases monotonically with the input weight code in host-driven mod… view at source ↗
Figure 7
Figure 7. Figure 7: STDP learning controller. Pre- and post-synaptic timestamps are captured against an eight-bit counter, their signed difference indexes a programmable plasticity table split into potentiation and depression halves, and the result is scaled by a learning rate. A four-state machine sequences the computation and supports single-shot and continuous operation. a zero time difference is classified as potentiation… view at source ↗
Figure 8
Figure 8. Figure 8: Three-factor extensions of the learning controller. (a) The base spike-timing update passes through an optional sign inversion for the anti-Hebbian mode and is then released by a reward gate that is enabled only while the eligibility trace is non￾zero, so the committed change is the base update gated by reward and recent activity rather than a function of the decayed trace level. (b) The eligibility trace … view at source ↗
Figure 9
Figure 9. Figure 9: Default on-chip plasticity curve held in the eight-entry table. Potentiation entries apply for a positive spike-time difference and depression entries for a negative difference. The values implement an asymmetric characteristic; the dashed curves are guides to the eye for the default entries, which are fully programmable. 10 [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Crossbar controller operation. A seven-state machine sequences forming, set, reset, read, and an automated sweep over an eight-by-eight device array, with an inter-pulse gap state for pulse trains. Programming pulses of configurable width are applied through a digital-to-analogue code, and an external analogue-to-digital converter returns the sensed value with a ready handshake or a timeout. 7. Memristive… view at source ↗
Figure 11
Figure 11. Figure 11: Control and datapath timing of a crossbar SET operation. After the start command the controller asserts the row and column enables, drives the programming pulse for the configured width, waits in the sense phase for the converter ready handshake, and reports completion before returning to idle. A read operation follows the same sequence but skips the pulse phase [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Serial register maps of the four blocks. A common layout places a control register at address zero and a status register near the top of the lower half (address seven for the three programmable blocks, address six for the sensor), with read-only result registers and the eight-entry lookup tables occupying the upper half of the address space where present [PITH_FULL_IMAGE:figures/full_fig_p013_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Implementation summary from the open standard-cell flow. (a) Placed standard-cell utilisation per tile. (b) Post￾synthesis standard-cell area per tile in square micrometres. Ring-oscillator sensor (tile 454) Stochastic LIF neuron (tile 460) STDP controller (tile 458) Crossbar controller (tile 456) Post-route standard-cell layout of the four blocks (SkyWater 130 nm, Tiny Tapeout 1x1 tiles) [PITH_FULL_IMAG… view at source ↗
Figure 14
Figure 14. Figure 14: Post-route standard-cell layout of the four blocks on the SkyWater 130 nm process. Each block is hardened as a single Tiny Tapeout 1x1 tile (about 161 by 112 µm) and rendered from the routed GDSII produced by the open flow on the ttsky26a shuttle. These are layout renders, not measured silicon [PITH_FULL_IMAGE:figures/full_fig_p015_14.png] view at source ↗
read the original abstract

Edge neuromorphic systems need compact, configurable hardware that combines probabilistic inference, local learning, and an interface to emerging analogue memory. We present four interface-compatible digital IP blocks implemented as standard-cell CMOS on the SkyWater 130 nm process: a process, voltage and temperature (PVT) sensor built from five selectable ring oscillators that also provides a jitter-based true-random-number generator and a frequency-bounds health monitor; a stochastic leaky integrate-and-fire (LIF) neuron with a configurable LFSR, a programmable activation table, and a refractory period; an on-chip spike-timing-dependent plasticity (STDP) controller with a programmable curve and reward-modulated, eligibility-trace, and anti-Hebbian modes; and a memristive-crossbar controller supporting forming, set, reset, read, and automated current-voltage sweep with current-compliance limiting and half-select biasing. All four blocks share a common serial peripheral interface (SPI) register file; the sensor also exposes a parallel readout. Each occupies a single tile at a 50 MHz target. The suite was verified with 99 cocotb tests at register-transfer and gate level (all passing) and taken through an open standard-cell flow, then submitted for tapeout via the Tiny Tapeout shared-silicon programme. Mapped to the open cell library, each block occupies a post-synthesis cell area of 9.3 to 10.6 thousand square micrometres, places at 61 to 70 per cent tile utilisation, meets the 50 MHz constraint with positive setup and hold margin after clock-tree synthesis, and draws an estimated 0.64 to 0.70 mW under a default switching-activity assumption. The contribution is a coherent, openly released set of building blocks unified by one register interface and one verification flow. All results are from simulation and the implementation flow; no fabricated silicon is reported.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 2 minor

Summary. The manuscript describes the design of four interface-compatible digital IP blocks in SkyWater 130 nm CMOS for neuromorphic edge systems: a PVT sensor incorporating a jitter-based TRNG and health monitor, a stochastic LIF neuron with configurable LFSR and activation table, an STDP controller supporting programmable curves and multiple modes, and a memristive crossbar programmer with forming/set/reset/read and sweep capabilities. All blocks share a common SPI register file (with parallel readout on the sensor), were verified via 99 passing cocotb tests at RTL and gate level, meet a 50 MHz target with positive timing margins after CTS, occupy 9.3–10.6 kµm² post-synthesis at 61–70% utilization, and were submitted for tapeout via Tiny Tapeout. Power is estimated at 0.64–0.70 mW under default switching activity. The stated contribution is a coherent, openly released set of blocks unified by one register interface and verification flow; all results are from simulation and the implementation flow with no fabricated silicon reported.

Significance. If the post-synthesis behavior holds, the work supplies openly released, interface-unified digital building blocks that integrate sensing, stochastic inference, on-chip learning, and crossbar control—elements useful for constructing compact neuromorphic systems. The comprehensive cocotb verification suite, open standard-cell flow, and tapeout submission provide concrete reproducibility assets that strengthen the engineering contribution.

minor comments (2)
  1. [Abstract] Abstract and §4 (results): the power figures rely on a default switching-activity assumption; adding a short sentence on the range under varied activity factors would clarify the estimate's robustness without altering the central claims.
  2. The manuscript would benefit from a consolidated table (perhaps in §4) listing area, utilization, timing slack, and estimated power for all four blocks side-by-side to facilitate direct comparison.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the constructive summary and the recommendation of minor revision. The report accurately captures the scope of the work as four interface-compatible digital IP blocks verified entirely through simulation and the open implementation flow, with submission to Tiny Tapeout but no post-fabrication silicon measurements yet available. We address the report below.

Circularity Check

0 steps flagged

No significant circularity identified

full rationale

The paper is an engineering design description of four digital IP blocks (PVT sensor/TRNG, stochastic LIF, STDP controller, crossbar programmer) sharing an SPI register file. All claims rest on explicit RTL/gate-level simulation, 99 passing cocotb tests, post-synthesis area/timing numbers from the SkyWater 130 nm open flow, and the statement that no fabricated silicon results are reported. There are no equations, fitted parameters, predictions, or derivation steps that reduce to inputs by construction, and no load-bearing self-citations. The central contribution (existence and compatibility of the blocks under the stated verification flow) is therefore self-contained and externally falsifiable via the open release.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a digital design paper; no free parameters, mathematical axioms, or invented physical entities are introduced. The work relies on standard CMOS design assumptions and the SkyWater 130 nm PDK.

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Reference graph

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