Low Complexity Neural Network Digital Predistortion of Wideband Power Amplifiers through Feature Selection

Ali H Alsarraf; Cel Thys; Dominique Schreurs; Rodney Martinez Alonso; Sofie Pollin

REVIEW 3 major objections 5 minor 18 references

Low Complexity Neural Network Digital Predistortion of Wideband Power Amplifiers through Feature Selection

T0 review · 3 major / 5 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read Offline feature selection lets compact neural networks linearize FR3 power amplifiers at 25–32% lower computational cost.

desk verdict Sensible feature-selection DPD with good measured linearization, but the central FLOP-savings claim is unverifiable because the cost of generating the selected features—the very thing that distinguishes it from the baseline—is missing from the complexity model. read the letter →

arxiv 2607.15441 v1 pith:4SZPXRMT submitted 2026-07-16 eess.SP

Cel Thys , Rodney Martinez Alonso , Ali H Alsarraf , Dominique Schreurs , Sofie Pollin This is my paper · ORCID

classification eess.SP

keywords digitalpredistortionneuralnetworkDPDfeatureselectionLASSOMRMRFR3poweramplifierVolterrafeaturesNMSE-complexitytradeoff

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that neural-network digital predistortion (DPD) can be made much cheaper without losing accuracy, if the expensive part — finding which inputs matter — is moved offline. It proposes a two-stage pipeline: build a huge library of Volterra-inspired real-valued input features, prune and rank them with LASSO and MRMR, and feed only the top ~100–200 features into a small residual phase-normalized network. On measured 15 GHz FR3 power amplifiers with 100 MHz signals, this Feature Selection NN reaches −37 dB NMSE at 595 FLOPs and −34 dB NMSE at 234 FLOPs, corresponding to roughly 25% and 32% reductions versus a phase-normalized NN baseline at comparable accuracy. Measured EVM and ACLR on one device confirm the trend. If correct, the approach narrows the long-standing complexity gap between neural-network DPD and polynomial DPD, removing a barrier to real-time deployment.

What carries the argument

The machinery is an offline feature-engineering pipeline followed by a small network. LASSO (ℓ1-regularized least squares) prunes a 321,200-column library of real-valued Volterra-inspired features to roughly 2,000 survivors, and MRMR greedily ranks those survivors by mutual information with the target minus redundancy with already-chosen features, yielding a top-k input set with k around 100–200. The online stage is a residual phase-normalized neural network whose per-sample cost is counted as feature generation plus phase normalization plus fully connected multiply-adds plus tanh activations; the offline LASSO/MRMR search is excluded because it does not run under real-time constraints.

What would settle it

Implement the selected top-k feature set (terms of the forms |x(n−m)|^p, xI(n−l)xQ(n−m), xI(n−l)|x(n−m)|^p, and their Q counterparts) in a cycle-accurate DSP/RTL model that counts every real multiply and add per sample, then recompute the NMSE-vs-FLOP Pareto curves. If the added feature-generation FLOPs exceed the roughly 200-FLOP gap between the proposed model and PNN at matched NMSE, the central complexity claim collapses.

Watch

Extended reading notes

Core claim

The central discovery is that the input representation, not the network size, is what makes NN DPD expensive. A residual phase-normalized network with only 100–200 pre-selected features — I/Q delay taps, odd-order envelope magnitudes, and I/Q cross-products of the kind used in GMP models — matches or beats the linearization accuracy of a phase-normalized NN while using roughly 25% fewer FLOPs on a 15 GHz GaAs PA (595 vs 797 FLOPs at −37 dB NMSE) and 32% fewer on a high-gain PA (234 FLOPs at −34 dB NMSE). The feature selection itself runs once offline on 15,000 samples from 321,200 candidates; only generation of the selected top-k features and NN inference count toward runtime complexity. Mea

Load-bearing premise

The FLOP reduction hinges on a complexity model that counts the selected features' generation and the NN inference but excludes the offline selection cost; if generating the top-k Volterra-like features (envelope powers, I/Q cross-products) in real time costs more than Table I assigns, the claimed 25–32% saving shrinks.

Editorial extensions

If this is right

Neural DPD can operate at a few hundred FLOPs per sample while matching phase-normalized NN accuracy, bringing it into the same complexity regime as MP/GMP polynomial models.
The winning features are standard Volterra-like terms, so no new nonlinear basis is needed; the gain comes from selecting a compact subset instead of using all candidate terms.
The NMSE-vs-FLOPs Pareto front places the Feature Selection NN below and to the left of the PNN baseline in the low-complexity region on both measured devices.
Measured EVM and ACLR on the first DUT confirm the simulated advantage at roughly 400 FLOPs, with the proposed model reaching 1.38% EVM versus 1.88% for the PNN.
The released FR3 PA datasets let other groups reproduce the comparison and benchmark future DPD algorithms against the same devices.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A natural next step, left implicit, is to inspect which features MRMR selects across different PAs; a recurring small set could be hard-coded, removing the need for per-device offline selection.
The same offline-selection idea could be applied adaptively: periodically re-running LASSO/MRMR on new captures would keep the feature set compact as the PA ages or its operating point drifts, without raising per-sample cost.
A hardware-level test — synthesis or cycle-accurate RTL for the selected features and network — would show whether the FLOP savings survive real implementation overheads such as memory access and activation-table lookups.
Because the basis includes envelope and I/Q cross-terms, the approach is likely to extend to wider bandwidths (e.g., 200–400 MHz) where memory effects are stronger, though the optimal k may need to grow.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: this is a useful engineering paper with a plausible complexity-saving pipeline, but the headline 25–30% FLOP reduction is not checkable from the manuscript. The missing piece is the feature-generation cost that separates the proposed method from the baseline PNN.

What is actually new: using LASSO plus MRMR offline to select a compact set of Volterra-like features as the input to a residual phase-normalized NN, instead of feeding raw delayed I/Q samples. That combination has been used for polynomial DPD but not, as far as I can tell, for NN-DPD input design. The authors also release measured FR3 PA datasets, which is real and welcome. The measured EVM/ACLR results on two 15 GHz devices support the linearization claim, and the reported Pareto curves show the proposed model reaching similar NMSE at lower listed FLOPs than PNN.

The soft spot is the central one. Section III explicitly says runtime complexity counts top-k feature generation plus NN inference, but Table I only includes phase normalization, fully connected layers, and tanh. There is no expression for computing envelope terms, I/Q cross-products, or products with envelope terms—the actual selected features. With k in the 100–200 range, even a few FLOPs per feature adds hundreds of FLOPs per sample, comparable to the claimed 595-FLOP budget. The PNN baseline takes raw delayed I/Q, which is nearly free, so the comparison may be systematically under-counting the proposed method. I don't think the saving necessarily disappears, but the paper as written gives no way to check. That is not a minor omission; it is the load-bearing claim.

Other concerns are minor: single-point measurements without error bars, no code or exact feature/network configuration beyond the dataset, and only two DUTs. The citation pattern looks fine. The paper is honest about what is offline and what is real-time, and the dataset is a genuine contribution.

Who this is for: people working on low-complexity NN DPD for FR3/6G will want the datasets and the measured linearization results. A serious referee should push for a complete FLOP derivation—either an honest accounting of feature generation or a hardware/fixed-point implementation cost—before the complexity claim can be accepted.

Recommendation: send it to peer review, but make the FLOP accounting fix a condition. If the 25–30% saving survives that, this is a solid, practical result. If not, the linearization results still stand, but the paper's main claim needs to be rewritten.

Referee Report

3 major / 5 minor

Summary. The paper proposes a Feature Selection Neural Network (NN) architecture for digital predistortion (DPD) of wideband FR3 power amplifiers. An offline pipeline uses LASSO to prune a large Volterra-inspired feature library and MRMR to rank and select a compact set of k real-valued features; these features are then fed into a residual phase-normalized NN. The authors report measured NMSE, EVM, and ACLR results on two 15 GHz devices with 100 MHz signals, and claim up to 30% FLOP reduction relative to a PNN baseline at comparable linearization performance. The measured FR3 PA datasets are publicly released.

Significance. If the complexity accounting is correct, the paper makes a practically relevant contribution: it addresses the gap between NN-DPD accuracy and real-time implementation cost, and the use of measured FR3 data with public datasets is a genuine strength. The offline feature-selection idea is sensible, and the measured EVM/ACLR results (Table II) support the linearization capability of the proposed model. However, the central quantitative claim—a 25–32% complexity reduction—depends on a FLOP model that is currently incomplete. Because the paper's headline contribution is specifically a complexity reduction, this accounting issue is load-bearing and must be resolved before the claim can be accepted.

major comments (3)

[II-C/Table I; §III] The text states that "only the top-k feature generation and NN model inference are counted" in the runtime complexity, but Table I has no term for input feature generation. The proposed NN input consists of features of the forms (8)–(10), which require computing envelope magnitudes |x(n−m)|, odd powers, and real multiplications between I/Q and envelope terms. For k≈100–200, even a low estimate of 2–3 FLOPs per selected feature adds 200–600 FLOPs per sample—comparable to the 595-FLOP point used for the 25% saving in §IV-A and to the 407-FLOP point in Table II. The PNN baseline consumes delayed raw I/Q samples, whose generation cost is essentially a memory read. Without deriving and adding C_feature_gen, the claimed 25–32% reduction may shrink or vanish. This is load-bearing because the headline claim is a complexity reduction.
[III-D; II-C] It is unclear how phase normalization is applied to the proposed feature set. Table I says phase normalization is applied to "all input features" and to the NN output, but §III-D says it is kept "for I and Q inputs." For envelope terms such as |x(n−m)|^p and products like x_I(n−l)|x(n−m)|^p, phase normalization is not a well-defined complex multiplication. The formula C_PN(I)=6(I+1) therefore may over- or under-count the operations for the proposed model. This ambiguity affects the FLOP comparison and must be clarified, with a precise definition of the phase-normalization operation for each feature type.
[IV-A; Figs. 5 and 7] The headline Pareto points (e.g., 595 vs. 797 FLOPs for the first DUT, and 234 FLOPs for the second DUT) are reported without the corresponding architecture details: the value of k, the hidden-layer sizes, the number of layers, and the composition of the selected feature set. Since the central claim is a quantitative complexity comparison, these details are necessary for reproducibility. Please include a table of the exact architectures and feature indices for the reported Pareto points, or otherwise make the selected features publicly available.

minor comments (5)

[III-A] The total number of candidate features is stated as F=321200 for M=200 and P=7, but no formula for F is provided. Give the general expression to make the feature-basis construction reproducible.
[III-C] The MRMR step uses mutual information between continuous features and the target, but no estimator or discretization scheme is specified. This is important for reproducibility of the selected feature ranking.
[Table II] The "No DPD" row reports EVM and ACLR but not NMSE; consider aligning the columns or explaining why NMSE is not applicable.
[Abstract / §IV-A] The abstract states "up to 30% reduction", while §IV-A reports 25% for DUT1 and 32% for DUT2. Clarify the distinction between the two datasets in the abstract or conclusion.
[II-C] The 10-FLOP tanh cost is attributed to a single technical report [17]. A brief justification of why this is representative for low-complexity hardware implementations would be helpful.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: empirical validation against measured PA data with an external benchmark; FLOP accounting gap is a correctness issue, not circular.

full rationale

The paper's central claims are empirical: the Feature Selection NN is trained on measured FR3 PA data, features are selected offline by LASSO/MRMR, and NMSE/EVM/ACLR are evaluated on held-out validation and hardware measurements. None of these quantities is defined in terms of the model's own output; the released dataset [14] is an externally measurable benchmark, so the self-citation is not load-bearing. The only notable issue is an accounting inconsistency: Section III states that 'only the top-k feature generation and NN model inference are counted' in runtime complexity, but Table I provides no expression for the cost of generating the selected Volterra-like features (Eqs. (7)-(10)). This could undermine the claimed 25-32% FLOP savings, but it is a completeness/fairness concern, not a circular reduction: no equation here is equivalent to its input by construction. Thus no circular step is identified.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the given feature basis, the indirect-learning assumption, the heuristic feature selection, and the self-defined FLOPs model. No new physical entities are introduced.

free parameters (5)

k (number of selected NN input features) = 100-200 (optimal range)
Directly controls complexity-performance tradeoff; tuned via Bayesian optimization on validation NMSE (Section III-C, IV-A).
Neural network hidden-layer sizes/depth = e.g., model with 98 coefficients at 407 FLOPs; sizes not enumerated
Bayesian-optimized hyperparameters; the runtime complexity depends on them (Section II-C).
LASSO regularization strength λ = chosen via exhaustive search to yield ~2000 surviving features
Set by hand to a target sparsity level, not chosen by a principled criterion (Section III-B).
Candidate feature memory depth M and nonlinear order P = M=200, P=7, F=321200
Arbitrary choices defining the search space; not fitted to performance (Section III-A).
Target number of LASSO-surviving features = ~2000
Hand-set design target preceding MRMR (Section III-B).

assumptions (5)

domain assumption PA behavior is sufficiently invertible; the post-distorter identified by indirect learning can serve as a predistorter.
Section II, paragraph 2: 'Assuming that the PA behavior is sufficiently invertible within the operating region...'
domain assumption The Volterra-like feature basis (7)-(10) captures the relevant PA nonlinearity for NN input.
Section III-A constructs the candidate feature space from truncated Volterra terms; the paper does not prove completeness.
domain assumption Greedy MRMR (mutual-information-based) ranking yields a near-optimal feature subset for NN training.
Section III-C uses the off-the-shelf MRMR heuristic without optimality guarantees.
ad hoc to paper Phase normalization, as used in PNN, remains applicable when the NN input contains envelope and cross-term features.
Section III-D states the phase-normalization operation is kept for I/Q inputs but does not specify its action on the other selected features; this affects both architecture and FLOPs.
domain assumption The FLOP-counting model is implementation-agnostic and counts all runtime operations fairly across models.
Section II-C claims implementation-agnostic comparison but leaves NN feature-generation costs unspecified in Table I.

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Cite this review

Pith. "Pith review of Low Complexity Neural Network Digital Predistortion of Wideband Power Amplifiers through Feature Selection." pith.science (2026). https://pith.science/paper/4SZPXRMT

@misc{pith2026260715441,
  author       = {Pith},
  title        = {Pith review of: Low Complexity Neural Network Digital Predistortion of Wideband Power Amplifiers through Feature Selection},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4SZPXRMT}},
  note         = {Machine review of arXiv:2607.15441}
}

read the original abstract

Due to the continuous increase in communication bandwidth and the use of highly efficient yet nonlinear power amplifiers, Digital Predistortion (DPD) algorithms are becoming increasingly complex. In particular, neural network (NN) based DPD approaches using Phase-Normalized NN architectures often incur substantially higher computational costs than widely deployed polynomial-based methods, such as the Memory Polynomial (MP) and Generalized Memory Polynomial (GMP) models. To bridge this gap between research performance and practical implementation, we propose a low-complexity Feature Selection NN DPD architecture. The proposed method employs an offline feature-engineering pipeline based on the Least Absolute Shrinkage and Selection Operator (LASSO) and the Minimum Redundancy Maximum Relevance (MRMR) algorithm to construct a compact and informative input representation. Using measured wideband FR3 power amplifier datasets that are publicly released with this work, we demonstrate up to 30% reduction in computational complexity while maintaining comparable linearization performance.

Figures

Figures reproduced from arXiv: 2607.15441 by the authors.

**Figure 2.** Proposed feature selection approach to low complexi [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Measured AM/AM and AM/PM response of the 1st DUT. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (5 more)

**Figure 6.** Figure 6: Measured AM/AM and AM/PM response of the 2nd DUT. [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 7.** Figure 7: Validation NMSE as a function of DPD computational co [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]

**Figure 5.** Figure 5: Validation NMSE as a function of DPD computational co [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 8.** Figure 8: Measured output spectrum after applying NN DPD algor [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

**Figure 9.** Figure 9: Measured EVM of different DPD algorithms. [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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6G Wireless Communicati ons in 7–24 GHz Band: Opportunities, Techniques, and Challenges,

Z. Cui, P . Zhang, and S. Pollin, “6G Wireless Communicati ons in 7–24 GHz Band: Opportunities, Techniques, and Challenges, ” in 2025 IEEE International Symposium on Dynamic Spectrum Access Ne tworks (DySPAN), May 2025, pp. 1–8

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J. A. Becerra, K. S. Chuang, and P . L. Gilabert, “Digital P redistortion Linearization Demystiﬁed: Insights Y ou Always Wanted to Kn ow but Were Too Linear to Ask,” IEEE Microwave Magazine , pp. 2–21, 2026

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D. Morgan, Z. Ma, J. Kim, M. Zierdt, and J. Pastalan, “A Gen eralized Memory Polynomial Model for Digital Predistortion of RF Pow er Ampliﬁers,” IEEE Transactions on Signal Processing , vol. 54, no. 10, pp. 3852–3860, Oct. 2006

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T. Liu, S. Boumaiza, and F. Ghannouchi, “Dynamic behavio ral modeling of 3G power ampliﬁers using real-valued time-delay neural n etworks,” IEEE Transactions on Microwave Theory and Techniques , vol. 52, no. 3, pp. 1025–1033, Mar. 2004

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Dee p Neural Network-Based Digital Predistorter for Doherty Power Ampl iﬁers,

R. Hongyo, Y . Egashira, T. M. Hone, and K. Y amaguchi, “Dee p Neural Network-Based Digital Predistorter for Doherty Power Ampl iﬁers,” IEEE Microwave and Wireless Components Letters , vol. 29, no. 2, pp. 146–148, Feb. 2019

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M. T. Khan, Y . Ding, and G. Goussetis, “Next-Gen Digital P redistortion From Hardware Acceleration of Neural Networks: Trends, Cha llenges, and Future,” IEEE Transactions on Neural Networks and Learning Systems, pp. 1–21, 2026

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Res idual Neural Networks for Digital Predistortion,

Y . Wu, U. Gustavsson, A. G. i. Amat, and H. Wymeersch, “Res idual Neural Networks for Digital Predistortion,” in GLOBECOM 2020 - 2020 IEEE Global Communications Conference , Dec. 2020, pp. 01–06

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A. Fischer-B¨ uhner, L. Anttila, M. D. Gomony, and M. V alkama, “Phase- Normalized Neural Network for Linearization of RF Power Amp liﬁers,” IEEE Microwave and Wireless Technology Letters , 2023

2023