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Just-in-Time Packet State Prefetching

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arxiv 2407.04344 v1 pith:4XUEXHJL submitted 2024-07-05 cs.NI

Hamid Ghasemirahni , Alireza Farshin , Dejan Kostic , Marco Chiesa This is my paper · ORCID
classification cs.NI
keywords packethintsinformationpacketscachejust-in-timememoriesprefetching
verification ladder T0 review T1 audit T2 compute T3 formal
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Could information about future incoming packets be used to build more efficient CPU-based packet processors? Can such information be obtained accurately? This paper studies novel packet processing architectures that receive external hints about which packets are soon to arrive, thus enabling prefetching into fast cache memories of the state needed to process them, just-in-time for the packets' arrival. We explore possible approaches to (i) obtain such hints either from network devices or the end hosts in the communication and (ii) use these hints to better utilize cache memories. We show that such information (if accurate) can improve packet processing throughput by at least 50%.

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    cs.SE 2025-01 conditional novelty 6.0 of 10

    Iridescent uses JIT compilation, developer annotations, and metric-guided exploration to specialize low-level systems code at runtime.

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