MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem

Can Firtina; Geraldo F. Oliveira; Haiyu Mao; Klea Zambaku; Konstantina Koliogeorgi; Melina Soysal; Mohammad Sadrosadati; Nika Mansouri Ghiasi; Onur Mutlu; Rakesh Nadig

REVIEW 4 major objections 5 minor 241 references

MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem

T0 review · 4 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read MARS claims 93x faster nanopore read mapping by moving analysis into the SSD.

desk verdict A serious systems paper that makes a genuine case for in-storage RSGA; the speedups are simulated, and the human-genome real-time margin is thin enough that the data-placement assumption needs scrutiny. read the letter →

arxiv 2506.10931 v2 pith:55TTIX2O submitted 2025-06-12 cs.AR q-bio.GN

Melina Soysal , Konstantina Koliogeorgi , Can Firtina , Nika Mansouri Ghiasi , Rakesh Nadig , Haiyu Mao , Geraldo F. Oliveira , Yu Liang

show 3 more authors

Klea Zambaku Mohammad Sadrosadati Onur Mutlu

This is my paper · ORCID

classification cs.ARq-bio.GN

keywords in-storageprocessingrawsignalgenomeanalysisnanoporesequencingprocessing-in-memoryreadmappingSSDDRAMaccelerationbasecalling

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that the dominant bottleneck in real-time nanopore genome analysis is no longer computation but the movement of raw signal data out of storage, and that the remedy is to execute the raw-signal read-mapping pipeline inside the SSD itself. To that end it proposes MARS, which it claims is the first in-storage processing system for raw-signal genome analysis, combining Processing-Using-DRAM (hash lookup inside the SSD's internal DRAM) with Processing-Near-DRAM (arithmetic units near DRAM subarrays and sorter/merger units in the SSD controller). A sympathetic reader would care because, if the claims hold, real-time mapping of large genomes would require neither basecalling nor shipping gigabytes of signals to host memory, with large energy savings. The paper reports 93x speedup over a GPU-based basecalling pipeline, 40x over a PIM-based basecalling pipeline, and 28x over RawHash2, with energy reductions of 427x, 72x, and 180x respectively, while keeping mapping accuracy on par with basecalling-based pipelines.

What carries the argument

The load-bearing mechanism is the in-SSD pipeline itself, organized around four compute elements: an Arithmetic Unit per pair of DRAM subarrays that performs add/compare/multiply operations for event detection and hash-value generation (Processing-Near-DRAM), a Querying Unit per subarray that uses DRAM row activation, custom match logic, and gated sense amplifiers to look up hash values in parallel (Processing-Using-DRAM), and a Sorter/Merger pair per flash controller that implements bitonic sorting and one-pass merging inside the SSD controller. These are tied together by a MARS Control Unit, a finite-state machine that sequences the steps, and a custom log-structured logical-to-physical mapping that lets data be read sequentially across flash channels, so the raw signals and reference index are processed as a streaming flow that never leaves the device.

What would settle it

Run MARS on a live stream of raw nanopore signals as the sequencer produces them, including the time to flush FTL metadata and arrange the data across channels, and compare end-to-end latency to RawHash2 reading from preloaded host DRAM; if the ingestion pass erases the 28x gap, the I/O-elimination claim is conditional on pre-arranged data placement.

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Extended reading notes

Core claim

On the paper's own terms, the discovery is that hardware acceleration of raw-signal genome analysis only exposes a second bottleneck: once seeding and chaining are made fast, storage I/O accounts for up to 78% of end-to-end time, so any scalable RSGA system must be storage-centric. MARS is the proposed proof of concept: it runs the whole RSGA workflow inside a modern SSD, with event detection and quantization on near-DRAM arithmetic units, hash-table seeding by processing-using-DRAM row activation with gated sense amplifiers, and chaining via bitonic sorter/merger units in the SSD controller, all orchestrated by a finite-state-machine control unit with a log-structured address mapping that turns the genome index and raw signals into a sequential in-device stream. To fit the pipeline into the device, MARS adds two filters (frequency filtering and seed-and-vote, the latter applied to raw signals for the first time) and early quantization with 16-bit fixed-point arithmetic, which the paper shows costs little accuracy. The paper claims MARS matches or exceeds the accuracy of the RawHash2 software baseline while delivering the speedups and energy reductions stated in the abstract.

Load-bearing premise

The evaluation assumes input data is already placed sequentially and evenly across the SSD's flash channels, so the cost of ingesting and reorganizing raw signals as they stream from a real sequencer is not included.

Editorial extensions

If this is right

MARS reports throughput above the full MinION sequencer rate for all five datasets, so real-time nanopore read mapping becomes plausible without a server-grade host.
The basecalling step can be bypassed for read-mapping workloads, since filtering and quantization of raw signals alone give mapping accuracy comparable to basecalling-based pipelines.
The combination of Processing-Using-DRAM and Processing-Near-DRAM inside one SSD broadens the design space for in-storage acceleration of other data-intensive applications.
If the I/O-dominance analysis is right, future RSGA accelerators that ignore storage placement will deliver shrinking end-to-end returns as sequencing throughput grows.
The paper's comparison against an external-PIM variant (MS-EXT) implies that keeping computation in the device, not just accelerating it, is what yields the largest gains.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper does not model the cost of ingesting and reorganizing raw signals as they stream from the sequencer; if a data-placement pass is required before MARS can start, its end-to-end advantage over in-memory baselines could shrink.
The same event-detection/quantization/hash-query/sort structure appears in other nanopore signal analyses such as methylation or RNA-modification detection, so the storage-centric recipe may transfer to those tasks if their accuracy tolerates the same filtering.
A fair test of the central claim would compare MARS against RawHash2 with the raw signals already resident in host DRAM, isolating the I/O-elimination benefit from the filtering and fixed-point algorithmic gains.
The speedup numbers assume a performance-optimized SSD with 4 GB internal DRAM; the paper's own sensitivity analysis shows MARS scales with DRAM size, which suggests the design's benefits depend on continued growth of SSD-internal DRAM capacity.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Here's my read on MARS. It is a genuine systems contribution: the first in-storage processing design for raw-signal genome analysis, and the first to combine Processing-Using-DRAM and Processing-Near-DRAM inside an SSD. The motivational study (Section 3) makes the I/O bottleneck point concretely by showing that as seeding and chaining are accelerated, storage I/O dominates. That is a real observation, and it is the right justification for moving compute into the SSD. The architecture is carefully partitioned across the SSD controller, internal DRAM subarrays, and DRAM periphery, and the paper is unusually thorough in describing the querying, sorting, and arithmetic units. The area and energy numbers are plausible given the component-level synthesis and CACTI/MQSim simulations.

The soft spots are mostly about evidence, not about the idea. All results come from simulation: MQSim, CACTI7, and Verilog synthesis, combined with hand-computed data movement. There is no end-to-end validation against real hardware, no released artifact. That is typical for a complex architecture paper, but it means the 93x/40x/28x speedups should be read as modeled, not measured. The more specific concern is the data placement assumption in Section 7: data is assumed to be already sequentially and evenly striped across channels. MARS's custom L2P mapping depends on that layout. In a real deployment, raw signals arrive over time from the sequencer, and the cost of ingesting them into that layout is not modeled. The stress-test note gets this right: for the human genome (D5), MARS's throughput is 286,728 bp/s versus the MinION's 230,400 bp/s, a 1.24x margin. Any non-trivial ingestion or reorganization overhead could erase the real-time claim. For smaller genomes the margin is large, so the architecture still looks sound for viral and bacterial workloads.

The threshold tuning on 0.5-2% subsets of each dataset is a mild overfitting risk, since the same subsets are inside the evaluated data. It does not invalidate the accuracy comparison, but it should be disclosed more carefully. The leftover editing notes in Figures 1 and 9 ("Replace in Overleaf", "Improve text that fits to the figure") are sloppy and should be fixed before publication. I don't see a mismatch between the abstract's 28x and the Figure 11 geomean; the numbers line up.

Bottom line: this is a strong architecture paper with a novel integration and an honest, mostly transparent evaluation. The data-placement assumption is the one load-bearing assumption that needs a sensitivity analysis or an argument for why streaming writes naturally produce that layout. It deserves serious peer review, not a desk reject, with requests for artifact release and a sensitivity study on ingestion. I would bring it to the reading group; it will generate a good discussion about what it takes to make real-time genomics work inside storage.

Referee Report

4 major / 5 minor

Summary. The paper identifies I/O data movement as the dominant bottleneck for raw-signal genome analysis (RSGA) once seeding and chaining are computationally accelerated, and proposes MARS, an in-storage processing system that places the RSGA read-mapping pipeline inside an SSD. MARS combines processing-using-DRAM (pLUTo-style hash-table query units inside the SSD-internal DRAM), processing-near-DRAM (arithmetic units near DRAM subarrays), and processing-near-DRAM logic in the SSD controller (sorter/merger units), together with software modifications: frequency filtering, seed-and-vote filtering, early quantization, and fixed-point arithmetic. The evaluation uses MQSim, CACTI7, Verilog synthesis, and data-movement latency calculations on five real datasets, and the paper claims 93x/40x speedups over a GPU-based basecalling pipeline (BC) and GenPIP, 28x over RawHash2, with energy reductions of 427x/72x/180x on average. Accuracy is reported as on par with or better than RawHash2 and close to a basecalling ground truth.

Significance. If the claimed results are reliable, MARS is a significant contribution: it is the first ISP system for RSGA, it is the first architecture to combine processing-using-DRAM and processing-near-DRAM inside a storage device, and its motivational analysis of the I/O bottleneck for accelerated RSGA is timely and well framed. The software modifications (early quantization and the combination of two filtering techniques) also appear to improve accuracy over RawHash2 in the reported settings. However, the evaluation is entirely simulation-based with no released code or data, and several load-bearing assumptions and an internal inconsistency in the accuracy reporting need to be resolved before the headline speedup and energy claims can be taken at face value.

major comments (4)

[Section 7 (Datasets) and Section 6.5] The evaluation assumes that input data is 'already correctly placed, i.e. sequentially and evenly distributed across all SSD channels, for all evaluated systems' (Section 7). This assumption is load-bearing because MARS's custom L2P mapping in Section 6.5 stores only a starting LPA, the database size, and a sequence of PBAs, which works only if the reference index and raw signals are contiguous and striped across flash channels. In a real deployment, raw signals arrive as a stream from the sequencer and must be ingested or reorganized into this layout, and that cost is not modeled. Table 4 shows that the human-genome throughput of 286,728 bp/s is only 1.24x the full MinION rate of 230,400 bp/s, so even a modest ingestion or FTL-write overhead would erase the real-time margin for the largest dataset. Please add a quantitative ingestion/reorganization model, or explicitly scope the real-time claim to pre-placed data.
[Section 8.1 vs. Section 7] Section 8.1 states that 'All hardware systems implement MS-CPUFloat workflow and thus achieve the same accuracy,' yet Section 7 lists MARS as the in-storage design using fixed-point arithmetic, with MS-CPUFixed as the CPU fixed-point variant. Because the hardware MARS uses fixed-point arithmetic, its accuracy should follow the MS-CPUFixed row of Table 3, not the MS-CPUFloat row. This discrepancy matters for the accuracy-parity claim: the D5 F1 values are 0.7612 for MS-CPUFloat versus 0.7300 for MS-CPUFixed. Please clarify which arithmetic MARS actually implements and report the corresponding accuracy consistently.
[Section 7 (Evaluation Methodology) and Section 6.3] End-to-end performance is assembled by simulating each component individually and adding data-movement latencies, but the architecture description relies on overlap: Section 6.3 says that for partitioned indexes 'MARS overlaps computation with data loading, effectively hiding the data movement latency,' and Section 6.1.3 says compute units are activated whenever their inputs are available. The paper does not explain how the component-wise simulations account for this overlap or for contention among Arithmetic, Querying, Sorter, and Merger Units. In addition, the Querying Unit's sequential row-sweep cost in Section 6.3 is central to the reported seeding speedups, yet the simulation configuration in Table 1 provides no description of how row activations, matchline delays, or repeated sweeps over partitioned hash-table chunks are modeled. Please provide an end-to-end timing model that includes these effects or quantifies why they are negligible.
[Section 5.1 and Table 3] The filtering thresholds (thresh_freq, thresh_voting, voting_window) are tuned on a 0.5%-2% subset of each dataset, and Table 3 reports accuracy on the full versions of those same datasets. Because the thresholds directly determine how many seeds and anchors survive to chaining, they affect both the F1 scores in Table 3 and the speedups in Fig. 11; reporting in-sample results may therefore overstate accuracy and performance. Please add held-out evaluation or a sensitivity analysis showing that the reported conclusions are stable across reasonable threshold choices.

minor comments (5)

[Figure 9] The figure artwork contains explicit editing instructions that must be removed before publication: 'Improve text that fits to the figure', 'Show it is a sequence', 'Dotted lines call it step 1/2/3 etc', and 'Include that the current key is O'.
[Section 8.2] The text says 'all seven systems' but Section 7 lists nine evaluated systems: BC, RH2, MS-CPUFloat, MS-CPUFixed, MARS, MS-EXT, MS-SIMDRAM, GenPIP, and MS-SmartSSD.
[Figure 10] The label 'Contol Unit' should be corrected to 'Control Unit'.
[Section 6.3] The paper states that multiple copies of the hash table can be stored in DRAM, but it does not quantify how many copies fit in the 4 GB internal DRAM alongside raw signals, intermediate results, and FTL metadata; please provide this analysis.
[General] The manuscript does not state whether code or data will be released, which limits reproducibility of a fully simulated design; please add an availability statement.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: MARS's central speedup and energy claims are simulation/evaluation results, not derived from fitted inputs or self-citation chains.

full rationale

The paper's central claims are end-to-end performance and energy comparisons obtained by simulation (MQSim, CACTI7, Verilog synthesis) and by running software baselines; they are not the output of a parametric fit. The filtering thresholds in Section 5.1 are tuned offline on subsets of 0.5-2%, but the reported accuracy and runtime are measured on the full datasets, so the result is not forced by construction. The motivational claim that I/O becomes dominant under acceleration is an explicit latency-reduction experiment, not a definitional identity. MARS builds on prior author-group components (RawHash2, pLUTo, FULCRUM-style arithmetic units, and related ISP work), but these are cited as published building blocks or baselines; the speedup numbers are not derived by citing those works' results. The stated evaluation assumption that data is pre-placed sequentially across SSD channels (Section 7) is an unmodeled real-world ingestion cost that could affect the real-time margin, but it is an experimental assumption, not a circular derivation. I find no equation, fitted parameter, or self-citation chain that makes the claimed prediction equivalent to its inputs.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central performance claims rest on a chain of modeling choices: the pLUTo and FULCRUM-derived PIM units, the MQSim/CACTI simulation stack, the 4 GB internal DRAM capacity, and the assumption that input data is pre-placed sequentially across channels. The filtering thresholds are fitted to small subsets of the same test datasets. No new physical entity is introduced.

free parameters (4)

thresh_freq = 2000 (small genomes), 20000 (large genomes)
Frequency filter threshold; tuned offline on a subset of each dataset (Section 5.1). Affects how many seeds are discarded and therefore the measured workload and F1.
thresh_voting = 5 (small), 2 (large)
Seed-and-vote threshold; tuned with parameter space exploration on a subset of each dataset (Section 5.1).
voting_window = 256
Window size for seed-and-vote; selected in the same offline exploration (Section 5.1).
fixed-point bit width = 16
Chosen after an experimental analysis of 32, 16, and 8 bits (Section 5.2); a design decision affecting accuracy and resource use.

assumptions (5)

domain assumption The pLUTo-style Querying Unit performs DRAM row-sweep hash table lookups at the modeled latency without errors.
MARS adopts pLUTo [118] for lookup; Section 6.3 describes the four-step query but does not account for potential analog reliability or refresh issues in the SSD-internal DRAM.
domain assumption The FULCRUM-based Arithmetic Unit can execute the required signal-to-event, quantization, hashing, filtering, and chaining DP operations at 164 MHz.
Section 6.2 borrows FULCRUM's ALU design; the paper does not verify that the instruction buffer and column-selection latches can implement all operators at the modeled frequency.
domain assumption Input raw signal data and the reference index are already sequentially and evenly distributed across all channels of the SSD.
Section 7 states this assumption for all evaluated systems; MARS's I/O savings depend on it because the custom L2P mapping (Section 6.5) assumes log-structured sequential placement.
standard math MQSim and CACTI7 provide accurate models for the SSD and LPDDR4 DRAM behavior.
The evaluation (Section 7) uses these simulators; they are established tools, so this is a standard modeling assumption.
domain assumption 4 GB SSD-internal DRAM can hold the working set (hash table partitions of up to 2.6 GB for the human genome) and intermediate data simultaneously.
Section 6.3 partitions the 52 GB index into 2.6 GB regions; Section 8.5 varies DRAM size, but the base case assumes the partitioning causes no capacity-related stalls that are not modeled.

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Cite this review

Pith. "Pith review of MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem." pith.science (2026). https://pith.science/paper/55TTIX2O

@misc{pith2026250610931,
  author       = {Pith},
  title        = {Pith review of: MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/55TTIX2O}},
  note         = {Machine review of arXiv:2506.10931}
}

read the original abstract

Raw signal genome analysis (RSGA) has emerged as a promising approach to enable real-time genome analysis by directly analyzing raw electrical signals. However, rapid advancements in sequencing technologies make it increasingly difficult for software-based RSGA to match the throughput of raw signal generation. This paper demonstrates that while hardware acceleration techniques can significantly accelerate RSGA, the high volume of genomic data shifts the performance and energy bottleneck from computation to I/O data movement. As sequencing throughput increases, I/O overhead becomes the main contributor to both runtime and energy consumption. Therefore, there is a need to design a high-performance, energy-efficient system for RSGA that can both alleviate the data movement bottleneck and provide large acceleration capabilities. We propose MARS, a storage-centric system that leverages the heterogeneous resources within modern storage systems (e.g., storage-internal DRAM, storage controller, flash chips) alongside their large storage capacity to tackle both data movement and computational overheads of RSGA in an area-efficient and low-cost manner. MARS accelerates RSGA through a novel hardware/software co-design approach. First, MARS modifies the RSGA pipeline via two filtering mechanisms and a quantization scheme, reducing hardware demands and optimizing for in-storage execution. Second, MARS accelerates the RSGA steps directly within the storage by leveraging both Processing-Near-Memory and Processing-Using-Memory paradigms. Third, MARS orchestrates the execution of all steps to fully exploit in-storage parallelism and minimize data movement. Our evaluation shows that MARS outperforms basecalling-based software and hardware-accelerated state-of-the-art read mapping pipelines by 93x and 40x, on average across different datasets, while reducing their energy consumption by 427x and 72x.

Figures

Figures reproduced from arXiv: 2506.10931 by the authors.

**Figure 1.** Overview of a typical RSGA read mapping workflow based on a hash-table for indexing. A Indexing (offline): The reference genome is converted into events through reference-to-event conversion and quantization. These events are then stored in an efficient data structure, e.g., a hash table, to enable fast lookup of matching signal patterns. B Mapping (online): This stage maps raw signals to the reference genome usin… view at source ↗

**Figure 2.** Overview of the seed-and-vote filtering technique for a threshold value of 5. 2.2. SSD Architecture [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Organizational overview of a modern SSD. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

Figures from the paper (5 more)

**Figure 5.** Figure 5: RawHash2 runtime breakdown for real-world ge [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 7.** Figure 7: High-level overview of MARS architecture. [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]

**Figure 8.** Figure 8: Overview of the MARS Arithmetic Unit near a DRAM [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]

**Figure 10.** Figure 10: Simplified overview of our Sort-and-Merge workflow. As shown in [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]

**Figure 13.** Figure 13: Sensitivity to SSD-internal DRAM size. 9. Related Work To our knowledge, this is the first work to 1) enable in-storage acceleration of Raw Signal Genome Analysis and 2) combine the use of Processing-Near-Memory and Processing-UsingMemory inside the storage system. I…

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