Power-Integrity Modeling of VR Faults in High-Performance Applications

Inna Partin-Vaisband; Sriharini Krishnakumar

arxiv: 2605.24877 · v1 · pith:7DV5X6W2new · submitted 2026-05-24 · 📡 eess.SY · cs.SY

Power-Integrity Modeling of VR Faults in High-Performance Applications

Sriharini Krishnakumar , Inna Partin-Vaisband This is my paper

Pith reviewed 2026-06-29 23:59 UTC · model grok-4.3

classification 📡 eess.SY cs.SY

keywords vertical power deliveryfault detectionvoltage regulator faultspower integrityinductor current modelingSPICE simulationhigh-performance computingfault isolation

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The pith

Analytical inductor-current models from control signals enable sub-microsecond fault detection and dual-fuse isolation in vertical power delivery systems.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a real-time fault detection and isolation method for distributed vertical power delivery in high-performance computing to counter short- and open-circuit faults that arise from thermal and mechanical stresses in tightly integrated voltage regulators. These faults can propagate through shared networks and degrade system efficiency at rates up to 0.5 percent per microsecond. The approach derives analytical inductor-current models exclusively from signals already present in the converter control circuitry, eliminating any need for extra sensors. SPICE simulations of the resulting framework show sub-microsecond detection times, effective isolation via dual fuses, and uninterrupted operation with total efficiency loss kept below 2 percent.

Core claim

A real-time fault-detection and isolation methodology for vertical power delivery systems is developed based on analytical inductor-current models that rely solely on signals available within the converter control circuitry, thereby eliminating additional sensing overhead. The proposed framework is designed and simulated in SPICE environment, demonstrating sub-microsecond fault detection and effective dual-fuse isolation, maintaining uninterrupted power delivery with a system-wide efficiency degradation of less than 2%.

What carries the argument

analytical inductor-current models that rely solely on signals available within the converter control circuitry

If this is right

Fault isolation can occur without adding sensing components or overhead to the power delivery network.
Dual-fuse mechanisms allow the system to maintain continuous power delivery after a fault occurs.
System-wide efficiency remains within 2 percent of nominal even after fault events.
The method applies directly to stacked-substrate voltage regulator configurations in high-current-density computing platforms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the models hold in silicon, control-circuitry-only monitoring could become standard in future vertical power architectures, reducing component count.
The same signal-based modeling approach may generalize to detect other transient anomalies such as voltage droops or thermal hotspots.
Hardware validation would also clarify whether the sub-microsecond response time remains achievable when board parasitics and noise are present.

Load-bearing premise

The analytical inductor-current models derived solely from control circuitry signals are sufficiently accurate to enable reliable real-time fault detection and isolation in actual hardware, without post-simulation validation or additional sensing.

What would settle it

Side-by-side comparison of model-predicted inductor currents against measured currents on physical hardware during induced short-circuit and open-circuit faults under realistic thermal and mechanical stress.

Figures

Figures reproduced from arXiv: 2605.24877 by Inna Partin-Vaisband, Sriharini Krishnakumar.

**Figure 1.** Figure 1: Schematic of a DVPD system. enabling current sharing across multiple parallel conduction paths. This architecture reduces the electrical distance between the VRs and points of load (POLs), lowers parasitic resistance and loop inductance, and enables fast transient response while supporting high power-density operation. However, the increasing integration density and architectural complexity of DVPD systems… view at source ↗

**Figure 2.** Figure 2: Illustration of DVPD system comprising multiple parallel VRs connected to a shared PDN. The inset shows a representative buck converter with [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: Impact of SCF and OCF in power switches on system-wide efficiency [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗

**Figure 4.** Figure 4: Measured and estimated inductor current under transient conditions [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 5.** Figure 5: Illustration of the impact of different fault types on the inductor current and the corresponding fault-flag signal generated by the proposed detection [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗

**Figure 3.** Figure 3: Performance of the system designed with the proposed [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

read the original abstract

Distributed vertical power delivery has emerged as a promising approach to meet aggressive current-density, efficiency, and transient response requirements in high-performance computing systems. Tight integration of voltage regulators within stacked substrates, however, increases the vulnerability of the power delivery system to short-circuit and open-circuit faults arising from elevated thermal and mechanical stresses. Such faults can propagate through the shared power delivery network, leading to rapid degradation of system-wide efficiency at worst-case rates of up to 0.5% per microsecond. Advanced fault-tolerant power management strategies are therefore required to ensure efficient power delivery. A real-time fault-detection and isolation methodology are proposed in this paper for vertical power delivery systems. The methodology is developed based on an analytical inductor-current models that rely solely on signals available within the converter control circuitry, thereby eliminating additional sensing overhead. The proposed framework is designed and simulated in SPICE environment, demonstrating sub-microsecond fault detection and effective dual-fuse isolation, maintaining uninterrupted power delivery with a system-wide efficiency degradation of less than 2%.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This paper runs SPICE simulations of a sensor-free fault detection scheme for vertical power delivery but offers no hardware checks on the models.

read the letter

The core contribution is an analytical inductor-current model built only from signals already inside the converter control loop. The authors use it to trigger dual-fuse isolation in a stacked voltage-regulator setup and report sub-microsecond detection with less than 2 % system efficiency drop in simulation.

That modeling choice is the practical part: it avoids extra current sensors, which matters when regulators are tightly integrated. The SPICE results show the isolation works without interrupting power delivery, and the efficiency numbers are presented clearly.

The limitation is straightforward. All claims rest on simulation; there is no prototype, no injected noise, and no tolerance analysis for parasitics or component spread. The paper therefore cannot show whether the models remain accurate enough for real-time decisions once switching noise and layout effects appear. That gap is central, not minor.

Power-integrity engineers working on high-current-density HPC boards are the natural audience. They may pick up the control-signal modeling approach as a reference. Readers who need measured silicon results will find the work preliminary.

The manuscript is coherent on its own terms and addresses a real constraint in vertical power delivery, so it is worth sending to referees. They can decide whether the simulation evidence is sufficient for the claims or whether hardware validation is required before publication.

Referee Report

1 major / 0 minor

Summary. The paper proposes a real-time fault-detection and isolation methodology for vertical power delivery systems in high-performance computing. It relies on analytical inductor-current models derived solely from signals in the converter control circuitry (no extra sensors), with the framework implemented and tested exclusively via SPICE simulations that report sub-microsecond fault detection, effective dual-fuse isolation, and system-wide efficiency degradation below 2%.

Significance. If the analytical models prove transferable to hardware, the approach would address a practical need for low-overhead fault tolerance in tightly integrated voltage regulators, where faults can degrade efficiency at rates up to 0.5% per microsecond. The elimination of additional sensing hardware is a clear strength if validated.

major comments (1)

[Abstract / Simulation Results] Abstract and simulation-results section: the central claims of sub-microsecond detection and <2% efficiency degradation rest entirely on SPICE simulations of the analytical inductor-current models; no hardware prototype, noise-injection tests, component-tolerance analysis, or layout-parasitic study is reported, leaving the transferability of the models to physical VR hardware unverified and load-bearing for the real-time reliability assertion.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed review and constructive feedback. We address the major comment below, providing a point-by-point response while maintaining the simulation-based scope of the work.

read point-by-point responses

Referee: [Abstract / Simulation Results] Abstract and simulation-results section: the central claims of sub-microsecond detection and <2% efficiency degradation rest entirely on SPICE simulations of the analytical inductor-current models; no hardware prototype, noise-injection tests, component-tolerance analysis, or layout-parasitic study is reported, leaving the transferability of the models to physical VR hardware unverified and load-bearing for the real-time reliability assertion.

Authors: We agree that all reported results derive from SPICE simulations of the proposed analytical inductor-current models, with no hardware prototypes, noise-injection experiments, tolerance sweeps, or parasitic extractions included. The manuscript's core contribution is the derivation of these models from existing control-circuitry signals and their demonstration of sub-microsecond detection and dual-fuse isolation under ideal simulated conditions. We will revise the abstract, simulation-results section, and conclusions to explicitly qualify all performance claims as simulation-based, add a limitations paragraph discussing unmodeled effects (component variation, layout parasitics, and noise), and outline hardware validation as future work. These textual clarifications will be made without altering the modeling framework or simulation data. revision: partial

Circularity Check

0 steps flagged

No circularity: analytical models presented as independent of simulation outcomes

full rationale

The paper derives inductor-current models analytically from control-circuitry signals alone and then reports SPICE simulation results for detection latency and efficiency. No equations reduce to their own inputs by construction, no fitted parameters are relabeled as predictions, and no self-citation chain is invoked to justify uniqueness or an ansatz. The central claims rest on the stated analytical independence of the models from the reported simulation metrics, making the derivation self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the unverified accuracy of the analytical models for fault conditions. No free parameters or invented entities are mentioned in the abstract.

axioms (1)

domain assumption Analytical inductor-current models derived from control circuitry signals accurately represent short-circuit and open-circuit fault behavior in vertical power delivery systems.
This premise is required for the methodology to eliminate additional sensing overhead and enable real-time detection.

pith-pipeline@v0.9.1-grok · 5710 in / 1168 out tokens · 27011 ms · 2026-06-29T23:59:14.203197+00:00 · methodology

discussion (0)

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing
eess.SY 2026-06 unverdicted novelty 5.0

A design framework for distributed vertical power delivery in HPC systems achieves 84% end-to-end efficiency for 48V-to-1V conversion while using 54% of the area under the load.

Reference graph

Works this paper leans on

8 extracted references · cited by 1 Pith paper

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M. Ashourloo, V . R. Namburi, G. V . Piqu ´e, J. Pigott, H. J. Bergveld, A. El Sherif, and O. Trescases, “Fault detection in a hybrid dickson dc– dc converter for 48-v automotive applications,”IEEE Transactions on Power Electronics, vol. 36, no. 4, pp. 4254–4268, 2020

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G. K. Kumar and D. Elangovan, “Review on fault-diagnosis and fault- tolerance for dc–dc converters,”IET Power Electronics, vol. 13, no. 1, pp. 1–13, 2020

2020

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High-efficiency nonisolated converter with very high step-down conversion ratio,

O. Kirshenboim and M. M. Peretz, “High-efficiency nonisolated converter with very high step-down conversion ratio,”IEEE Transactions on Power Electronics, vol. 32, no. 5, pp. 3683–3690, 2017

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Model-based fault detection and identification for switching power converters,

J. Poon, P. Jain, I. C. Konstantakopoulos, C. Spanos, S. K. Panda, and S. R. Sanders, “Model-based fault detection and identification for switching power converters,”IEEE Transactions on Power Electronics, vol. 32, no. 2, pp. 1419–1430, 2016

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M. Ashourloo, V . R. Namburi, G. V . Piqu ´e, J. Pigott, H. J. Bergveld, A. El Sherif, and O. Trescases, “Fault detection in a hybrid dickson dc– dc converter for 48-v automotive applications,”IEEE Transactions on Power Electronics, vol. 36, no. 4, pp. 4254–4268, 2020

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