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Analyzing GPU Tensor Core Potential for Fast Reductions

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arxiv 1903.03640 v1 pith:7XL3CVXB submitted 2019-03-08 cs.DC

classification cs.DC
keywords tensoralgorithmanalyzingarchitecturecomputingcoresfastnumbers
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abstract

The Nvidia GPU architecture has introduced new computing elements such as the \textit{tensor cores}, which are special processing units dedicated to perform fast matrix-multiply-accumulate (MMA) operations and accelerate \textit{Deep Learning} applications. In this work we present the idea of using tensor cores for a different purpose such as the parallel arithmetic reduction problem, and propose a new GPU tensor-core based algorithm as well as analyze its potential performance benefits in comparison to a traditional GPU-based one. The proposed method, encodes the reduction of $n$ numbers as a set of $m\times m$ MMA tensor-core operations (for Nvidia's Volta architecture $m=16$) and takes advantage from the fact that each MMA operation takes just one GPU cycle. When analyzing the cost under a simplified GPU computing model, the result is that the new algorithm manages to reduce a problem of $n$ numbers in $T(n) = 5\log_{m^2}(n)$ steps with a speedup of $S = \frac{4}{5}\log_2(m^2)$.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. A Computational Model for Tensor Core Units

    cs.DS 2019-08 conditional novelty 6.0 of 10

    The paper introduces the (m,ℓ)-TCU computational model for tensor-core accelerators and derives asymptotic running-time bounds for a portfolio of algorithms under it.

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