Limits to the Energy Efficiency of CMOS Microprocessors

CMOS microprocessors have achieved massive energy efficiency gains but may reach limits soon. This paper presents an approach to estimating the limits on the maximum floating point operations per Joule (FLOP/J) for CMOS microprocessors. We analyze the three primary sources of energy dissipation: transistor switching, interconnect capacitances and leakage power. Using first-principles calculations of minimum energy costs based on Landauer's principle, prior estimates of relevant parameters, and empirical data on hardware, we derive the energy cost per FLOP for each component. Combining these yields a geometric mean estimate of 4.7e15 FP4/J for the maximum CMOS energy efficiency, roughly two hundred-fold more efficient than current microprocessors.