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arxiv: 1906.11915 · v3 · pith:BBDGQV4Onew · submitted 2019-06-27 · 💻 cs.AR

Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic

Soroush Ghodrati , Hardik Sharma , Sean Kinzer , Amir Yazdanbakhsh , Kambiz Samadi , Nam Sung Kim , Doug Burger , Hadi Esmaeilzadeh This is my paper

Pith reviewed 2026-05-25 13:42 UTC · model grok-4.3

classification 💻 cs.AR
keywords mixed-signal accelerationdeep neural networkscharge-domain computingbit-partitioned arithmeticswitched-capacitor circuitsanalog dot-product3D-stacked architecture
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The pith

Bit-partitioning dot-products into interleaved low-bitwidth groups lets mixed-signal circuits accumulate in charge domain and share A/D converters.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that a vector dot-product can be reformulated as groups of spatially parallel low-bitwidth operations interleaved across vector elements. This change turns the accelerator building blocks into wide yet low-bitwidth multiply-accumulate units that run in the analog domain and share a single A/D converter. Switched-capacitor circuitry performs the group multiplications in the charge domain and accumulates results over multiple cycles. The approach addresses limited encoding range and noise through low bitwidth while removing the need for per-operation A/D conversion.

Core claim

A vector dot-product can be bit-partitioned into groups of spatially parallel low-bitwidth operations interleaved across multiple elements of the vectors, so that groups of wide yet low-bitwidth multiply-accumulate units operate in the analog domain and share a single A/D converter, with switched-capacitor circuitry performing the group multiplications in the charge domain and accumulating the results of the group in its capacitors over multiple cycles.

What carries the argument

Interleaved bit-partitioned arithmetic realized through switched-capacitor charge-domain accumulation that shares one A/D converter across a group.

Load-bearing premise

Low-bitwidth bit-partitioned operations performed in the analog domain can handle encoding range limits and noise while the interleaved capacitive accumulation preserves the accuracy of the original DNN computation.

What would settle it

A direct accuracy comparison between a full DNN inference run on the proposed charge-domain interleaved bit-partitioned units versus an equivalent high-precision digital implementation, or power measurements showing whether A/D conversion energy per dot-product actually drops.

Figures

Figures reproduced from arXiv: 1906.11915 by Amir Yazdanbakhsh, Doug Burger, Hadi Esmaeilzadeh, Hardik Sharma, Kambiz Samadi, Nam Sung Kim, Sean Kinzer, Soroush Ghodrati.

Figure 1
Figure 1. Figure 1: Wide, interleaved, and bit-partitioned mathematical formulation. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Hierarchically clustered architecture of B [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: depicts the design of a single 3-bit sign-magnitude MACC. The xsx1x0 and wsw1w0 denote the bit-partitions operands. The result of each MACC operation is retained as electric charge in the accumulating capacitor (CACC). In addi￾tion to CACC, the MACC unit contains two capacitive Digital￾to-Analog Converters, one for inputs (C-DACX) and one for weights (C-DACW). The C-DACX and C-DACW convert the C-DACx C-DAC… view at source ↗
Figure 4
Figure 4. Figure 4: Charge-domain MACC; phase by phase. 2-bit magnitude of the input and weight to the analog domain as an electric charge proportional to |x| and |w| respectively. C-DACX and C-DACW are each composed of two capacitors ((CX, 2CX) and (CW, 2CW)) which operate in parallel and are combined to convert the operands to analog domain. Each of these capacitors are controlled by a pair of transmission gates which deter… view at source ↗
Figure 5
Figure 5. Figure 5: Mixed-Signal bit-partitioned MACC unit. With this choice, Qsw becomes Qsw =|x|×|w| CWvDD 3 . Clkφ(3) : In the last phase, ( [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: ResNet-50 and VGG-16 accuracy after fine-tuning. experiments show that, variations in voltage can be mitigated up to 20%. The extensive amount of vector dot-product operations in DNNs, allows for the minimum and maximum values of the distributions being sampled sufficient amount of times, leading to coverage of the corner cases. Atop all these considerations, we use differential signaling for ADCs which at… view at source ↗
Figure 7
Figure 7. Figure 7: BIHIWE compilation stack. 7 [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Speedup and energy improvement over TETRIS. GPU comparison. We also compare BIHIWE to two Nvidia GPUs (i.e., RTX 2080 TI and Titan Xp) based on Turing and Pascal architecture respectively, listed in [PITH_FULL_IMAGE:figures/full_fig_p009_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Energy breakdown of BIHIWE and TETRIS. normalized to TETRIS. Energy breakdown is reported across four major architectural components: (1) on-chip compute units, (2) on-chip memory (buffers and register file), (3) interconnect, and (4) 3D-stacked DRAM. DRAM accesses account for the highest portion of the energy in BIHIWE, since BIHIWE significantly reduces the on-chip compute energy. While BIHIWE has a sign… view at source ↗
Figure 10
Figure 10. Figure 10: Iso-area comparison with TETRIS. 9 [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Performance comparison to GPUs. weights. Therefore, PTB-RNN and PTB-LSTM use more energy for DRAM accesses compared to other benchmarks. Unlike the fully-digital PEs in TETRIS that perform a single operation in a cycle, BIHIWE uses MS-WAGGs which perform wide vectorized operations–crucial in BIHIWE to amortize the high cost of ADCs. As shown in [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 14
Figure 14. Figure 14: Design space exploration for MS-BPMACC. A/D conversion and the number of MACC units (n) are two main parameters of MS-BPMACC which define resolution and the sample rate of the ADC, determining its power [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Design space exploration for # core per cluster. [PITH_FULL_IMAGE:figures/full_fig_p011_15.png] view at source ↗
read the original abstract

Low-power potential of mixed-signal design makes it an alluring option to accelerate Deep Neural Networks (DNNs). However, mixed-signal circuitry suffers from limited range for information encoding, susceptibility to noise, and Analog to Digital (A/D) conversion overheads. This paper aims to address these challenges by offering and leveraging the insight that a vector dot-product (the basic operation in DNNs) can be bit-partitioned into groups of spatially parallel low-bitwidth operations, and interleaved across multiple elements of the vectors. As such, the building blocks of our accelerator become a group of wide, yet low-bitwidth multiply-accumulate units that operate in the analog domain and share a single A/D converter. The low-bitwidth operation tackles the encoding range limitation and facilitates noise mitigation. Moreover, we utilize the switched-capacitor design for our bit-level reformulation of DNN operations. The proposed switched-capacitor circuitry performs the group multiplications in the charge domain and accumulates the results of the group in its capacitors over multiple cycles. The capacitive accumulation combined with wide bit-partitioned operations alleviate the need for A/D conversion per operation. With such mathematical reformulation and its switched-capacitor implementation, we define a 3D-stacked microarchitecture, dubbed BIHIWE.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper proposes a bit-partitioned reformulation of vector dot-products for DNN acceleration, enabling groups of low-bitwidth analog multiply-accumulate operations that share a single A/D converter. It describes a switched-capacitor implementation for charge-domain group multiplications with capacitive accumulation across cycles, and defines a 3D-stacked microarchitecture (BIHIWE) intended to reduce per-operation A/D overheads while addressing encoding range and noise issues via low-bitwidth operations.

Significance. If the claims on accuracy preservation and overhead reduction hold under realistic noise and process variation, the approach could enable more efficient mixed-signal DNN accelerators by minimizing A/D conversions through interleaved bit-partitioned charge-domain accumulation. The switched-capacitor reformulation is a concrete implementation idea that merits further exploration if supported by analysis.

major comments (2)
  1. [Abstract] Abstract: The central claims regarding noise mitigation, encoding range handling, and A/D overhead reduction via low-bitwidth bit-partitioned operations and interleaved capacitive accumulation are presented at a high level only, with no quantitative results, error analysis, simulations, circuit derivations, or accuracy evaluations provided to support them.
  2. [Abstract (paragraph on insight and implementation)] The weakest assumption—that low-bitwidth analog operations combined with switched-capacitor accumulation can maintain sufficient accuracy without per-operation A/D conversions—is not accompanied by any supporting derivation, noise model, or empirical validation in the manuscript.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the major comments point by point below, agreeing where additional support is needed and outlining revisions.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claims regarding noise mitigation, encoding range handling, and A/D overhead reduction via low-bitwidth bit-partitioned operations and interleaved capacitive accumulation are presented at a high level only, with no quantitative results, error analysis, simulations, circuit derivations, or accuracy evaluations provided to support them.

    Authors: We agree that the abstract presents the claims at a high level. The manuscript body provides the bit-partitioned reformulation of dot-products, the switched-capacitor implementation details, and the 3D-stacked microarchitecture definition. In revision we will expand the abstract to incorporate key quantitative estimates (such as A/D conversion reduction factors) drawn from the analysis already present in the paper. revision: yes

  2. Referee: [Abstract (paragraph on insight and implementation)] The weakest assumption—that low-bitwidth analog operations combined with switched-capacitor accumulation can maintain sufficient accuracy without per-operation A/D conversions—is not accompanied by any supporting derivation, noise model, or empirical validation in the manuscript.

    Authors: The referee correctly notes that the accuracy claim requires explicit support. The current manuscript argues qualitatively that low-bitwidth operations mitigate encoding-range and noise issues but does not include a noise model or derivation. We will add an analytical noise model and supporting derivation in the revised manuscript. revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation is self-contained

full rationale

The paper presents a novel architectural proposal that reformulates vector dot-products as interleaved bit-partitioned low-bitwidth analog operations implemented via switched-capacitor circuits, leading to the BIHIWE microarchitecture. No load-bearing step reduces by construction to fitted parameters, self-definitions, or self-citation chains; the central claims introduce independent design elements (group MAC units sharing A/D, capacitive accumulation over cycles) whose validity rests on the stated circuit properties rather than prior outputs of the same work. The provided abstract and description contain no equations or citations that exhibit the enumerated circular patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract supplies no explicit free parameters, axioms, or invented entities; insufficient information to identify any.

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