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arxiv: 1907.02969 · v1 · pith:BCQQPUO4new · submitted 2019-07-05 · ⚛️ physics.ins-det

Prototype of a transient waveform recording ASIC

Jiajun Qin , Lei Zhao , Boyu Cheng , Han Chen , Yuxiang Guo , Shubin Liu , Qi An This is my paper

Pith reviewed 2026-05-25 01:57 UTC · model grok-4.3

classification ⚛️ physics.ins-det
keywords ASICSwitched Capacitor ArraySCAwaveform recordingtiming precisionWilkinson ADCCMOS prototype
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The pith

This ASIC prototype achieves timing precision better than 15 ps RMS through timing interval calibration.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper describes the design and testing of a two-channel transient waveform recording ASIC using switched capacitor array technology. Each channel has 128 samples, a 12-bit Wilkinson ADC, and supports serial readout. Tests confirm a 1 V voltage range, about 450 MHz analog bandwidth, and sampling rates from 0.076 to 3.2 Gsps. With calibration of sampling intervals, the timing precision reaches better than 15 ps RMS, which would allow more accurate waveform timing in applications like particle physics detectors.

Core claim

The ASIC based on the Switched Capacitor Array architecture demonstrates adjustable sampling speeds up to 3.2 Gsps and, after careful calibration of timing intervals between samples, achieves a timing precision better than 15 ps RMS.

What carries the argument

Switched Capacitor Array (SCA) with 128-sample depth per channel and Wilkinson ADC, using timing interval calibration to improve resolution.

If this is right

  • Full 1 V signal voltage range is available for recording.
  • Input analog bandwidth reaches approximately 450 MHz.
  • Sampling speed is adjustable from 0.076 to 3.2 Gsps.
  • The device supports serial data readout for the recorded waveforms.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Such timing precision could improve event reconstruction in high-energy physics experiments.
  • Integration with other detector systems might enable better synchronization across multiple channels.
  • Further scaling to more channels could be tested for larger detector arrays.

Load-bearing premise

The timing calibration procedure fully accounts for all variations in sampling intervals and the test measurements accurately represent the chip's performance under operational conditions.

What would settle it

An independent measurement of the timing resolution under realistic operating conditions that exceeds 15 ps RMS would disprove the claim.

Figures

Figures reproduced from arXiv: 1907.02969 by Boyu Cheng, Han Chen, Jiajun Qin, Lei Zhao, Qi An, Shubin Liu, Yuxiang Guo.

Figure 7
Figure 7. Figure 7: A stable sampling rate ranging from 76 Msps [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
read the original abstract

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 {\mu}m CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The manuscript presents the design and test results of a two-channel prototype transient waveform recording ASIC in 0.18 μm CMOS using a Switched Capacitor Array (SCA) architecture with 128-sample depth per channel, a 12-bit Wilkinson ADC, and serial readout. Reported performance includes a 1 V signal range, ~450 MHz analog bandwidth, adjustable sampling rates from 0.076 to 3.2 Gsps, and a timing precision better than 15 ps RMS after careful calibration of sampling intervals.

Significance. If the timing-precision result is substantiated with reproducible calibration details and representative test conditions, the work would provide a useful incremental contribution to SCA-based waveform digitizers for applications such as particle-physics instrumentation or time-of-flight measurements, demonstrating competitive performance in a standard CMOS process.

major comments (1)
  1. [Abstract] Abstract: the central claim that timing precision is 'proved to be better than 15 ps RMS' after 'careful calibration' is load-bearing, yet the abstract (and, per the provided stress-test note, the manuscript) supplies no description of the calibration algorithm, the test waveform, the statistical extraction method for the RMS figure, or cross-checks against temperature drift, supply variation, or capacitor mismatch. Without these specifics the claim cannot be evaluated.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed review and constructive comments on our manuscript. We address the major comment point by point below and will incorporate revisions as indicated.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that timing precision is 'proved to be better than 15 ps RMS' after 'careful calibration' is load-bearing, yet the abstract (and, per the provided stress-test note, the manuscript) supplies no description of the calibration algorithm, the test waveform, the statistical extraction method for the RMS figure, or cross-checks against temperature drift, supply variation, or capacitor mismatch. Without these specifics the claim cannot be evaluated.

    Authors: We agree that the timing-precision result requires more supporting detail to allow independent evaluation. The current manuscript text is concise on this point and does not include the requested elements. In the revised version we will add a dedicated subsection describing the calibration algorithm, the test waveform and setup, the statistical procedure used to extract the RMS value, and any cross-checks performed for temperature, supply, or mismatch effects. We will also revise the abstract to indicate that these details are now provided in the body of the paper. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental hardware measurements with no derivations or fitted predictions

full rationale

The paper reports ASIC design, fabrication, and bench measurements of an SCA-based waveform recorder. The timing precision claim (<15 ps RMS) is presented as a direct experimental outcome after 'careful calibration' of sampling intervals; no equations, first-principles derivations, parameter fits, or predictions appear in the abstract or described content. No self-citations, uniqueness theorems, or ansatzes are invoked. The work is self-contained as a prototype characterization report; the central result does not reduce to its own inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The paper describes an experimental hardware prototype without any mathematical derivations or models that introduce free parameters, axioms, or invented entities.

pith-pipeline@v0.9.0 · 5677 in / 979 out tokens · 36193 ms · 2026-05-25T01:57:36.058499+00:00 · methodology

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Reference graph

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