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REVIEW 5 major objections 6 minor 37 references

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads

T0 review · 5 major / 6 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read A bottom-up decomposition of FFT, GEMM, and QR into primitives, implemented in Verilog, Chisel, and HLS, reveals where the tools diverge in achievable frequency and resource use.

desk verdict A genuine methodology contribution—primitive-level decomposition plus automated achievable-frequency search—whose quantitative evidence is too uncontrolled and incomplete to support the tool-divergence claims as stated. read the letter →

arxiv 2509.09774 v1 pith:BKVOA57P submitted 2025-09-11 cs.AR

Doru Thom Popovici , Mario Vega , Angelos Ioannou , Fabien Chaix , Dania Mosuli , Blair Reasoner , Tan Nguyen , Xiaokun Yang
show 1 more author
John Shalf
This is my paper · ORCID
classification cs.AR
keywords hardwaredesignlanguageshigh-levelsynthesisChiselVerilogFPGAfrequencyautotuningkerneldecompositiondivergenceanalysis
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper is trying to establish that end-to-end benchmark comparisons of hardware design tools are too coarse, and that a better way is to decompose mathematical kernels into reusable primitives, implement each primitive in Verilog, Chisel, and Vivado HLS, and then automatically search for the highest achievable frequency at every level. If correct, designers can pinpoint whether an inefficiency comes from a single building block or from how blocks are assembled, and tool developers can see exactly where code generation diverges. The paper applies this methodology to FFT, GEMM, and QR factorization and reports concrete divergence patterns, but its central claim is the methodology itself, not a winner among the tools.

What carries the argument

The central mechanism is the pairing of primitive-level decomposition with an automated achievable-frequency autotuner. The autotuner iteratively sets a target frequency, runs synthesis and implementation, reads the worst negative slack (WNS), and computes the achievable frequency as fa[i] = f[i] / (1 - WNS[i] * f[i]), then stochastically picks the next target frequency. This loop produces a frequency-resource frontier for each design at each decomposition level, turning tool comparison into a searchable design-space exploration rather than a single end-to-end benchmark.

What would settle it

A third-party replication in which each primitive and algorithm is implemented in Verilog, Chisel, and HLS by different engineers given equal time, targeting the same FPGA and using the same autotuner, should reproduce the main ordering: Verilog at the highest frequency, HLS at the highest resource cost for wide streaming. If the ordering flips or disappears under matched effort, the divergences are implementation artifacts rather than tool-level properties.

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Extended reading notes

Core claim

The paper claims that a hierarchical decomposition of kernels into primitives—multiply-accumulate arrays, butterfly units, permutation units, pointwise operations, reduction trees, and AXPY operations—combined with an automated frequency-search loop, produces fairer and more granular comparisons among hardware design tools than the full-application benchmarks found in prior work. It reports that for small streaming widths all three implementations consume similar resources, with Verilog consistently reaching higher frequencies; as streaming width grows, HLS requires progressively more resources in compute-heavy primitives and in GEMM and FFT assemblies, while the QR factorization converges a

Load-bearing premise

The load-bearing premise is that the three hand-written designs are equally mature and comparable representatives of their tools; the paper states the implementations were made by hand with efficient Verilog as the focus, but it does not control for author effort or optimization quality, so the observed divergences could reflect implementer skill rather than tool capability.

Editorial extensions

If this is right

  • Designers can attribute a performance or resource gap to a specific primitive rather than to the whole application, making optimization effort more targeted.
  • Tool developers get a direct view of which constructs—such as permutation units or streaming interfaces—cause divergence in frequency or LUT usage.
  • The same primitive decomposition can be applied to other kernels, since the building blocks (MAC, butterfly, permutation, pointwise, reduction, AXPY) are reusable across many HPC computations.
  • Automated achievable-frequency search removes much of the manual timing-closure burden, making wide design-space exploration practical on clusters or single servers.
  • Because comparisons happen at every level, the methodology is more likely to expose tool-specific strengths than a single end-to-end number.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An extension beyond the paper: a controlled study that matches optimization effort across tools—or uses independently written designs from multiple engineers—would separate tool capability from implementer skill, which the present comparison does not do.
  • The primitive set could evolve into a de facto microbenchmark suite for hardware generation tools, similar to compiler test suites, if the decomposition is standardized across more kernels and tools.
  • The stochastic frequency-search loop could be paired with power, flip-flop, BRAM, or different FPGA families to test whether the observed divergence ordering holds beyond the single Alveo U280 target.
  • The QR result, where HLS detects redundant dot products, hints that data-path reuse is a key divergence point; the paper reports it but does not generalize it into a design rule.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper proposes a bottom-up methodology for comparing hardware design flows (Verilog, Chisel, Vivado HLS) on HPC kernels. It decomposes GEMM, FFT, and QR factorization into primitive building blocks (MAC arrays, butterfly units, permutation units, pointwise operations, reduction trees), hand-implements each primitive and algorithm in the three environments, and uses an automated Vivado-based loop to search for a reported 'achievable frequency' and to record resource utilization. The authors report synthesizing approximately 1,500 configurations and present a representative subset in Figure 8, concluding that the methodology identifies divergence points in code generation, resource usage, and performance. The paper explicitly frames the main contribution as the methodology itself, with the concrete results serving as a proof of concept.

Significance. If the methodology were rigorously validated, it would be a useful complement to existing end-to-end tool comparisons by isolating where high-level tools diverge from hand-written RTL. The hierarchical decomposition into reusable primitives is sensible, and the automated exploration harness (Slurm/shell support, JSON configuration, interactive plotting) is a practical infrastructure contribution. The authors are candid that the autotuning constants are arbitrary and that the quantitative results are only a proof of concept. However, the current empirical support is too thin and uncontrolled to sustain the tool-level divergence claims: the comparison is only as informative as the three hand-written implementations being compared, and the reported metrics lack variance information and verification evidence.

major comments (5)
  1. [§III-B, §IV-B] The comparisons treat the three hand-written implementations as representative of their respective tools, but no control exists for implementation quality, author effort, or microarchitecture equivalence. Section III-B states: 'we have focused on efficient Verilog implementations, we provided a similar Chisel implementation and finally we have made use of the features offered by HLS.' There is no third-party baseline, no optimization-maturity metric, and no standardization of pipeline depth, operator latency, or interface protocol. The consistent pattern in Fig. 8 (Verilog at higher frequency, HLS at higher LUT count) could therefore reflect differential designer skill or different algorithmic mappings rather than intrinsic tool capability. This load-bearing issue undermines the 'fairer comparisons' and 'divergence points' claims. The authors should either add controls (e.g., a public ba
  2. [§IV-A, Fig. 8] The quantitative support is weakened by the absence of error bars or run-to-run variance. The autotuner in Eq. (12) injects stochastic offsets U(0, F) and U(-α, α), yet each reported point appears to come from a single run. Vivado synthesis and implementation also exhibit run-to-run variability, so the observed differences between tools and configurations may be within the noise of the stochastic search. Additionally, 'a representative subset' of the ~1,500 implementations is shown without defining the selection criteria. Please report multiple trials per configuration, provide variance statistics, and describe how the subset was chosen.
  3. [§IV-B, Fig. 8(f)] For the QR factorization, the results are explicitly limited to the smallest configuration: 'Due to delays in generating the larger Verilog and Chisel designs, we only report results for the smallest configuration.' Contributions list an 'in-depth analysis' for the QR algorithm, but the evidence is a single point per tool. This is insufficient to support any cross-configuration or tool-level conclusion for QR. The authors should either complete the larger QR runs or scale back the QR claims to a single-case demonstration.
  4. [§III-B, stopping criterion 3] The stability stopping rule is printed as min_{j∈[i-W,i]} f_a[j] / min_{j∈[i-W,i]} f_a[j] < R. As written, the numerator and denominator are identical, so the ratio is always 1 and the criterion is vacuous for any R ≤ 1 (and trivially always true for R > 1). The intended ratio is presumably max/min over the window. Because this rule is part of the automated method that generates all frequency results, the typo needs correction, and the chosen W and R values should be reported.
  5. [§IV-B] The paper asserts functional correctness ('our implementations function correctly across the three languages and varying streaming widths') but does not describe any testbench, simulation, or equivalence-checking methodology. Resource and frequency numbers for incorrect or partially correct designs would be meaningless. Please describe the verification flow: test vectors, comparison against a software model, coverage of streaming widths and algorithms, and whether all ~1,500 configurations were verified.
minor comments (6)
  1. [Eq. (11)] The units for f and WNS are not stated. The formula f_a = f/(1 - wns·f) is dimensionally sensitive: if f is in MHz and wns in ns, a factor of 1000 is missing. Specify the units and verify the formula dimensionally.
  2. [Fig. 8 caption] Typo: 'LU Ts' should be 'LUTs'.
  3. [§III-A (DFT)] The sentence 'we focus on the streaming Fourier transform []' contains an empty citation placeholder.
  4. [§V] Typo: 'HPC e kernels' should be 'HPC kernels'.
  5. [Fig. 2(a)] The SystemVerilog snippet shows 'generate' but not the matching 'endgenerate'; the ellipsis placement is confusing. Consider showing complete synthesizable code or indicating omitted lines more clearly.
  6. [§IV-A] The paper says 'approximately 1500 implementations' here and 'nearly 1,500 designs' in the conclusion; the exact count and the configuration grid (which parameters were swept, how many per benchmark) should be stated precisely.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the frequency search and decomposition comparisons are self-contained; the only self-citation is a non-load-bearing design reference.

full rationale

The paper's central derivation chain is methodological rather than predictive. The achievable-frequency update (Eq. 11) is the standard WNS-based timing correction, and the stochastic next-frequency rule (Eq. 12) is an explicitly heuristic search step whose constants are admitted to be 'chosen arbitrarily' — not fitted to the reported outcomes. The algorithmic decompositions (GEMM to AXPY+reduction, FFT to butterfly+twiddle+permute, QR to pointwise+reduction+AXPY) are derived from the displayed equations (Eqs. 7–10) and standard references [29,30,32,33,35–37]; no prediction is defined in terms of its own output. The only self-citation is [34], a prior streaming-FFT paper by overlapping authors, but it is used only as a recommended reference for details ('we recommend the reader peruse the following works [34]–[36]') and is not invoked to constrain or justify a result. The uncontrolled-implementation-quality concern raised by a skeptical reader is a threat to external validity of the tool comparison, not circularity: it concerns whether the hand-written Verilog/Chisel/HLS files are equally optimized, which no equation in the paper defines into existence. Accordingly no circular step meets the evidentiary bar.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central claim rests on a small set of tool-behavior assumptions and an unverified comparability assumption about the three hand-written designs. The autotuner constants alpha, F, R, W are free parameters chosen arbitrarily, which is fine for a proof of concept but limits the reported frequency numbers. No new physical or architectural entities are introduced.

free parameters (5)
  • alpha in stochastic frequency update
    Used in Eq. 12 to scale the next frequency step; paper states 'constants alpha, F and R have been chosen arbitrarily' without values.
  • F (maximum random offset)
    Upper bound for the uniform random step when WNS > 0 in Eq. 12; chosen arbitrarily.
  • R (stability threshold)
    Threshold in the stopping criterion; chosen arbitrarily and the printed criterion is degenerate because numerator and denominator are identical.
  • W (stability window)
    Window size in the stability check 'min_{j in [i-W,i]} f_a[j]'; not given a numeric value.
  • F_MAX (system frequency cap) = not stated
    Stopping bound in Eq. 12; depends on target board, value not reported for Alveo U280.
assumptions (5)
  • domain assumption Vivado's WNS report accurately predicts the maximum achievable clock frequency given by Eq. 11.
    The automated search treats f_a[i] = f[i]/(1 - wns[i]*f[i]) as the true achievable frequency; this linear-slack model is an approximation of tool behavior, Section III-B.
  • domain assumption The hand-written Verilog, Chisel and HLS designs are comparable in optimization effort and algorithm structure, so differences measure tool capability.
    Section III-B states 'we focused on efficient Verilog implementations, we provided a similar Chisel implementation'; no effort metric or third-party implementation is used to validate comparability.
  • domain assumption A single Alveo U280 board and default Vivado 2024.1 strategies yield representative resource/frequency results.
    Experiments target one FPGA with default strategies, Section IV-A; no cross-board or rerun variability is reported.
  • domain assumption The three kernel implementations are functionally correct.
    Section IV.B asserts 'implementations function correctly' but no testbench or verification procedure is described.
  • domain assumption The algorithm decompositions (Cooley-Tukey with streaming, column-scaling GEMM, Householder QR) map faithfully onto the chosen primitives.
    Section III-A defines the decomposition; the framework's value depends on this mapping being representative of how these kernels are built.

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Cite this review

Pith. "Pith review of Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads." pith.science (2026). https://pith.science/paper/BKVOA57P

@misc{pith2026250909774,
  author       = {Pith},
  title        = {Pith review of: Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BKVOA57P}},
  note         = {Machine review of arXiv:2509.09774}
}
read the original abstract

Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has traditionally been a labor-intensive task. These accelerators typically require low-level programming in Verilog or other hardware description languages, along with significant manual optimization effort. Recently, to alleviate this challenge, high-level hardware design tools like Chisel and High-Level Synthesis have emerged. However, as with any compiler, some of the generated hardware may be suboptimal compared to expert-crafted designs. Understanding where these inefficiencies arise is crucial, as it provides valuable insights for both users and tool developers. In this paper, we propose a methodology to hierarchically decompose mathematical kernels - such as Fourier transforms, matrix multiplication, and QR factorization - into a set of common building blocks or primitives. Then the primitives are implemented in the different programming environments, and the larger algorithms get assembled. Furthermore, we employ an automatic approach to investigate the achievable frequency and required resources. Performing this experimentation at each level will provide fairer comparisons between designs and offer guidance for both tool developers and hardware designers to adopt better practices.

Figures

Figures reproduced from arXiv: 2509.09774 by the authors.

Figure 1
Figure 1. Array of multiply and accumulate operations. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Implementing an array of Multiply and Accumulate (MAC) operations between three vectors [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Our overall approach decomposes kernels such as Fourier transforms, matrix multiplication, and QR factorization into primitives, implemented with [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: This is the family of butterfly units. The left figure outlines a Fourier [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Two implementations for performing a transposition of a matrix of [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: The structure of the three main algorithms under evaluation: 1) the streaming Fourier transform, 2) the matrix-matrix multiplication and 3) the QR [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: The toolflow for autotuning and comparing hardware accelerator [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Plots showing the achievable frequency on the [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]

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