Paper Citation Record · LEDGER

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

As of 21 August 2026, this Paper Citation Record lists 26 of 26 outbound references and 1 inbound Pith citation observation for arXiv:2505.01107.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2505.01107 v1

Coverage vector

measured 26 of 26 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-16T04:30:06.801255Z

measured 27 of 27 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-21T06:32:19.484+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-05-10T04:28:31.416096Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-11T11:56:19.968828Z

Reference resolution

26 of 26 outbound references displayed

verified exact0
verified fuzzy25
unresolved1
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation b7ad65c3-b368-44f1-a092-9d1443469ef5 · outbound

This paper cites Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.172209Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 767b6802-c50d-4ec9-8550-b0ab199f4ad9 · outbound

This paper cites S2 Engine: A novel systolic architecture for sparse convolutional neural networks,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures S2 Engine: A novel systolic architecture for sparse convolutional neural networks,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.160467Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation ffe99b70-6efe-4d1f-adbf-f6fa11a1e5d8 · outbound

This paper cites AI and memory wall,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures AI and memory wall,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.147911Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 1d505cc5-bdbf-4d6b-a17e-6896d90dbe7b · outbound

This paper cites PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.136120Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation f60b27e9-8f3b-4a58-88ab-063ed4c6706b · outbound

This paper cites NAND-SPIN-based processing-in-MRAM ar- chitecture for convolutional neural network acceleration,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures NAND-SPIN-based processing-in-MRAM ar- chitecture for convolutional neural network acceleration,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.122624Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation c0b621f1-ebb1-4232-a7d8-f2dcedd5c2a3 · outbound

This paper cites DDC-PIM: Efficient algorithm/architecture co-design for doubling data capacity of SRAM-based processing-in- memory,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures DDC-PIM: Efficient algorithm/architecture co-design for doubling data capacity of SRAM-based processing-in- memory,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.109348Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 04b13226-0e98-4af6-8859-19a53e12e0bc · outbound

This paper cites ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.096087Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 120a11d8-cbb7-4924-9dab-c64e70c48bd8 · outbound

This paper cites PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures PUMA: A programmable ultra-efficient memristor-based accelerator for machine learning inference,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.082685Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 1efb6825-37ba-4724-9b90-e1354a67eb67 · outbound

This paper cites 16.3 a 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures 16.3 a 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.069492Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 89faeaa4-e2b5-4210-ac67-ee56a7dfa218 · outbound

This paper cites 16.4 an 89TOPS/W and 16.3 TOPS/mm 2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures 16.4 an 89TOPS/W and 16.3 TOPS/mm 2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.056018Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 7a5cc81e-3eaa-4690-bfa4-568c8a993bb4 · outbound

This paper cites A 1.041-Mb/MM 2 27.38-TOPS/W signed-int8 dynamic-logic-based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and em- bedded applications,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures A 1.041-Mb/MM 2 27.38-TOPS/W signed-int8 dynamic-logic-based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and em- bedded applications,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.042177Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 4857933e-265b-4cee-8214-d62e493f2744 · outbound

This paper cites Towards efficient sram-pim architecture design by exploiting unstructured bit-level sparsity,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Towards efficient sram-pim architecture design by exploiting unstructured bit-level sparsity,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.028648Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 9d17482c-d644-40a2-9f87-de3a4db098df · outbound

This paper cites PIMulator-NN: An event-driven, cross-level simula- tion framework for processing-in-memory-based neural network accel- erators,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures PIMulator-NN: An event-driven, cross-level simula- tion framework for processing-in-memory-based neural network accel- erators,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.014371Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 948dfa2c-268f-4347-90cd-e99238729db2 · outbound

This paper cites A simulation framework for memristor-based heterogeneous computing architectures,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures A simulation framework for memristor-based heterogeneous computing architectures,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:07.000666Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 66b840dc-c0d9-4632-b1cc-7fd57295ab41 · outbound

This paper cites Neurosim v1. 4: Extending technology support for digital compute-in-memory toward 1nm node,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Neurosim v1. 4: Extending technology support for digital compute-in-memory toward 1nm node,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.986941Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 47431cf2-0dfb-49e2-9ce2-0fb0e5327353 · outbound

This paper cites MNSIM 2.0: A behavior-level modeling tool for processing-in-memory architectures,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures MNSIM 2.0: A behavior-level modeling tool for processing-in-memory architectures,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.974597Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 30da9f26-1624-414f-a471-1c80b3e7834b · outbound

This paper cites OCC: An automated end-to- end machine learning optimizing compiler for computing-in-memory,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures OCC: An automated end-to- end machine learning optimizing compiler for computing-in-memory,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.962244Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 2e6a76b0-d70d-4338-b3a0-131b36301045 · outbound

This paper cites PIMCOMP: A universal compilation framework for crossbar-based PIM DNN ac- celerators,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures PIMCOMP: A universal compilation framework for crossbar-based PIM DNN ac- celerators,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.950020Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation f72f61b4-9388-4e0a-a9d3-a86e31f12f66 · outbound

This paper cites CIM-MLC: A multi-level compilation stack for computing-in-memory accelerators,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures CIM-MLC: A multi-level compilation stack for computing-in-memory accelerators,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.936213Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation d8d7c155-5328-4f7c-85b7-deb955eb99e0 · outbound

This paper cites Challenges and trends of SRAM-based computing-in-memory for AI edge devices,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Challenges and trends of SRAM-based computing-in-memory for AI edge devices,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.922154Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 52972016-7622-46ae-b0e8-36d2301cef79 · outbound

This paper cites AutoDCIM: An automated digital CIM compiler,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures AutoDCIM: An automated digital CIM compiler,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.907635Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 2be53341-75f1-4b01-a55c-b33804961886 · outbound

This paper cites ReDCIM: Reconfigurable digital computing-in-memory processor with unified FP/INT pipeline for cloud AI acceleration,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures ReDCIM: Reconfigurable digital computing-in-memory processor with unified FP/INT pipeline for cloud AI acceleration,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.891999Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation a8a3ec3b-a92e-4661-b523-f6ffd04b528c · outbound

This paper cites 16.7 A 40- 310TOPS/W SRAM-based all-digital up to 4b in-memory computing multi-tiled NN accelerator in FD-SOI 18nm for deep-learning edge applications,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures 16.7 A 40- 310TOPS/W SRAM-based all-digital up to 4b in-memory computing multi-tiled NN accelerator in FD-SOI 18nm for deep-learning edge applications,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.877694Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 984ecafd-79be-46bb-9350-9371d7c4e22c · outbound

This paper cites MLIR: Scaling compiler infrastructure for domain specific computation,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures MLIR: Scaling compiler infrastructure for domain specific computation,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.863522Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation e6f87eb7-91b7-405c-99ab-4b418187bc42 · outbound

This paper cites an unresolved cited work.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Unresolved cited work

Reference 25

Resolution: unresolved; raw_fallback, observed 2026-08-16T04:30:06.849657Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation f3649b29-2993-497a-b92e-93b7ccd9e97f · outbound

This paper cites Noxim: An open, extensible and cycle-accurate network on chip simulator,.

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures Noxim: An open, extensible and cycle-accurate network on chip simulator,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T04:30:06.835628Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Pith citing papers

Observation 0201e22d-649b-4d59-85ae-d01028ad9789 · inbound

AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator cites this paper.

AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

Reference 15

Resolution: verified exact; arxiv_id, observed 2026-05-11T11:56:20.025955Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.