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REVIEW 3 major objections 6 minor 60 references

Design and Implementation of Washing Machine HUD Using FPGAs

T0 review · 3 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A Spartan-3E FPGA can run a complete washing-machine simulator and drive its own VGA heads-up display.

desk verdict A candid student project write-up with honest debugging details, but no research contribution and no evidence for the central VGA claim; fine as a lab report, not for peer review. read the letter →

arxiv 2506.11287 v1 pith:CKT6ZYXC submitted 2025-06-12 cs.AR

Norman Stites , D.G. Perera This is my paper · ORCID
classification cs.AR
keywords FPGAwashingmachinecontrollerfinitestateVGAheads-updisplaySpartan-3EVerilogrotaryencoder
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that an FPGA can run an entire appliance controller and show its state on a screen: a Spartan-3E board executes the wash-cycle logic and drives a VGA heads-up display in real time. The design sequences Fill, Wash, Drain, Rinse, Spin, and Hold states with a finite state machine, reads load size from a rotary encoder, and pauses on a door-open signal. The authors validate the design through testbench simulation and on-board demonstrations, reporting that it fits comfortably in the Spartan-3E's resources. If correct, the work demonstrates that a single low-cost FPGA can replace a microcontroller for this class of appliance and provide user feedback without a separate video processor.

What carries the argument

The argument rides on the top-level Verilog module wm_top.v and its three coordinated subsystems: an FSM that sequences the six wash states and owns the load-dependent timer counters; a rotary_filter.v module that synchronizes and decodes the encoder's quadrature signals into a one-clock direction pulse; and a vga_sync.v module that generates HSYNC, VSYNC, and pixel addressing for the 640x480 display. The VGA domain runs on a divided 25 MHz clock, and synchronizers bridge signals between the 50 MHz FSM domain and the 25 MHz display domain. The HUD maps the current FSM state to color-coded screen regions, which is what makes the machine's behavior visible to the user.

What would settle it

Load the finished bitstream onto a Spartan-3E board and connect it to a VGA monitor known to require the exact 25.175 MHz pixel clock; if the monitor reports 'mode not supported' or never locks to the HUD, the paper's display claim fails.

Watch

Extended reading notes

Core claim

The central claim is that a Spartan-3E FPGA, programmed in Verilog, can implement a complete washing-machine controller and its graphical interface in one device. A finite state machine governs the cycle with six states—Fill, Wash, Drain, Rinse, Spin, and Hold—where the timings in each state are scaled by the selected load size, small, medium, or large. A rotary encoder with a quadrature filter selects the load, mechanical buttons provide start, reset, and door commands, and a VGA controller driven at 25 MHz renders a color-coded HUD that reflects the current state. The paper reports that the integrated design used 65% of the Spartan-3E's logic slices and 10% of its block RAM, and that hardware demonstrations confirmed stable VGA output and correct state transitions including the door-open safety pause.

Load-bearing premise

The design assumes that a standard VGA monitor will accept a 25 MHz pixel clock even though the VESA specification for 640x480 at 60 Hz calls for 25.175 MHz.

Editorial extensions

If this is right

  • A single FPGA can handle appliance sequencing, input debouncing, quadrature decoding, safety interlocks, and VGA output without a separate microcontroller.
  • The same finite state machine can be retimed for other cycle sequences or load profiles by changing counter values rather than hardware.
  • The rotary encoder filter and shift-register debouncing are reusable modules for any mechanical input on the Spartan-3E.
  • The color-coded HUD approach gives a template for adding graphical status displays to other FPGA-based demonstrations.
  • The design fits in about 65% of the Spartan-3E's logic slices, leaving room for added HUD features such as text or progress bars.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper: the HUD's pixel-to-state mapping suggests a general recipe for turning any FSM into a graphical display, so the same top-level split could be reused in student projects on other boards.
  • The only uncertain part of the design is monitor tolerance, so a straightforward follow-up would be to test the bitstream across several monitors and, if needed, generate a true 25.175 MHz pixel clock with a phase-locked loop.
  • The door-button edge-detect workaround is a practical lesson for FSM design, but it also points to a cleaner general pattern: treat safety inputs as pulses, not levels, unless the hardware enforces latching.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper reports a student FPGA project that implements a washing-machine controller on a Xilinx Spartan-3E board. The system comprises an FSM with Fill/Wash/Drain/Rinse/Spin/Hold states, a rotary encoder for load-size selection, debounced buttons for start/reset and door status, a timing module with load-dependent counters, and a VGA-based HUD that displays the current state. The manuscript gives a modular design narrative, partial Verilog fragments for rotary filtering and door logic, and qualitative claims of successful simulation and hardware validation. It also reports resource utilization of 65% of logic slices and 10% of block RAMs, and contains a large block of self-citations in the Future Work section.

Significance. If the system works as claimed, the paper would be a useful educational case study in FPGA-based embedded control and VGA interfacing. The design is clearly described at the block level, and the authors identify real practical issues such as switch debouncing, quadrature decoding, and UCF constraints. However, the significance is limited by the absence of reproducible evidence: no testbench waveforms, no VGA display captures, no synthesis or timing reports, and no measured verification of the non-standard VGA pixel clock. The central claim that the complete system operates on the Spartan-3E board therefore remains unverified. The paper's contribution is more of a project report than a validated design.

major comments (3)
  1. [Section 2.2 / Section 4.1] The VGA pixel-clock assumption is load-bearing and unverified. The text states that a 25 MHz clock divider is used because the VESA 640x480@60 spec calls for 25.175 MHz, and asserts that 'the VGA input can down clock and latch onto a slow clock if needed' without any reference or measurement. Section 4.1 then claims adherence to strict horizontal (31.77 us) and vertical (16.68 ms) sync intervals, but with a 25 MHz pixel clock and the usual 800 total pixels per line, the line period is 32 us, not 31.77 us; only 25.175 MHz yields the quoted numbers. If the target monitor rejects the 25 MHz timing, the HUD, a central deliverable, fails. The paper must either provide evidence that the specific monitor locked to the non-standard timing, or use a DCM/PLL to generate 25.175 MHz, and report the resulting measured sync intervals.
  2. [Sections 1.4, 3.5, 4.2] The claim of 'rigorous evaluation' is not supported by included evidence. The paper states that functional verification used simulation waveforms, state transitions, timer accuracy, and practical hardware demonstrations, but none of these artifacts appear in the manuscript: there are no testbench code listings, no waveform captures, no VGA display photographs or frame captures, no measured timings, and no synthesis or implementation reports. The only Verilog fragments are partial, and the exact counter values for vga_sync.v are not given. Consequently, an independent reader cannot confirm the central claim that the FSM, timer, rotary encoder, and VGA HUD work together on the Spartan-3E board.
  3. [Section 3.3 / Section 3.4] The synchronization between the 50 MHz FSM domain and the 25 MHz VGA domain is described only qualitatively. The text mentions 'implementing synchronizers to safely bridge signals' but provides no code or analysis for the state signals displayed on the HUD. The door-logic always block in Section 3.4 uses 'posedge clk_25MHz or posedge BTNS', treating a button input as an asynchronous clock event; this is not a standard synchronization structure and its behavior on the Spartan-3E is unclear. Without a concrete synchronizer design or a documented two-flop stage for the FSM state, the HUD could display metastable or stale state values. This needs to be addressed with code or an explicit timing analysis.
minor comments (6)
  1. [Section 2.1] The text says 'the UFC allows us to use only a 3-bit color encoder'; this should read 'UCF' (User Constraints File).
  2. [Section 3.4] The Verilog line 'assign direction = rotary_q2;' is not properly aligned or formatted, and the comment about 'counterclockwise or clockwise' should clarify the convention relative to ROTA/ROTB.
  3. [Section 4.1] The discussion of synthesis warnings ('I had quite a bit of warnings... due to a bit of lazy coding') is informal and does not identify which warnings appeared or why they were benign; a list of warning types would be more precise.
  4. [Figure 3] Figure 3 ('CRT Timing Example') is not referenced in the text and its source and relevance to the VGA timing discussion are unclear.
  5. [Section 4.3 / References] The Future Work section contains a large block of self-citations ([10]-[60]) that is not connected to specific technical claims in the paper; this reads as boilerplate and inflates the bibliography. It should be reduced to only the references actually used for specific statements.
  6. [Abstract / Section 1.1] The abstract and Section 1.1 repeat the same sentences nearly verbatim; the abstract should be a condensed, distinct summary.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the design is a constructed, hardware-validated implementation; self-citations in Future Work are not load-bearing.

full rationale

This paper is a design and implementation report, not a predictive derivation. The central claim that a Spartan-3E FPGA runs a washing machine FSM and renders a VGA HUD is supported by simulation testbenches, synthesis, and hardware demonstrations. The VGA timing follows VESA DMT specifications (with a 25 MHz pixel clock instead of 25.175 MHz, a correctness risk noted in Section 2.2, but not a circularity). The FSM states, debounce circuits, rotary encoder filter, and HUD color mapping are constructed components, not fitted parameters renamed as predictions. The only self-citations appear in Section 4.3 as an inspirational block asserting that FPGA-based systems are a good avenue for complex algorithms; this does not justify any specific design choice or claimed result in the paper. No equation reduces to its input by construction, no uniqueness theorem is imported from the authors, and no ansatz is smuggled in via citation. The derivation chain is self-contained and externally verified, so there is no significant circularity.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The paper is a design report, so the ledger captures hand-chosen timing values and unverified hardware assumptions. No new physical or computational entities are introduced.

free parameters (2)
  • Load-dependent wash cycle durations = not disclosed (small/medium/large)
    Section 2.1 says the timing module uses 32-bit counters to handle small, medium, and large loads with respective timings, but the actual durations are not given. These are hand-picked design values that determine FSM behavior.
  • Timer counter scaling to real-world timing = not specified
    Section 3.3 reports scaling timer counters to match real-world constraints after simulation mismatches; the scaling factors are not stated and act as fitted adjustments.
assumptions (3)
  • domain assumption VGA monitors tolerate a 25 MHz pixel clock instead of the VESA standard 25.175 MHz.
    Section 2.2 states the monitor 'can down clock and latch onto a slow clock if needed' without citing evidence.
  • domain assumption Shift-register debouncing and the Xilinx rotary encoder synchronizer fully remove mechanical jitter.
    Section 3.4 describes the approach qualitatively; no jitter measurements are provided.
  • domain assumption The FSM's safety rule (door switch can only open during spin states) matches the intended safety behavior.
    Section 3.4 introduces SW3_block to allow door opening only during spin; this is a design choice, not a derived requirement.

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Cite this review

Pith. "Pith review of Design and Implementation of Washing Machine HUD Using FPGAs." pith.science (2026). https://pith.science/paper/CKT6ZYXC

@misc{pith2026250611287,
  author       = {Pith},
  title        = {Pith review of: Design and Implementation of Washing Machine HUD Using FPGAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CKT6ZYXC}},
  note         = {Machine review of arXiv:2506.11287}
}
read the original abstract

In contemporary digital design education, practical field programmable gate array (FPGA) projects are indispensable for bridging theoretical concepts with real-world applications. This project focuses on developing a hardware-based simulation of a domestic washing machine controller using the Xilinx Spartan-3E development board. A critical component of the design is the graphical heads-up display (HUD), which renders real-time information about the machine's operational state and cycle selections via a VGA interface.

Figures

Figures reproduced from arXiv: 2506.11287 by the authors.

Figure 1
Figure 1. VGA UCF [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Spartan 3E Color Decoder The integrated top-level module (wm_top.v) orchestrates all subsystems, ensuring cohesive functionality under the specific constraints defined by the Spartan-3E development board in the user constraint file (spartan3e.ucf). 2.2 Design Flow The project adheres to a structured, iterative design process, beginning with initial requirements analysis that clearly defines washing cycle stages, tim… view at source ↗
Figure 3
Figure 3. CRT Timing Example Handling noisy quadrature signals from the rotary encoder posed challenges, prompting the development of a specialized rotary filter module (rotary_filter.v). This module decodes quadrature signals into clean pulses, reliably detecting direction based on the relative phase of the rotary signals, ensuring accurate load size selection. Transitioning FSM logic from simulation to hardware revealed mis… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: 640x480 Mode VGA Timings Rotary encoder jitter initially caused multiple increments per physical detent, which was effectively mitigated by introducing an input synchronizer based on the default Xilinx Spartan 3E demo code. reg [1:0] rotary_sync; reg rotary_q1, rotary_…

Discussion (0). Continue with ORCID to comment.

Reference graph

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    R. Raghavan and D.G. Perera, “A Fast and Scalable FPGA-Based Parallel Processing Architecture for K-Means Clustering for Big Data Analysis”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1-...

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    Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,

    D.G. Perera and Kin F. Li, “Parallel Computation of Similarity Measures Using an FPGA -Based Processor Array,” in Proceedings of 22nd IEEE International Conference on Advanced Information Networking and Applications, (AINA’08), pp. 955-962, Okinawa, Japan, March 2008

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    R. Raghavan, "A Fast and Scalable Hardware Architecture for K-Means Clustering for Big Data Analysis", MSc Thesis, (Supervisor Dr. Darshika G. Perera), Department of Electrical & Computer Engineering, University of Colorado Colorado Springs, CO, USA, May 2016

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    Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware

    D.G. Perera and K.F. Li, “Discrepancy in Execution Time: Static Vs. Dynamic Reconfigurable Hardware”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6- page manuscript, Victoria, BC, Canada, August 2024

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    D.G. Perera and Kin F. Li, “Similarity Computation Using Reconfigurable Embedded Hardware,” in Proceedings of 8th IEEE International Conference on Dependable, Autonomic, and Secure Computing (DASC’09), pp. 323-329, Chengdu, China, December 2009

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    Dynamic Partial Reconfigurable Hardware Architecture for Principal Component Analysis on Mobile and Embedded Devices

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    HDL Code Optimization: Impact on Hardware Implementations and CAD Tools

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    HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools

    I.D. Atwell and D.G. Perera, “HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools”, IEEE Pacific Rim Int. Conf. on Communications, Computers, and Signal Processing, (PacRim’24), 6- page manuscript, Victoria, BC, Canada, August 2024. 16

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    Towards Composing Optimized Bi -Directional Multi-Ported Memories for Next-Generation FPGAs

    S.N. Shahrouzi, A. Alkamil, and D.G. Perera, “Towards Composing Optimized Bi -Directional Multi-Ported Memories for Next-Generation FPGAs”, IEEE Access, Open Access Journal in IEEE, vol. 8, no. 1, pp. 91531- 91545, 14th May 2020

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    An Efficient Embedded Multi-Ported Memory Architecture for Next- Generation FPGAs

    S.N. Shahrouzi and D.G. Perera, “An Efficient Embedded Multi-Ported Memory Architecture for Next- Generation FPGAs”, in Proceedings of 28th Annual IEEE International Conferences on Application- Specific Systems, Architectures, and Processors, (ASAP’17), pp. 83-90, Seattle, WA,...

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    An Efficient FPGA-Based Memory Architecture for Compute-Intensive Applications on Embedded Devices

    S.N. Shahrouzi and D.G. Perera, “An Efficient FPGA-Based Memory Architecture for Compute-Intensive Applications on Embedded Devices”, in Proceedings of the IEEE Pacific Rim International Conference on Communications, Computers, and Signal Processing, (PacRim’17), pp. 1- 8, Vic...

    2017

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.